forked from M-Labs/artiq
354 lines
9.4 KiB
Python
354 lines
9.4 KiB
Python
import unittest
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from operator import itemgetter
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import os
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from fractions import Fraction
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from artiq import *
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from artiq.language.units import DimensionError
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from artiq.coredevice import comm_serial, core, runtime_exceptions, rtio
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from artiq.sim import devices as sim_devices
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no_hardware = bool(os.getenv("ARTIQ_NO_HARDWARE"))
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def _run_on_device(k_class, **parameters):
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comm = comm_serial.Comm()
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try:
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coredev = core.Core(comm=comm)
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k_inst = k_class(core=coredev, **parameters)
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k_inst.run()
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finally:
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comm.close()
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def _run_on_host(k_class, **parameters):
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coredev = sim_devices.Core()
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k_inst = k_class(core=coredev, **parameters)
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k_inst.run()
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class _Primes(AutoDB):
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class DBKeys:
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core = Device()
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output_list = Argument()
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maximum = Argument()
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@kernel
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def run(self):
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for x in range(1, self.maximum):
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d = 2
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prime = True
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while d*d <= x:
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if x % d == 0:
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prime = False
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break
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d += 1
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if prime:
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self.output_list.append(x)
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class _Misc(AutoDB):
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def build(self):
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self.input = 84
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self.inhomogeneous_units = []
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self.al = [1, 2, 3, 4, 5]
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self.list_copy_in = [2*Hz, 10*MHz]
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@kernel
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def run(self):
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self.half_input = self.input//2
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self.decimal_fraction = Fraction("1.2")
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self.inhomogeneous_units.append(1000*Hz)
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self.inhomogeneous_units.append(10*s)
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self.acc = 0
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for i in range(len(self.al)):
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self.acc += self.al[i]
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self.list_copy_out = self.list_copy_in
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self.unit_comp = [1*MHz for _ in range(3)]
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@kernel
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def dimension_error1(self):
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print(1*Hz + 1*s)
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@kernel
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def dimension_error2(self):
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print(1*Hz < 1*s)
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@kernel
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def dimension_error3(self):
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check_unit(1*Hz, "s")
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@kernel
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def dimension_error4(self):
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delay(10*Hz)
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class _PulseLogger(AutoDB):
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class DBKeys:
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core = Device()
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output_list = Argument()
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name = Argument()
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def _append(self, t, l, f):
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if not hasattr(self, "first_timestamp"):
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self.first_timestamp = t
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self.output_list.append((self.name, t-self.first_timestamp, l, f))
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def on(self, t, f):
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self._append(t, True, f)
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def off(self, t):
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self._append(t, False, 0)
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@kernel
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def pulse(self, f, duration):
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self.on(int(now().amount*1000000000), f)
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delay(duration)
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self.off(int(now().amount*1000000000))
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class _Pulses(AutoDB):
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class DBKeys:
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core = Device()
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output_list = Argument()
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def build(self):
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for name in "a", "b", "c", "d":
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pl = _PulseLogger(core=self.core,
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output_list=self.output_list,
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name=name)
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setattr(self, name, pl)
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@kernel
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def run(self):
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for i in range(3):
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with parallel:
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with sequential:
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self.a.pulse(100+i, 20*us)
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self.b.pulse(200+i, 20*us)
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with sequential:
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self.c.pulse(300+i, 10*us)
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self.d.pulse(400+i, 20*us)
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class _MyException(Exception):
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pass
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class _Exceptions(AutoDB):
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class DBKeys:
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core = Device()
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trace = Argument()
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@kernel
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def run(self):
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for i in range(10):
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self.trace.append(i)
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if i == 4:
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try:
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self.trace.append(10)
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try:
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self.trace.append(11)
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break
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except:
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pass
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else:
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self.trace.append(12)
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try:
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self.trace.append(13)
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except:
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pass
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except _MyException:
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self.trace.append(14)
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for i in range(4):
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try:
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self.trace.append(100)
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if i == 1:
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raise _MyException
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elif i == 2:
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raise IndexError
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except (TypeError, IndexError):
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self.trace.append(101)
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raise
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except:
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self.trace.append(102)
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else:
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self.trace.append(103)
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finally:
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self.trace.append(104)
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class _RPCExceptions(AutoDB):
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def build(self):
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self.success = False
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def exception_raiser(self):
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raise _MyException
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@kernel
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def do_not_catch(self):
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self.exception_raiser()
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@kernel
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def catch(self):
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try:
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self.exception_raiser()
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except _MyException:
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self.success = True
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@unittest.skipIf(no_hardware, "no hardware")
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class ExecutionCase(unittest.TestCase):
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def test_primes(self):
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l_device, l_host = [], []
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_run_on_device(_Primes, maximum=100, output_list=l_device)
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_run_on_host(_Primes, maximum=100, output_list=l_host)
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self.assertEqual(l_device, l_host)
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def test_misc(self):
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comm = comm_serial.Comm()
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try:
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coredev = core.Core(comm=comm)
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uut = _Misc(core=coredev)
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uut.run()
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self.assertEqual(uut.half_input, 42)
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self.assertEqual(uut.decimal_fraction, Fraction("1.2"))
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self.assertEqual(uut.inhomogeneous_units, [1000*Hz, 10*s])
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self.assertEqual(uut.acc, sum(uut.al))
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self.assertEqual(uut.list_copy_in, uut.list_copy_out)
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self.assertEqual(uut.unit_comp, [1*MHz for _ in range(3)])
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with self.assertRaises(DimensionError):
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uut.dimension_error1()
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with self.assertRaises(DimensionError):
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uut.dimension_error2()
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with self.assertRaises(DimensionError):
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uut.dimension_error3()
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with self.assertRaises(DimensionError):
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uut.dimension_error4()
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finally:
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comm.close()
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def test_pulses(self):
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l_device, l_host = [], []
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_run_on_device(_Pulses, output_list=l_device)
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_run_on_host(_Pulses, output_list=l_host)
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l_host = sorted(l_host, key=itemgetter(1))
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for channel in "a", "b", "c", "d":
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c_device = [x for x in l_device if x[0] == channel]
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c_host = [x for x in l_host if x[0] == channel]
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self.assertEqual(c_device, c_host)
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def test_exceptions(self):
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t_device, t_host = [], []
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with self.assertRaises(IndexError):
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_run_on_device(_Exceptions, trace=t_device)
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with self.assertRaises(IndexError):
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_run_on_host(_Exceptions, trace=t_host)
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self.assertEqual(t_device, t_host)
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def test_rpc_exceptions(self):
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comm = comm_serial.Comm()
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try:
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uut = _RPCExceptions(core=core.Core(comm=comm))
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with self.assertRaises(_MyException):
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uut.do_not_catch()
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uut.catch()
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self.assertTrue(uut.success)
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finally:
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comm.close()
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class _RTIOLoopback(AutoDB):
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class DBKeys:
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core = Device()
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i = Device()
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o = Device()
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npulses = Argument()
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def report(self, n):
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self.result = n
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@kernel
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def run(self):
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with parallel:
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with sequential:
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for i in range(self.npulses):
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delay(25*ns)
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self.o.pulse(25*ns)
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self.i.gate_rising(10*us)
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self.report(self.i.count())
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class _RTIOUnderflow(AutoDB):
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class DBKeys:
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core = Device()
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o = Device()
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@kernel
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def run(self):
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while True:
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delay(25*ns)
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self.o.pulse(25*ns)
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class _RTIOSequenceError(AutoDB):
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class DBKeys:
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core = Device()
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o = Device()
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@kernel
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def run(self):
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t = now()
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self.o.pulse(25*us)
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at(t)
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self.o.pulse(25*us)
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@unittest.skipIf(no_hardware, "no hardware")
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class RTIOCase(unittest.TestCase):
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# Connect channels 0 and 1 together for this test
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# (C11 and C13 on Papilio Pro)
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def test_loopback(self):
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npulses = 4
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comm = comm_serial.Comm()
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try:
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coredev = core.Core(comm=comm)
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uut = _RTIOLoopback(
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core=coredev,
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i=rtio.RTIOIn(core=coredev, channel=0),
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o=rtio.RTIOOut(core=coredev, channel=2),
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npulses=npulses
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)
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uut.run()
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self.assertEqual(uut.result, npulses)
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finally:
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comm.close()
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def test_underflow(self):
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comm = comm_serial.Comm()
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try:
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coredev = core.Core(comm=comm)
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uut = _RTIOUnderflow(
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core=coredev,
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o=rtio.RTIOOut(core=coredev, channel=2)
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)
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with self.assertRaises(runtime_exceptions.RTIOUnderflow):
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uut.run()
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finally:
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comm.close()
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def test_sequence_error(self):
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comm = comm_serial.Comm()
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try:
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coredev = core.Core(comm=comm)
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uut = _RTIOSequenceError(
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core=coredev,
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o=rtio.RTIOOut(core=coredev, channel=2)
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)
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with self.assertRaises(runtime_exceptions.RTIOSequenceError):
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uut.run()
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finally:
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comm.close()
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