This website requires JavaScript.
Explore
Help
Sign In
srenblad
/
artiq
Watch
1
Star
0
Fork
0
You've already forked artiq
forked from
M-Labs/artiq
Code
Pull Requests
Activity
424b2bfbd8
artiq
/
artiq
/
gateware
/
rtio
History
Robert Jordens
424b2bfbd8
rtio: describe rio and rio_phy domains a bit more
2017-06-17 12:21:07 +02:00
..
phy
Remove Pipistrello support
2017-05-15 17:17:44 +08:00
__init__.py
rtio: export DMA and CRIInterconnectShared
2016-12-01 16:30:29 +08:00
analyzer.py
make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads
2017-03-27 16:32:23 +08:00
cdc.py
drtio: use BlindTransfer for error reporting
2017-04-03 00:18:07 +08:00
core.py
rtio: describe rio and rio_phy domains a bit more
2017-06-17 12:21:07 +02:00
cri.py
cri: add note about clearing of o_data
2017-06-16 19:06:00 +02:00
dma.py
gateware: simplify the CRI arbiter to use a plain mux.
2017-04-05 15:09:19 +00:00
moninj.py
moninj: do not require a rsys clock domain
2017-02-20 15:52:48 +08:00
rtlink.py
rtio: add support for latency compensation in phy
2016-12-14 19:16:07 +01:00