Sebastien Bourdeauducq 2881d5f00a gateware: add RTIO clock generator		2015-07-02 18:20:26 +02:00
..
Makefile	doc: add sphinx infrastructure	2014-09-18 17:45:54 +08:00
conf.py	fix doc build	2015-06-06 00:55:48 +08:00
core_device_flash_storage.rst	flash_storage: refactor + unit tests + artiq_coreconfig.py CLI + doc	2015-05-27 18:06:12 +08:00
core_drivers_reference.rst	coredevice: rename rtio to ttl, integrated in+out driver, loopback on the same pin in tests	2015-05-02 10:35:21 +08:00
core_language_reference.rst	doc: fixes and add sync_struct docstrings	2015-01-19 19:20:14 +08:00
default_network_ports.rst	doc/manual: list core device port	2015-04-28 00:00:00 +08:00
developing_a_ndsp.rst	controllers: use --simulation for simulation	2015-06-29 13:04:01 +02:00
faq.rst	manual: fix faq item title about determining pyserial URL by serial number	2015-06-26 18:22:47 +02:00
fpga_board_ports.rst	gateware: add RTIO clock generator	2015-07-02 18:20:26 +02:00
getting_started.rst	manual: explain how to compile and flash the idle kernel	2015-05-29 17:38:23 +02:00
index.rst	flash_storage: refactor + unit tests + artiq_coreconfig.py CLI + doc	2015-05-27 18:06:12 +08:00
installing.rst	doc/manual/installing: minor cleanups	2015-06-19 08:10:33 +02:00
introduction.rst	README/manual: refactor intro	2015-03-23 18:49:07 -06:00
management_system.rst	doc/manual/management: add short descriptions of tools	2015-02-15 14:55:15 -07:00
ndsp_reference.rst	manual: minor fixes	2015-06-23 19:44:02 +00:00
protocols_reference.rst	doc/manual: add fire_and_forget	2015-07-01 22:37:12 +02:00
utilities.rst	artiq_coreconfig: better arg parsing	2015-06-18 17:07:20 +02:00