forked from M-Labs/artiq
Robert Jordens
01416bb0be
These are contributions of >= 30% or >= 20 lines (half-automated).
I hereby resubmit all my previous contributions to the ARTIQ project
under the following terms:
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Closes #130
Signed-off-by: Robert Jordens <jordens@gmail.com>
74 lines
2.6 KiB
Python
74 lines
2.6 KiB
Python
# Copyright (C) 2014, 2015 Robert Jordens <jordens@gmail.com>
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from artiq import *
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class PulseNotReceivedError(Exception):
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pass
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class TDR(EnvExperiment):
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"""Time domain reflectometer.
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From ttl2 an impedance matched pulse is send onto a coax
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cable with an open end. pmt0 (very short stub, high impedance) also
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listens on the transmission line near ttl2.
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When the forward propagating pulse passes pmt0, the voltage is half of the
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logic voltage and does not register as a rising edge. Once the
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rising edge is reflected at an open end (same sign) and passes by pmt0 on
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its way back to ttl2, it is detected. Analogously, hysteresis leads to
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detection of the falling edge once the reflection reaches pmt0 after
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one round trip time.
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This works marginally and is just a proof of principle: it relies on
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hysteresis at FPGA inputs around half voltage and good impedance steps,
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as well as reasonably low loss cable. It does not work well for longer
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cables (>100 ns RTT). The default drive strength of 12 mA and 3.3 V would
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be ~300 Ω but it seems 40 Ω series impedance at the output matches
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the hysteresis of the input.
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This is also equivalent to a loopback tester or a delay measurement.
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"""
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def build(self):
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self.attr_device("core")
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self.attr_device("pmt0")
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self.attr_device("ttl2")
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def run(self):
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n = 1000 # repetitions
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latency = 50e-9 # calibrated latency without a transmission line
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pulse = 1e-6 # pulse length, larger than rtt
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try:
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self.many(n, seconds_to_mu(pulse, self.core))
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except PulseNotReceivedError:
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print("to few edges: cable too long or wiring bad")
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else:
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print(self.t)
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t_rise = mu_to_seconds(self.t[0], self.core)/n - latency
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t_fall = mu_to_seconds(self.t[1], self.core)/n - latency - pulse
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print("round trip times:")
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print("rising: {:5g} ns, falling {:5g} ns".format(
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t_rise/1e-9, t_fall/1e-9))
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@kernel
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def many(self, n, p):
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t = [0 for i in range(2)]
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self.core.break_realtime()
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for i in range(n):
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self.one(t, p)
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self.t = t
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@kernel
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def one(self, t, p):
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t0 = now_mu()
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with parallel:
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self.pmt0.gate_both_mu(2*p)
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self.ttl2.pulse_mu(p)
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for i in range(len(t)):
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ti = self.pmt0.timestamp_mu()
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if ti <= 0:
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raise PulseNotReceivedError
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t[i] += ti - t0
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self.pmt0.count() # flush
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