forked from M-Labs/artiq
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@ -0,0 +1 @@
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artiq/_version.py export-subst
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@ -1,49 +0,0 @@
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---
|
||||
name: Bug report
|
||||
about: Report a bug in ARTIQ
|
||||
|
||||
---
|
||||
|
||||
<!-- Above are non-Markdown tags for Github auto-prompting issue type. Template based on pylint: https://raw.githubusercontent.com/PyCQA/pylint/master/.github/ISSUE_TEMPLATE/ -->
|
||||
|
||||
# Bug Report
|
||||
|
||||
<!-- Thanks for reporting a bug report to ARTIQ! You can also discuss issues and ask questions on IRC (the [#m-labs channel on freenode](https://webchat.freenode.net/?channels=m-labs) or on the [forum](https://forum.m-labs.hk). Please check Github/those forums to avoid posting a repeat issue.
|
||||
|
||||
Context helps us fix issues faster, so please include the following when relevant:
|
||||
-->
|
||||
|
||||
## One-Line Summary
|
||||
|
||||
Short summary.
|
||||
|
||||
## Issue Details
|
||||
|
||||
### Steps to Reproduce
|
||||
|
||||
1. Step 1.
|
||||
2. Step 2.
|
||||
3. Step 3.
|
||||
|
||||
### Expected Behavior
|
||||
|
||||
Behavior
|
||||
|
||||
### Actual (undesired) Behavior
|
||||
|
||||
* Text description
|
||||
* Log message, tracebacks, screen shots where relevant
|
||||
|
||||
### Your System (omit irrelevant parts)
|
||||
|
||||
* Operating System:
|
||||
* ARTIQ version: (with recent versions of ARTIQ, run ``artiq_client --version``)
|
||||
* Version of the gateware and runtime loaded in the core device: (in the output of ``artiq_coremgmt -D .... log``)
|
||||
* If using Conda, output of `conda list` (please submit as a file attachment, as this tends to be long)
|
||||
* Hardware involved:
|
||||
|
||||
<!--
|
||||
For in-depth information on bug reporting, see:
|
||||
|
||||
http://www.chiark.greenend.org.uk/~sgtatham/bugs.html https://developer.mozilla.org/en-US/docs/Mozilla/QA/Bug_writing_guidelines
|
||||
-->
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
---
|
||||
name: Feature request
|
||||
about: Suggest an idea for ARTIQ
|
||||
|
||||
---
|
||||
|
||||
<!--
|
||||
Hi there! Thank you for wanting to make ARTIQ better.
|
||||
|
||||
Before you submit this, make sure that this feature wasn't
|
||||
already requested or if it is not already implemented in the master branch.
|
||||
|
||||
Based on pylint: https://raw.githubusercontent.com/PyCQA/pylint/master/.github/ISSUE_TEMPLATE/2_Feature_request.md
|
||||
-->
|
||||
|
||||
# ARTIQ Feature Request
|
||||
|
||||
## Problem this request addresses
|
||||
|
||||
A clear and concise description of what the problem is.
|
||||
|
||||
## Describe the solution you'd like
|
||||
|
||||
A clear and concise description of what you want to happen.
|
||||
|
||||
## Additional context
|
||||
|
||||
Add any other context about the feature request here.
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
---
|
||||
name: Support question
|
||||
about: Questions about ARTIQ that are not covered in the documentation
|
||||
|
||||
---
|
||||
|
||||
# Question
|
||||
|
||||
<!--
|
||||
Make sure you check the ARTIQ documentation before posting a question.
|
||||
Don't forget you can search it!
|
||||
|
||||
Beta version: https://m-labs.hk/artiq/manual-beta/
|
||||
Stable version: https://m-labs.hk/artiq/manual/
|
||||
|
||||
The forum is also a very good place for questions: https://forum.m-labs.hk/
|
||||
Can also ask on IRC: https://webchat.freenode.net/?channels=m-labs or
|
||||
check mailing list archives: https://ssl.serverraum.org/lists-archive/artiq/
|
||||
|
||||
Remember: if you have this question then others probably do too! The best way of thanking the people who help you with this issue is to contribute to ARTIQ by submitting a pull request to update the documentation.
|
||||
-->
|
||||
|
||||
## Category: FILL_IN
|
||||
|
||||
<!-- One-word category this question falls into: GUI, installation/setup, devices, development, documentation, etc. -->
|
||||
|
||||
## Description
|
||||
|
||||
Question text
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
<!--
|
||||
|
||||
Thank you for submitting a PR to ARTIQ!
|
||||
|
||||
To ease the process of reviewing your PR, do make sure to complete the following boxes.
|
||||
|
||||
You can also read more about contributing to ARTIQ in this document:
|
||||
https://github.com/m-labs/artiq/blob/master/CONTRIBUTING.rst#contributing-code
|
||||
|
||||
Based on https://raw.githubusercontent.com/PyCQA/pylint/master/.github/PULL_REQUEST_TEMPLATE.md
|
||||
-->
|
||||
|
||||
# ARTIQ Pull Request
|
||||
|
||||
## Description of Changes
|
||||
|
||||
### Related Issue
|
||||
|
||||
<!--
|
||||
If this PR fixes a particular issue, use the following to automatically close that issue
|
||||
once this PR gets merged:
|
||||
|
||||
Closes #XXX
|
||||
-->
|
||||
|
||||
## Type of Changes
|
||||
|
||||
<!-- Leave ONLY the corresponding lines for the applicable type of change: -->
|
||||
| | Type |
|
||||
| ------------- | ------------- |
|
||||
| ✓ | :bug: Bug fix |
|
||||
| ✓ | :sparkles: New feature |
|
||||
| ✓ | :hammer: Refactoring |
|
||||
| ✓ | :scroll: Docs |
|
||||
|
||||
## Steps (Choose relevant, delete irrelevant before submitting)
|
||||
|
||||
### All Pull Requests
|
||||
|
||||
- [x] Use correct spelling and grammar.
|
||||
- [ ] Update [RELEASE_NOTES.rst](../RELEASE_NOTES.rst) if there are noteworthy changes, especially if there are changes to existing APIs.
|
||||
- [ ] Close/update issues.
|
||||
- [ ] Check the copyright situation of your changes and sign off your patches (`git commit --signoff`, see [copyright](../CONTRIBUTING.rst#copyright-and-sign-off)).
|
||||
|
||||
### Code Changes
|
||||
|
||||
- [ ] Run `flake8` to check code style (follow PEP-8 style). `flake8` has issues with parsing Migen/gateware code, ignore as necessary.
|
||||
- [ ] Test your changes or have someone test them. Mention what was tested and how.
|
||||
- [ ] Add and check docstrings and comments
|
||||
- [ ] Check, test, and update the [unittests in /artiq/test/](../artiq/test/) or [gateware simulations in /artiq/gateware/test](../artiq/gateware/test)
|
||||
|
||||
### Documentation Changes
|
||||
|
||||
- [ ] Check, test, and update the documentation in [doc/](../doc/). Build documentation (`cd doc/manual/; make html`) to ensure no errors.
|
||||
|
||||
### Git Logistics
|
||||
|
||||
- [ ] Split your contribution into logically separate changes (`git rebase --interactive`). Merge/squash/fixup commits that just fix or amend previous commits. Remove unintended changes & cleanup. See [tutorial](https://www.atlassian.com/git/tutorials/rewriting-history/git-rebase).
|
||||
- [ ] Write short & meaningful commit messages. Review each commit for messages (`git show`). Format:
|
||||
```
|
||||
topic: description. < 50 characters total.
|
||||
|
||||
Longer description. < 70 characters per line
|
||||
```
|
||||
|
||||
### Licensing
|
||||
|
||||
See [copyright & licensing for more info](https://github.com/m-labs/artiq/blob/master/CONTRIBUTING.rst#copyright-and-sign-off).
|
||||
ARTIQ files that do not contain a license header are copyrighted by M-Labs Limited and are licensed under LGPLv3+.
|
||||
|
|
@ -29,7 +29,6 @@ __pycache__/
|
|||
/repository/
|
||||
/results
|
||||
/last_rid.pyon
|
||||
/dataset_db.mdb
|
||||
/dataset_db.mdb-lock
|
||||
/dataset_db.pyon
|
||||
/device_db*.py
|
||||
/test*
|
||||
|
|
|
|||
|
|
@ -7,8 +7,9 @@ Reporting Issues/Bugs
|
|||
|
||||
Thanks for `reporting issues to ARTIQ
|
||||
<https://github.com/m-labs/artiq/issues/new>`_! You can also discuss issues and
|
||||
ask questions on IRC (the #m-labs channel on OFTC), the `Mattermost chat
|
||||
<https://chat.m-labs.hk>`_, or on the `forum <https://forum.m-labs.hk>`_.
|
||||
ask questions on IRC (the `#m-labs channel on freenode
|
||||
<https://webchat.freenode.net/?channels=m-labs>`_) or on the `mailing list
|
||||
<https://ssl.serverraum.org/lists/listinfo/artiq>`_.
|
||||
|
||||
The best bug reports are those which contain sufficient information. With
|
||||
accurate and comprehensive context, an issue can be resolved quickly and
|
||||
|
|
@ -16,19 +17,19 @@ efficiently. Please consider adding the following data to your issue
|
|||
report if possible:
|
||||
|
||||
* A clear and unique summary that fits into one line. Also check that
|
||||
this issue has not yet been reported. If it has, add additional information there.
|
||||
this issue has not jet been reported. If it has, add additional information there.
|
||||
* Precise steps to reproduce (list of actions that leads to the issue)
|
||||
* Expected behavior (what should happen)
|
||||
* Actual behavior (what happens instead)
|
||||
* Logging message, trace backs, screen shots where relevant
|
||||
* Components involved (omit irrelevant parts):
|
||||
* Components involved:
|
||||
|
||||
* Operating System
|
||||
* ARTIQ version (with recent versions of ARTIQ, run ``artiq_client --version``)
|
||||
* Version of the gateware and runtime loaded in the core device (in the output of ``artiq_coremgmt -D .... log``)
|
||||
* Operating system
|
||||
* Conda version
|
||||
* ARTIQ version (package or git commit id, versions for bitstream, BIOS,
|
||||
runtime and host software)
|
||||
* Hardware involved
|
||||
|
||||
|
||||
For in-depth information on bug reporting, see:
|
||||
|
||||
http://www.chiark.greenend.org.uk/~sgtatham/bugs.html
|
||||
|
|
@ -41,8 +42,10 @@ Contributing Code
|
|||
ARTIQ welcomes contributions. Write bite-sized patches that can stand alone,
|
||||
clean them up, write proper commit messages, add docstrings and unittests. Then
|
||||
``git rebase`` them onto the current master or merge the current master. Verify
|
||||
that the testsuite passes. Then submit a pull request. Expect your contribution
|
||||
to be held up to coding standards (e.g. use ``flake8`` to check yourself).
|
||||
that the testsuite passes. Then prepare a pull request or send patches to the
|
||||
`mailing list <https://ssl.serverraum.org/lists/listinfo/artiq>`_ to be
|
||||
discussed. Expect your contribution to be held up to coding standards (e.g. use
|
||||
``flake8`` to check yourself).
|
||||
|
||||
Checklist for Code Contributions
|
||||
--------------------------------
|
||||
|
|
@ -64,6 +67,7 @@ Checklist for Code Contributions
|
|||
- Update ``RELEASE_NOTES.md`` if there are noteworthy changes, especially if
|
||||
there are changes to existing APIs
|
||||
- Check, test, and update the documentation in `doc/`
|
||||
- Check, test, and update the conda recipes in `conda/`
|
||||
- Check, test, and update the unittests
|
||||
- Close and/or update issues
|
||||
|
||||
|
|
@ -115,4 +119,4 @@ then you just add a line saying
|
|||
using your legal name (sorry, no pseudonyms or anonymous contributions.)
|
||||
|
||||
ARTIQ files that do not contain a license header are copyrighted by M-Labs Limited
|
||||
and are licensed under GNU LGPL version 3 or later.
|
||||
and are licensed under GNU GPL version 3.
|
||||
|
|
|
|||
|
|
@ -1,17 +1,94 @@
|
|||
Release process
|
||||
===============
|
||||
|
||||
Maintain ``RELEASE_NOTES.rst`` with a list of new features and API changes in each major release.
|
||||
|
||||
Major releases
|
||||
--------------
|
||||
|
||||
1. Create branch release-X from master.
|
||||
2. Tag the next commit in master X+1.0.dev.
|
||||
3. Ensure that release versions of all packages required are available under the ``main`` label in conda. Ensure that new packages in ``main`` do not break older ARTIQ releases.
|
||||
4. In the release-X branch, remove any unfinished features.
|
||||
5. Test and fix any problems found. Apply fixes to both master and release-X.
|
||||
6. If you have willing testers for release candidates, tag X.0rc1 in the release-X branch (generally use signed annotated tags, i.e. ``git tag -sa X.0rc1``), have it build, and point testers there. Iterate over the previous points with new release candidates if necessary.
|
||||
7. Tag X.0 in the release-X branch, build it, and copy its packages to ``main`` channel.
|
||||
8. Mint a new DOI from Zenodo and update the README/introduction.
|
||||
9. Update the m-labs.hk/artiq/manual redirect to point to m-labs.hk/artiq/manual-release-X (edit /artiq/.htaccess).
|
||||
10. "Draft a new release" and close the milestone on GitHub.
|
||||
11. Deprecate the old release documentation with a banner in
|
||||
doc/manual/_templates/layout.html in the old ``release-(X-1)`` branch.
|
||||
|
||||
Minor (bugfix) releases
|
||||
-----------------------
|
||||
|
||||
1. Backport bugfixes from the master branch or fix bugs specific to old releases into the currently maintained release-X branch(es).
|
||||
2. When significant bugs have been fixed, tag X.Y+1.
|
||||
3. To help dealing with regressions, no new features or refactorings should be implemented in release-X branches. Those happen in the master branch, and then a new release-X+1 branch is created.
|
||||
4. "Draft a new release" and close the milestone on GitHub.
|
||||
|
||||
Sharing development boards
|
||||
==========================
|
||||
|
||||
To avoid conflicts for development boards on the server, while using a board you must hold the corresponding lock file present in the ``/tmp`` folder of the machine to which the board is connected. Holding the lock file grants you exclusive access to the board.
|
||||
To avoid conflicts for development boards on the server, while using a board you must hold the corresponding lock file present in ``/var/lib/artiq/boards``. Holding the lock file grants you exclusive access to the board.
|
||||
|
||||
For example, to lock the KC705 until ENTER is pressed:
|
||||
To lock the KC705 for 30 minutes or until Ctrl-C is pressed:
|
||||
::
|
||||
ssh rpi-1.m-labs.hk "flock /tmp/board_lock-kc705-1 -c 'echo locked; read; echo unlocked'"
|
||||
flock --verbose /var/lib/artiq/boards/kc705-1 sleep 1800
|
||||
|
||||
Check that the command acquires the lock, i.e. prints something such as:
|
||||
::
|
||||
flock: getting lock took 0.000003 seconds
|
||||
flock: executing sleep
|
||||
|
||||
To lock the KC705 for the duration of the execution of a shell:
|
||||
::
|
||||
flock /var/lib/artiq/boards/kc705-1 bash
|
||||
|
||||
You may also use this script:
|
||||
::
|
||||
#!/bin/bash
|
||||
exec flock /var/lib/artiq/boards/$1 bash --rcfile <(cat ~/.bashrc; echo PS1=\"[$1\ lock]\ \$PS1\")
|
||||
|
||||
If the board is already locked by another user, the ``flock`` commands above will wait for the lock to be released.
|
||||
|
||||
To determine which user is locking a board, use a command such as:
|
||||
To determine which user is locking a board, use:
|
||||
::
|
||||
ssh rpi-1.m-labs.hk "fuser -v /tmp/board_lock-kc705-1"
|
||||
fuser -v /var/lib/artiq/boards/kc705-1
|
||||
|
||||
|
||||
Selecting a development board with artiq_flash
|
||||
==============================================
|
||||
|
||||
The board lock file also contains the openocd commands for selecting the corresponding developer board:
|
||||
::
|
||||
artiq_flash -I "$(cat /var/lib/artiq/boards/sayma-1)"
|
||||
|
||||
|
||||
Using developer tools
|
||||
=====================
|
||||
|
||||
ARTIQ ships with an ``artiq_devtool`` binary, which automates common actions arising when developing the board gateware and firmware on a machine other than the one to which the board is connected.
|
||||
|
||||
.. argparse::
|
||||
:ref: artiq.frontend.artiq_devtool.get_argparser
|
||||
:prog: artiq_devtool
|
||||
|
||||
To build and flash the firmware for ``sayma_amc_standalone`` target:
|
||||
::
|
||||
artiq_devtool -t sayma_amc_standalone build flash+log
|
||||
|
||||
To build the same target, flash it to the 3rd connected board, and forward the core device ports (1380, 1381, ...) as well as logs on the serial port:
|
||||
::
|
||||
artiq_devtool -t sayma_amc_standalone -b sayma-3 build flash connect
|
||||
|
||||
While the previous command is running, to build a new firmware and hotswap it, i.e. run without reflashing the board:
|
||||
::
|
||||
artiq_devtool -t sayma_amc_standalone build hotswap
|
||||
|
||||
While the previous command is running, to reset a board, e.g. if it became unresponsive:
|
||||
::
|
||||
artiq_devtool -t sayma_amc_standalone reset
|
||||
|
||||
|
||||
Deleting git branches
|
||||
|
|
|
|||
|
|
@ -3,6 +3,3 @@ graft artiq/examples
|
|||
include artiq/gui/logo*.svg
|
||||
include versioneer.py
|
||||
include artiq/_version.py
|
||||
include artiq/coredevice/coredevice_generic.schema.json
|
||||
include artiq/compiler/kernel.ld
|
||||
include artiq/afws.pem
|
||||
|
|
|
|||
21
README.rst
21
README.rst
|
|
@ -4,23 +4,23 @@
|
|||
.. image:: https://raw.githubusercontent.com/m-labs/artiq/master/doc/logo/artiq.png
|
||||
:target: https://m-labs.hk/artiq
|
||||
|
||||
ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) is a leading-edge control and data acquisition system for quantum information experiments.
|
||||
It is maintained and developed by `M-Labs <https://m-labs.hk>`_ and the initial development was for and in partnership with the `Ion Storage Group at NIST <https://www.nist.gov/pml/time-and-frequency-division/ion-storage>`_. ARTIQ is free software and offered to the entire research community as a solution equally applicable to other challenging control tasks, including outside the field of ion trapping. Many laboratories around the world have adopted ARTIQ as their control system, with over a hundred Sinara hardware crates deployed, and some have `contributed <https://m-labs.hk/experiment-control/funding/>`_ to it.
|
||||
ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) is the next-generation control system for quantum information experiments.
|
||||
It is maintained and developed by `M-Labs <https://m-labs.hk>`_ and the initial development was for and in partnership with the `Ion Storage Group at NIST <https://www.nist.gov/pml/time-and-frequency-division/ion-storage>`_. ARTIQ is free software and offered to the entire research community as a solution equally applicable to other challenging control tasks, including outside the field of ion trapping. Several other laboratories (e.g. at the University of Oxford, the Army Research Lab, and the University of Maryland) have later adopted ARTIQ as their control system and have contributed to it.
|
||||
|
||||
The system features a high-level programming language that helps describing complex experiments, which is compiled and executed on dedicated hardware with nanosecond timing resolution and sub-microsecond latency. It includes graphical user interfaces to parametrize and schedule experiments and to visualize and explore the results.
|
||||
|
||||
ARTIQ uses FPGA hardware to perform its time-critical tasks. The `Sinara hardware <https://github.com/sinara-hw>`_, and in particular the Kasli FPGA carrier, is designed to work with ARTIQ.
|
||||
ARTIQ is designed to be portable to hardware platforms from different vendors and FPGA manufacturers.
|
||||
Several different configurations of a `FPGA evaluation kit <https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html>`_ and of a `Zynq evaluation kit <https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html>`_ are also used and supported. FPGA platforms can be combined with any number of additional peripherals, either already accessible from ARTIQ or made accessible with little effort.
|
||||
Several different configurations of a `high-end FPGA evaluation kit <http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html>`_ are also used and supported. FPGA platforms can be combined with any number of additional peripherals, either already accessible from ARTIQ or made accessible with little effort.
|
||||
|
||||
ARTIQ and its dependencies are available in the form of Nix packages (for Linux) and MSYS2 packages (for Windows). See `the manual <https://m-labs.hk/experiment-control/resources/>`_ for installation instructions.
|
||||
ARTIQ and its dependencies are available in the form of `conda packages <https://conda.anaconda.org/m-labs/label/main>`_ for both Linux and Windows.
|
||||
Packages containing pre-compiled binary images to be loaded onto the hardware platforms are supplied for each configuration.
|
||||
Like any open source software ARTIQ can equally be built and installed directly from `source <https://github.com/m-labs/artiq>`_.
|
||||
|
||||
ARTIQ is supported by M-Labs and developed openly.
|
||||
Components, features, fixes, improvements, and extensions are often `funded <https://m-labs.hk/experiment-control/funding/>`_ by and developed for the partnering research groups.
|
||||
Components, features, fixes, improvements, and extensions are funded by and developed for the partnering research groups.
|
||||
|
||||
Core technologies employed include `Python <https://www.python.org/>`_, `Migen <https://github.com/m-labs/migen>`_, `Migen-AXI <https://github.com/peteut/migen-axi>`_, `Rust <https://www.rust-lang.org/>`_, `MiSoC <https://github.com/m-labs/misoc>`_/`VexRiscv <https://github.com/SpinalHDL/VexRiscv>`_, `LLVM <https://llvm.org/>`_/`llvmlite <https://github.com/numba/llvmlite>`_, and `Qt5 <https://www.qt.io/>`_.
|
||||
Technologies employed include `Python <https://www.python.org/>`_, `Migen <https://github.com/m-labs/migen>`_, `MiSoC <https://github.com/m-labs/misoc>`_/`mor1kx <https://github.com/openrisc/mor1kx>`_, `LLVM <http://llvm.org/>`_/`llvmlite <https://github.com/numba/llvmlite>`_, and `Qt5 <http://www.qt.io/>`_.
|
||||
|
||||
Website: https://m-labs.hk/artiq
|
||||
|
||||
|
|
@ -29,7 +29,7 @@ Website: https://m-labs.hk/artiq
|
|||
License
|
||||
=======
|
||||
|
||||
Copyright (C) 2014-2023 M-Labs Limited.
|
||||
Copyright (C) 2014-2018 M-Labs Limited.
|
||||
|
||||
ARTIQ is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU Lesser General Public License as published by
|
||||
|
|
@ -48,10 +48,9 @@ The ARTIQ manifesto
|
|||
===================
|
||||
|
||||
The free and open dissemination of methods and results is central to scientific progress.
|
||||
|
||||
The ARTIQ and Sinara authors, contributors, and supporters consider the free and open exchange of scientific tools to be equally important and have chosen the licensing terms of ARTIQ and Sinara accordingly. ARTIQ, including its gateware, the firmware, and the ARTIQ tools and libraries are licensed as LGPLv3+. The Sinara hardware designs are licensed under CERN OHL.
|
||||
This ensures that a user of ARTIQ or Sinara hardware designs obtains broad rights to use, redistribute, study, and modify them.
|
||||
|
||||
The ARTIQ authors, contributors, and supporters consider the free and open exchange of scientific tools to be equally important and have chosen the licensing terms of ARTIQ accordingly.
|
||||
ARTIQ, including its gateware, the firmware, and the ARTIQ tools and libraries are licensed as LGPLv3+.
|
||||
This ensures that a user of ARTIQ obtains broad rights to use, redistribute, and modify it.
|
||||
The following statements are intended to clarify the interpretation and application of the licensing terms:
|
||||
|
||||
* There is no requirement to distribute any unmodified, modified, or extended versions of ARTIQ. Only when distributing ARTIQ the source needs to be made available.
|
||||
|
|
|
|||
|
|
@ -3,345 +3,12 @@
|
|||
Release notes
|
||||
=============
|
||||
|
||||
ARTIQ-8 (Unreleased)
|
||||
--------------------
|
||||
|
||||
Highlights:
|
||||
|
||||
* New hardware support:
|
||||
- Support for Shuttler, a 16-channel 125MSPS DAC card intended for ion transport.
|
||||
Waveform generator and user API are similar to the NIST PDQ.
|
||||
- Implemented Phaser-servo. This requires recent gateware on Phaser.
|
||||
- Almazny v1.2 with finer RF switch control.
|
||||
- Metlino and Sayma support has been dropped due to complications with synchronous RTIO clocking.
|
||||
- More user LEDs are exposed to RTIO on Kasli.
|
||||
- Implemented Phaser-MIQRO support. This requires the proprietary Phaser MIQRO gateware
|
||||
variant from QUARTIQ.
|
||||
- Sampler: fixed ADC MU to Volt conversion factor for Sampler v2.2+.
|
||||
For earlier hardware versions, specify the hardware version in the device
|
||||
database file (e.g. ``"hw_rev": "v2.1"``) to use the correct conversion factor.
|
||||
* Support for distributed DMA, where DMA is run directly on satellites for corresponding
|
||||
RTIO events, increasing bandwidth in scenarios with heavy satellite usage.
|
||||
* Support for subkernels, where kernels are run on satellite device CPUs to offload some
|
||||
of the processing and RTIO operations.
|
||||
* CPU (on softcore platforms) and AXI bus (on Zynq) are now clocked synchronously with the RTIO
|
||||
clock, to facilitate implementation of local processing on DRTIO satellites, and to slightly
|
||||
reduce RTIO latency.
|
||||
* Support for DRTIO-over-EEM, used with Shuttler.
|
||||
* Added channel names to RTIO error messages.
|
||||
* GUI:
|
||||
- Implemented Applet Request Interfaces which allow applets to modify datasets and set the
|
||||
current values of widgets in the dashboard's experiment windows.
|
||||
- Implemented a new EntryArea widget which allows argument entry widgets to be used in applets.
|
||||
- The "Close all applets" command (shortcut: Ctrl-Alt-W) now ignores docked applets,
|
||||
making it a convenient way to clean up after exploratory work without destroying a
|
||||
carefully arranged default workspace.
|
||||
- Hotkeys now organize experiment windows in the order they were last interacted with:
|
||||
+ CTRL+SHIFT+T tiles experiment windows
|
||||
+ CTRL+SHIFT+C cascades experiment windows
|
||||
* Persistent datasets are now stored in a LMDB database for improved performance.
|
||||
* Python's built-in types (such as ``float``, or ``List[...]``) can now be used in type annotations on
|
||||
kernel functions.
|
||||
* Full Python 3.10 support.
|
||||
* MSYS2 packaging for Windows, which replaces Conda. Conda packages are still available to
|
||||
support legacy installations, but may be removed in a future release.
|
||||
|
||||
Breaking changes:
|
||||
|
||||
* ``SimpleApplet`` now calls widget constructors with an additional ``ctl`` parameter for control
|
||||
operations, which includes dataset operations. It can be ignored if not needed. For an example usage,
|
||||
refer to the ``big_number.py`` applet.
|
||||
* ``SimpleApplet`` and ``TitleApplet`` now call ``data_changed`` with additional parameters. Derived applets
|
||||
should change the function signature as below:
|
||||
|
||||
::
|
||||
|
||||
# SimpleApplet
|
||||
def data_changed(self, value, metadata, persist, mods)
|
||||
# SimpleApplet (old version)
|
||||
def data_changed(self, data, mods)
|
||||
# TitleApplet
|
||||
def data_changed(self, value, metadata, persist, mods, title)
|
||||
# TitleApplet (old version)
|
||||
def data_changed(self, data, mods, title)
|
||||
|
||||
Accesses to the data argument should be replaced as below:
|
||||
|
||||
::
|
||||
|
||||
data[key][0] ==> persist[key]
|
||||
data[key][1] ==> value[key]
|
||||
|
||||
* The ``ndecimals`` parameter in ``NumberValue`` and ``Scannable`` has been renamed to ``precision``.
|
||||
Parameters after and including ``scale`` in both constructors are now keyword-only.
|
||||
Refer to the updated ``no_hardware/arguments_demo.py`` example for current usage.
|
||||
* Almazny v1.2 is incompatible with the legacy versions and is the default.
|
||||
To use legacy versions, specify ``almazny_hw_rev`` in the JSON description.
|
||||
* kasli_generic.py has been merged into kasli.py, and the demonstration designs without JSON descriptions
|
||||
have been removed. The base classes remain present in kasli.py to support third-party flows without
|
||||
JSON descriptions.
|
||||
* Legacy PYON databases should be converted to LMDB with the script below:
|
||||
|
||||
::
|
||||
|
||||
from sipyco import pyon
|
||||
import lmdb
|
||||
|
||||
old = pyon.load_file("dataset_db.pyon")
|
||||
new = lmdb.open("dataset_db.mdb", subdir=False, map_size=2**30)
|
||||
with new.begin(write=True) as txn:
|
||||
for key, value in old.items():
|
||||
txn.put(key.encode(), pyon.encode((value, {})).encode())
|
||||
new.close()
|
||||
|
||||
* ``artiq.wavesynth`` has been removed.
|
||||
|
||||
ARTIQ-7
|
||||
-------
|
||||
|
||||
Highlights:
|
||||
|
||||
* New hardware support:
|
||||
- Kasli-SoC, a new EEM carrier based on a Zynq SoC, enabling much faster kernel execution
|
||||
(see: https://arxiv.org/abs/2111.15290).
|
||||
- DRTIO support on Zynq-based devices (Kasli-SoC and ZC706).
|
||||
- DRTIO support on KC705.
|
||||
- HVAMP_8CH 8 channel HV amplifier for Fastino / Zotinos
|
||||
- Almazny mezzanine board for Mirny
|
||||
- Phaser: improved documentation, exposed the DAC coarse mixer and ``sif_sync``, exposed upconverter calibration
|
||||
and enabling/disabling of upconverter LO & RF outputs, added helpers to align Phaser updates to the
|
||||
RTIO timeline (``get_next_frame_mu()``).
|
||||
- Urukul: ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912.
|
||||
* Softcore targets now use the RISC-V architecture (VexRiscv) instead of OR1K (mor1kx).
|
||||
* Gateware FPU is supported on KC705 and Kasli 2.0.
|
||||
* Faster compilation for large arrays/lists.
|
||||
* Faster exception handling.
|
||||
* Several exception handling bugs fixed.
|
||||
* Support for a simpler shared library system with faster calls into the runtime. This is only used by the NAC3
|
||||
compiler (nac3ld) and improves RTIO output performance (test_pulse_rate) by 9-10%.
|
||||
* Moninj improvements:
|
||||
- Urukul monitoring and frequency setting (through dashboard) is now supported.
|
||||
- Core device moninj is now proxied via the ``aqctl_moninj_proxy`` controller.
|
||||
* The configuration entry ``rtio_clock`` supports multiple clocking settings, deprecating the usage
|
||||
of compile-time options.
|
||||
* Added support for 100MHz RTIO clock in DRTIO.
|
||||
* Previously detected RTIO async errors are reported to the host after each kernel terminates and a
|
||||
warning is logged. The warning is additional to the one already printed in the core device log
|
||||
immediately upon detection of the error.
|
||||
* Extended Kasli gateware JSON description with configuration for SPI over DIO.
|
||||
* TTL outputs can be now configured to work as a clock generator from the JSON.
|
||||
* On Kasli, the number of FIFO lanes in the scalable events dispatcher (SED) can now be configured in
|
||||
the JSON.
|
||||
* ``artiq_ddb_template`` generates edge-counter keys that start with the key of the corresponding
|
||||
TTL device (e.g. ``ttl_0_counter`` for the edge counter on TTL device ``ttl_0``).
|
||||
* ``artiq_master`` now has an ``--experiment-subdir`` option to scan only a subdirectory of the
|
||||
repository when building the list of experiments.
|
||||
* Experiments can now be submitted by-content.
|
||||
* The master can now optionally log all experiments submitted into a CSV file.
|
||||
* Removed worker DB warning for writing a dataset that is also in the archive.
|
||||
* Experiments can now call ``scheduler.check_termination()`` to test if the user
|
||||
has requested graceful termination.
|
||||
* ARTIQ command-line programs and controllers now exit cleanly on Ctrl-C.
|
||||
* ``artiq_coremgmt reboot`` now reloads gateware as well, providing a more thorough and reliable
|
||||
device reset (7-series FPGAs only).
|
||||
* Firmware and gateware can now be built on-demand on the M-Labs server using ``afws_client``
|
||||
(subscribers only). Self-compilation remains possible.
|
||||
* Easier-to-use packaging via Nix Flakes.
|
||||
* Python 3.10 support (experimental).
|
||||
|
||||
Breaking changes:
|
||||
|
||||
* Due to the new RISC-V CPU, the device database entry for the core device needs to be updated.
|
||||
The ``target`` parameter needs to be set to ``rv32ima`` for Kasli 1.x and to ``rv32g`` for all
|
||||
other boards. Freshly generated device database templates already contain this update.
|
||||
* Updated Phaser-Upconverter default frequency 2.875 GHz. The new default uses the target PFD
|
||||
frequency of the hardware design.
|
||||
* ``Phaser.init()`` now disables all Kasli-oscillators. This avoids full power RF output being
|
||||
generated for some configurations.
|
||||
* Phaser: fixed coarse mixer frequency configuration
|
||||
* Mirny: Added extra delays in ``ADF5356.sync()``. This avoids the need of an extra delay before
|
||||
calling ``ADF5356.init()``.
|
||||
* The deprecated ``set_dataset(..., save=...)`` is no longer supported.
|
||||
* The ``PCA9548`` I2C switch class was renamed to ``I2CSwitch``, to accommodate support for PCA9547,
|
||||
and possibly other switches in future. Readback has been removed, and now only one channel per
|
||||
switch is supported.
|
||||
|
||||
|
||||
ARTIQ-6
|
||||
-------
|
||||
|
||||
Highlights:
|
||||
|
||||
* New hardware support:
|
||||
- Phaser, a quad channel 1GS/s RF generator card with dual IQ upconverter and dual 5MS/s
|
||||
ADC and FPGA.
|
||||
- Zynq SoC core device (ZC706), enabling kernels to run on 1 GHz CPU core with a floating-point
|
||||
unit for faster computations. This currently requires an external
|
||||
repository (https://git.m-labs.hk/m-labs/artiq-zynq).
|
||||
- Mirny 4-channel wide-band PLL/VCO-based microwave frequency synthesiser
|
||||
- Fastino 32-channel, 3MS/s per channel, 16-bit DAC EEM
|
||||
- Kasli 2.0, an improved core device with 12 built-in EEM slots, faster FPGA, 4 SFPs, and
|
||||
high-precision clock recovery circuitry for DRTIO (to be supported in ARTIQ-7).
|
||||
* ARTIQ Python (core device kernels):
|
||||
- Multidimensional arrays are now available on the core device, using NumPy syntax.
|
||||
Elementwise operations (e.g. ``+``, ``/``), matrix multiplication (``@``) and
|
||||
multidimensional indexing are supported; slices and views are not yet.
|
||||
- Trigonometric and other common math functions from NumPy are now available on the
|
||||
core device (e.g. ``numpy.sin``), both for scalar arguments and implicitly
|
||||
broadcast across multidimensional arrays.
|
||||
- Failed assertions now raise ``AssertionError``\ s instead of aborting kernel
|
||||
execution.
|
||||
* Performance improvements:
|
||||
- SERDES TTL inputs can now detect edges on pulses that are shorter
|
||||
than the RTIO period (https://github.com/m-labs/artiq/issues/1432)
|
||||
- Improved performance for kernel RPC involving list and array.
|
||||
* Coredevice SI to mu conversions now always return valid codes, or raise a ``ValueError``.
|
||||
* Zotino now exposes ``voltage_to_mu()``
|
||||
* ``ad9910``:
|
||||
- The maximum amplitude scale factor is now ``0x3fff`` (was ``0x3ffe`` before).
|
||||
- The default single-tone profile is now 7 (was 0).
|
||||
- Added option to ``set_mu()`` that affects the ASF, FTW and POW registers
|
||||
instead of the single-tone profile register.
|
||||
* Mirny now supports HW revision independent, human readable ``clk_sel`` parameters:
|
||||
"XO", "SMA", and "MMCX". Passing an integer is backwards compatible.
|
||||
* Dashboard:
|
||||
- Applets now restart if they are running and a ccb call changes their spec
|
||||
- A "Quick Open" dialog to open experiments by typing part of their name can
|
||||
be brought up Ctrl-P (Ctrl+Return to immediately submit the selected entry
|
||||
with the default arguments).
|
||||
- The Applets dock now has a context menu command to quickly close all open
|
||||
applets (shortcut: Ctrl-Alt-W).
|
||||
* Experiment results are now always saved to HDF5, even if ``run()`` fails.
|
||||
* Core device: ``panic_reset 1`` now correctly resets the kernel CPU as well if
|
||||
communication CPU panic occurs.
|
||||
* NumberValue accepts a ``type`` parameter specifying the output as ``int`` or ``float``
|
||||
* A parameter ``--identifier-str`` has been added to many targets to aid
|
||||
with reproducible builds.
|
||||
* Python 3.7 support in Conda packages.
|
||||
* `kasli_generic` JSON descriptions are now validated against a
|
||||
schema. Description defaults have moved from Python to the
|
||||
schema. Warns if ARTIQ version is too old.
|
||||
|
||||
Breaking changes:
|
||||
|
||||
* ``artiq_netboot`` has been moved to its own repository at
|
||||
https://git.m-labs.hk/m-labs/artiq-netboot
|
||||
* Core device watchdogs have been removed.
|
||||
* The ARTIQ compiler now implements arrays following NumPy semantics, rather than as a
|
||||
thin veneer around lists. Most prior use cases of NumPy arrays in kernels should work
|
||||
unchanged with the new implementation, but the behavior might differ slightly in some
|
||||
cases (for instance, non-rectangular arrays are not currently supported).
|
||||
* ``quamash`` has been replaced with ``qasync``.
|
||||
* Protocols are updated to use device endian.
|
||||
* Analyzer dump format includes a byte for device endianness.
|
||||
* To support variable numbers of Urukul cards in the future, the
|
||||
``artiq.coredevice.suservo.SUServo`` constructor now accepts two device name lists,
|
||||
``cpld_devices`` and ``dds_devices``, rather than four individual arguments.
|
||||
* Experiment classes with underscore-prefixed names are now ignored when ``artiq_client``
|
||||
determines which experiment to submit (consistent with ``artiq_run``).
|
||||
|
||||
ARTIQ-5
|
||||
-------
|
||||
|
||||
Highlights:
|
||||
|
||||
* Performance improvements:
|
||||
- Faster RTIO event submission (1.5x improvement in pulse rate test)
|
||||
See: https://github.com/m-labs/artiq/issues/636
|
||||
- Faster compilation times (3 seconds saved on kernel compilation time on a typical
|
||||
medium-size experiment)
|
||||
See: https://github.com/m-labs/artiq/commit/611bcc4db4ed604a32d9678623617cd50e968cbf
|
||||
* Improved packaging and build system:
|
||||
- new continuous integration/delivery infrastructure based on Nix and Hydra,
|
||||
providing reproducibility, speed and independence.
|
||||
- rolling release process (https://github.com/m-labs/artiq/issues/1326).
|
||||
- firmware, gateware and device database templates are automatically built for all
|
||||
supported Kasli variants.
|
||||
- new JSON description format for generic Kasli systems.
|
||||
- Nix packages are now supported.
|
||||
- many Conda problems worked around.
|
||||
- controllers are now out-of-tree.
|
||||
- split packages that enable lightweight applications that communicate with ARTIQ,
|
||||
e.g. controllers running on non-x86 single-board computers.
|
||||
* Improved Urukul support:
|
||||
- AD9910 RAM mode.
|
||||
- Configurable refclk divider and PLL bypass.
|
||||
- More reliable phase synchronization at high sample rates.
|
||||
- Synchronization calibration data can be read from EEPROM.
|
||||
* A gateware-level input edge counter has been added, which offers higher
|
||||
throughput and increased flexibility over the usual TTL input PHYs where
|
||||
edge timestamps are not required. See ``artiq.coredevice.edge_counter`` for
|
||||
the core device driver and ``artiq.gateware.rtio.phy.edge_counter``/
|
||||
``artiq.gateware.eem.DIO.add_std`` for the gateware components.
|
||||
* With DRTIO, Siphaser uses a better calibration mechanism.
|
||||
See: https://github.com/m-labs/artiq/commit/cc58318500ecfa537abf24127f2c22e8fe66e0f8
|
||||
* Schedule updates can be sent to influxdb (artiq_influxdb_schedule).
|
||||
* Experiments can now programatically set their default pipeline, priority, and flush flag.
|
||||
* List datasets can now be efficiently appended to from experiments using
|
||||
``artiq.language.environment.HasEnvironment.append_to_dataset``.
|
||||
* The core device now supports IPv6.
|
||||
* To make development easier, the bootloader can receive firmware and secondary FPGA
|
||||
gateware from the network.
|
||||
* Python 3.7 compatibility (Nix and source builds only, no Conda).
|
||||
* Various other bugs from 4.0 fixed.
|
||||
* Preliminary Sayma v2 and Metlino hardware support.
|
||||
|
||||
Breaking changes:
|
||||
|
||||
* The ``artiq.coredevice.ad9910.AD9910`` and
|
||||
``artiq.coredevice.ad9914.AD9914`` phase reference timestamp parameters
|
||||
have been renamed to ``ref_time_mu`` for consistency, as they are in machine
|
||||
units.
|
||||
* The controller manager now ignores device database entries without the
|
||||
``command`` key set to facilitate sharing of devices between multiple
|
||||
masters.
|
||||
* The meaning of the ``-d/--dir`` and ``--srcbuild`` options of ``artiq_flash``
|
||||
has changed.
|
||||
* Controllers for third-party devices are now out-of-tree.
|
||||
* ``aqctl_corelog`` now filters log messages below the ``WARNING`` level by default.
|
||||
This behavior can be changed using the ``-v`` and ``-q`` options like the other
|
||||
programs.
|
||||
* On Kasli the firmware now starts with a unique default MAC address
|
||||
from EEPROM if `mac` is absent from the flash config.
|
||||
* The ``-e/--experiment`` switch of ``artiq_run`` and ``artiq_compile``
|
||||
has been renamed ``-c/--class-name``.
|
||||
* ``artiq_devtool`` has been removed.
|
||||
* Much of ``artiq.protocols`` has been moved to a separate package ``sipyco``.
|
||||
``artiq_rpctool`` has been renamed to ``sipyco_rpctool``.
|
||||
|
||||
|
||||
ARTIQ-4
|
||||
-------
|
||||
|
||||
4.0
|
||||
***
|
||||
|
||||
* The ``artiq.coredevice.ttl`` drivers no longer track the timestamps of
|
||||
submitted events in software, requiring the user to explicitly specify the
|
||||
timeout for ``count()``/``timestamp_mu()``. Support for ``sync()`` has been dropped.
|
||||
|
||||
Now that RTIO has gained DMA support, there is no longer a reliable way for
|
||||
the kernel CPU to track the individual events submitted on any one channel.
|
||||
Requiring the timeouts to be specified explicitly ensures consistent API
|
||||
behavior. To make this more convenient, the ``TTLInOut.gate_*()`` functions
|
||||
now return the cursor position at the end of the gate, e.g.::
|
||||
|
||||
ttl_input.count(ttl_input.gate_rising(100 * us))
|
||||
|
||||
In most situations – that is, unless the timeline cursor is rewound after the
|
||||
respective ``gate_*()`` call – simply passing ``now_mu()`` is also a valid
|
||||
upgrade path::
|
||||
|
||||
ttl_input.count(now_mu())
|
||||
|
||||
The latter might use up more timeline slack than necessary, though.
|
||||
|
||||
In place of ``TTL(In)Out.sync``, the new ``Core.wait_until_mu()`` method can
|
||||
be used, which blocks execution until the hardware RTIO cursor reaches the
|
||||
given timestamp::
|
||||
|
||||
ttl_output.pulse(10 * us)
|
||||
self.core.wait_until_mu(now_mu())
|
||||
* RTIO outputs use a new architecture called Scalable Event Dispatcher (SED),
|
||||
which allows building systems with large number of RTIO channels more
|
||||
efficiently.
|
||||
|
|
@ -354,13 +21,11 @@ ARTIQ-4
|
|||
server address argument and the notify port.
|
||||
* The master now has a ``--name`` argument. If given, the dashboard is labelled
|
||||
with this name rather than the server address.
|
||||
* ``artiq_flash`` targets Kasli by default. Use ``-t kc705`` to flash a KC705
|
||||
instead.
|
||||
* ``artiq_flash -m/--adapter`` has been changed to ``artiq_flash -V/--variant``.
|
||||
* The ``proxy`` action of ``artiq_flash`` is determined automatically and should
|
||||
not be specified manually anymore.
|
||||
* ``kc705_dds`` has been renamed ``kc705``.
|
||||
* The ``-H/--hw-adapter`` option of ``kc705`` has been renamed ``-V/--variant``.
|
||||
* the ``-H/--hw-adapter`` option of ``kc705`` has ben renamed ``-V/--variant``.
|
||||
* SPI masters have been switched from misoc-spi to misoc-spi2. This affects
|
||||
all out-of-tree RTIO core device drivers using those buses. See the various
|
||||
commits on e.g. the ``ad53xx`` driver for an example how to port from the old
|
||||
|
|
@ -372,24 +37,11 @@ ARTIQ-4
|
|||
is no longer necessary.
|
||||
* The configuration entry ``startup_clock`` is renamed ``rtio_clock``. Switching
|
||||
clocks dynamically (i.e. without device restart) is no longer supported.
|
||||
* ``set_dataset(..., save=True)`` has been renamed
|
||||
``set_dataset(..., archive=True)``.
|
||||
* On the AD9914 DDS, when switching to ``PHASE_MODE_CONTINUOUS`` from another mode,
|
||||
use the returned value of the last ``set_mu`` call as the phase offset for
|
||||
``PHASE_MODE_CONTINUOUS`` to avoid a phase discontinuity. This is no longer done
|
||||
automatically. If one phase glitch when entering ``PHASE_MODE_CONTINUOUS`` is not
|
||||
an issue, this recommendation can be ignored.
|
||||
|
||||
|
||||
ARTIQ-3
|
||||
-------
|
||||
|
||||
3.7
|
||||
***
|
||||
|
||||
No further notes.
|
||||
|
||||
|
||||
3.6
|
||||
***
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,11 @@
|
|||
from ._version import get_version
|
||||
__version__ = get_version()
|
||||
del get_version
|
||||
from ._version import get_versions
|
||||
__version__ = get_versions()['version']
|
||||
del get_versions
|
||||
|
||||
import os
|
||||
__artiq_dir__ = os.path.dirname(os.path.abspath(__file__))
|
||||
del os
|
||||
|
||||
from ._version import get_versions
|
||||
__version__ = get_versions()['version']
|
||||
del get_versions
|
||||
|
|
|
|||
|
|
@ -1,7 +1,520 @@
|
|||
|
||||
# This file helps to compute a version number in source trees obtained from
|
||||
# git-archive tarball (such as those provided by githubs download-from-tag
|
||||
# feature). Distribution tarballs (built by setup.py sdist) and build
|
||||
# directories (produced by setup.py build) will contain a much shorter file
|
||||
# that just contains the computed version number.
|
||||
|
||||
# This file is released into the public domain. Generated by
|
||||
# versioneer-0.18 (https://github.com/warner/python-versioneer)
|
||||
|
||||
"""Git implementation of _version.py."""
|
||||
|
||||
import errno
|
||||
import os
|
||||
import re
|
||||
import subprocess
|
||||
import sys
|
||||
|
||||
def get_rev():
|
||||
return os.getenv("VERSIONEER_REV", default="unknown")
|
||||
|
||||
def get_version():
|
||||
return os.getenv("VERSIONEER_OVERRIDE", default="8.0+unknown.beta")
|
||||
def get_keywords():
|
||||
"""Get the keywords needed to look up the version information."""
|
||||
# these strings will be replaced by git during git-archive.
|
||||
# setup.py/versioneer.py will grep for the variable names, so they must
|
||||
# each be defined on a line of their own. _version.py will just call
|
||||
# get_keywords().
|
||||
git_refnames = "$Format:%d$"
|
||||
git_full = "$Format:%H$"
|
||||
git_date = "$Format:%ci$"
|
||||
keywords = {"refnames": git_refnames, "full": git_full, "date": git_date}
|
||||
return keywords
|
||||
|
||||
|
||||
class VersioneerConfig:
|
||||
"""Container for Versioneer configuration parameters."""
|
||||
|
||||
|
||||
def get_config():
|
||||
"""Create, populate and return the VersioneerConfig() object."""
|
||||
# these strings are filled in when 'setup.py versioneer' creates
|
||||
# _version.py
|
||||
cfg = VersioneerConfig()
|
||||
cfg.VCS = "git"
|
||||
cfg.style = "pep440"
|
||||
cfg.tag_prefix = ""
|
||||
cfg.parentdir_prefix = "artiq-"
|
||||
cfg.versionfile_source = "artiq/_version.py"
|
||||
cfg.verbose = False
|
||||
return cfg
|
||||
|
||||
|
||||
class NotThisMethod(Exception):
|
||||
"""Exception raised if a method is not valid for the current scenario."""
|
||||
|
||||
|
||||
LONG_VERSION_PY = {}
|
||||
HANDLERS = {}
|
||||
|
||||
|
||||
def register_vcs_handler(vcs, method): # decorator
|
||||
"""Decorator to mark a method as the handler for a particular VCS."""
|
||||
def decorate(f):
|
||||
"""Store f in HANDLERS[vcs][method]."""
|
||||
if vcs not in HANDLERS:
|
||||
HANDLERS[vcs] = {}
|
||||
HANDLERS[vcs][method] = f
|
||||
return f
|
||||
return decorate
|
||||
|
||||
|
||||
def run_command(commands, args, cwd=None, verbose=False, hide_stderr=False,
|
||||
env=None):
|
||||
"""Call the given command(s)."""
|
||||
assert isinstance(commands, list)
|
||||
p = None
|
||||
for c in commands:
|
||||
try:
|
||||
dispcmd = str([c] + args)
|
||||
# remember shell=False, so use git.cmd on windows, not just git
|
||||
p = subprocess.Popen([c] + args, cwd=cwd, env=env,
|
||||
stdout=subprocess.PIPE,
|
||||
stderr=(subprocess.PIPE if hide_stderr
|
||||
else None))
|
||||
break
|
||||
except EnvironmentError:
|
||||
e = sys.exc_info()[1]
|
||||
if e.errno == errno.ENOENT:
|
||||
continue
|
||||
if verbose:
|
||||
print("unable to run %s" % dispcmd)
|
||||
print(e)
|
||||
return None, None
|
||||
else:
|
||||
if verbose:
|
||||
print("unable to find command, tried %s" % (commands,))
|
||||
return None, None
|
||||
stdout = p.communicate()[0].strip()
|
||||
if sys.version_info[0] >= 3:
|
||||
stdout = stdout.decode()
|
||||
if p.returncode != 0:
|
||||
if verbose:
|
||||
print("unable to run %s (error)" % dispcmd)
|
||||
print("stdout was %s" % stdout)
|
||||
return None, p.returncode
|
||||
return stdout, p.returncode
|
||||
|
||||
|
||||
def versions_from_parentdir(parentdir_prefix, root, verbose):
|
||||
"""Try to determine the version from the parent directory name.
|
||||
|
||||
Source tarballs conventionally unpack into a directory that includes both
|
||||
the project name and a version string. We will also support searching up
|
||||
two directory levels for an appropriately named parent directory
|
||||
"""
|
||||
rootdirs = []
|
||||
|
||||
for i in range(3):
|
||||
dirname = os.path.basename(root)
|
||||
if dirname.startswith(parentdir_prefix):
|
||||
return {"version": dirname[len(parentdir_prefix):],
|
||||
"full-revisionid": None,
|
||||
"dirty": False, "error": None, "date": None}
|
||||
else:
|
||||
rootdirs.append(root)
|
||||
root = os.path.dirname(root) # up a level
|
||||
|
||||
if verbose:
|
||||
print("Tried directories %s but none started with prefix %s" %
|
||||
(str(rootdirs), parentdir_prefix))
|
||||
raise NotThisMethod("rootdir doesn't start with parentdir_prefix")
|
||||
|
||||
|
||||
@register_vcs_handler("git", "get_keywords")
|
||||
def git_get_keywords(versionfile_abs):
|
||||
"""Extract version information from the given file."""
|
||||
# the code embedded in _version.py can just fetch the value of these
|
||||
# keywords. When used from setup.py, we don't want to import _version.py,
|
||||
# so we do it with a regexp instead. This function is not used from
|
||||
# _version.py.
|
||||
keywords = {}
|
||||
try:
|
||||
f = open(versionfile_abs, "r")
|
||||
for line in f.readlines():
|
||||
if line.strip().startswith("git_refnames ="):
|
||||
mo = re.search(r'=\s*"(.*)"', line)
|
||||
if mo:
|
||||
keywords["refnames"] = mo.group(1)
|
||||
if line.strip().startswith("git_full ="):
|
||||
mo = re.search(r'=\s*"(.*)"', line)
|
||||
if mo:
|
||||
keywords["full"] = mo.group(1)
|
||||
if line.strip().startswith("git_date ="):
|
||||
mo = re.search(r'=\s*"(.*)"', line)
|
||||
if mo:
|
||||
keywords["date"] = mo.group(1)
|
||||
f.close()
|
||||
except EnvironmentError:
|
||||
pass
|
||||
return keywords
|
||||
|
||||
|
||||
@register_vcs_handler("git", "keywords")
|
||||
def git_versions_from_keywords(keywords, tag_prefix, verbose):
|
||||
"""Get version information from git keywords."""
|
||||
if not keywords:
|
||||
raise NotThisMethod("no keywords at all, weird")
|
||||
date = keywords.get("date")
|
||||
if date is not None:
|
||||
# git-2.2.0 added "%cI", which expands to an ISO-8601 -compliant
|
||||
# datestamp. However we prefer "%ci" (which expands to an "ISO-8601
|
||||
# -like" string, which we must then edit to make compliant), because
|
||||
# it's been around since git-1.5.3, and it's too difficult to
|
||||
# discover which version we're using, or to work around using an
|
||||
# older one.
|
||||
date = date.strip().replace(" ", "T", 1).replace(" ", "", 1)
|
||||
refnames = keywords["refnames"].strip()
|
||||
if refnames.startswith("$Format"):
|
||||
if verbose:
|
||||
print("keywords are unexpanded, not using")
|
||||
raise NotThisMethod("unexpanded keywords, not a git-archive tarball")
|
||||
refs = set([r.strip() for r in refnames.strip("()").split(",")])
|
||||
# starting in git-1.8.3, tags are listed as "tag: foo-1.0" instead of
|
||||
# just "foo-1.0". If we see a "tag: " prefix, prefer those.
|
||||
TAG = "tag: "
|
||||
tags = set([r[len(TAG):] for r in refs if r.startswith(TAG)])
|
||||
if not tags:
|
||||
# Either we're using git < 1.8.3, or there really are no tags. We use
|
||||
# a heuristic: assume all version tags have a digit. The old git %d
|
||||
# expansion behaves like git log --decorate=short and strips out the
|
||||
# refs/heads/ and refs/tags/ prefixes that would let us distinguish
|
||||
# between branches and tags. By ignoring refnames without digits, we
|
||||
# filter out many common branch names like "release" and
|
||||
# "stabilization", as well as "HEAD" and "master".
|
||||
tags = set([r for r in refs if re.search(r'\d', r)])
|
||||
if verbose:
|
||||
print("discarding '%s', no digits" % ",".join(refs - tags))
|
||||
if verbose:
|
||||
print("likely tags: %s" % ",".join(sorted(tags)))
|
||||
for ref in sorted(tags):
|
||||
# sorting will prefer e.g. "2.0" over "2.0rc1"
|
||||
if ref.startswith(tag_prefix):
|
||||
r = ref[len(tag_prefix):]
|
||||
if verbose:
|
||||
print("picking %s" % r)
|
||||
return {"version": r,
|
||||
"full-revisionid": keywords["full"].strip(),
|
||||
"dirty": False, "error": None,
|
||||
"date": date}
|
||||
# no suitable tags, so version is "0+unknown", but full hex is still there
|
||||
if verbose:
|
||||
print("no suitable tags, using unknown + full revision id")
|
||||
return {"version": "0+unknown",
|
||||
"full-revisionid": keywords["full"].strip(),
|
||||
"dirty": False, "error": "no suitable tags", "date": None}
|
||||
|
||||
|
||||
@register_vcs_handler("git", "pieces_from_vcs")
|
||||
def git_pieces_from_vcs(tag_prefix, root, verbose, run_command=run_command):
|
||||
"""Get version from 'git describe' in the root of the source tree.
|
||||
|
||||
This only gets called if the git-archive 'subst' keywords were *not*
|
||||
expanded, and _version.py hasn't already been rewritten with a short
|
||||
version string, meaning we're inside a checked out source tree.
|
||||
"""
|
||||
GITS = ["git"]
|
||||
if sys.platform == "win32":
|
||||
GITS = ["git.cmd", "git.exe"]
|
||||
|
||||
out, rc = run_command(GITS, ["rev-parse", "--git-dir"], cwd=root,
|
||||
hide_stderr=True)
|
||||
if rc != 0:
|
||||
if verbose:
|
||||
print("Directory %s not under git control" % root)
|
||||
raise NotThisMethod("'git rev-parse --git-dir' returned error")
|
||||
|
||||
# if there is a tag matching tag_prefix, this yields TAG-NUM-gHEX[-dirty]
|
||||
# if there isn't one, this yields HEX[-dirty] (no NUM)
|
||||
describe_out, rc = run_command(GITS, ["describe", "--tags", "--dirty",
|
||||
"--always", "--long", "--abbrev=8",
|
||||
"--match", "%s*" % tag_prefix],
|
||||
cwd=root)
|
||||
# --long was added in git-1.5.5
|
||||
if describe_out is None:
|
||||
raise NotThisMethod("'git describe' failed")
|
||||
describe_out = describe_out.strip()
|
||||
full_out, rc = run_command(GITS, ["rev-parse", "HEAD"], cwd=root)
|
||||
if full_out is None:
|
||||
raise NotThisMethod("'git rev-parse' failed")
|
||||
full_out = full_out.strip()
|
||||
|
||||
pieces = {}
|
||||
pieces["long"] = full_out
|
||||
pieces["short"] = full_out[:8] # maybe improved later
|
||||
pieces["error"] = None
|
||||
|
||||
# parse describe_out. It will be like TAG-NUM-gHEX[-dirty] or HEX[-dirty]
|
||||
# TAG might have hyphens.
|
||||
git_describe = describe_out
|
||||
|
||||
# look for -dirty suffix
|
||||
dirty = git_describe.endswith("-dirty")
|
||||
pieces["dirty"] = dirty
|
||||
if dirty:
|
||||
git_describe = git_describe[:git_describe.rindex("-dirty")]
|
||||
|
||||
# now we have TAG-NUM-gHEX or HEX
|
||||
|
||||
if "-" in git_describe:
|
||||
# TAG-NUM-gHEX
|
||||
mo = re.search(r'^(.+)-(\d+)-g([0-9a-f]+)$', git_describe)
|
||||
if not mo:
|
||||
# unparseable. Maybe git-describe is misbehaving?
|
||||
pieces["error"] = ("unable to parse git-describe output: '%s'"
|
||||
% describe_out)
|
||||
return pieces
|
||||
|
||||
# tag
|
||||
full_tag = mo.group(1)
|
||||
if not full_tag.startswith(tag_prefix):
|
||||
if verbose:
|
||||
fmt = "tag '%s' doesn't start with prefix '%s'"
|
||||
print(fmt % (full_tag, tag_prefix))
|
||||
pieces["error"] = ("tag '%s' doesn't start with prefix '%s'"
|
||||
% (full_tag, tag_prefix))
|
||||
return pieces
|
||||
pieces["closest-tag"] = full_tag[len(tag_prefix):]
|
||||
|
||||
# distance: number of commits since tag
|
||||
pieces["distance"] = int(mo.group(2))
|
||||
|
||||
# commit: short hex revision ID
|
||||
pieces["short"] = mo.group(3)
|
||||
|
||||
else:
|
||||
# HEX: no tags
|
||||
pieces["closest-tag"] = None
|
||||
count_out, rc = run_command(GITS, ["rev-list", "HEAD", "--count"],
|
||||
cwd=root)
|
||||
pieces["distance"] = int(count_out) # total number of commits
|
||||
|
||||
# commit date: see ISO-8601 comment in git_versions_from_keywords()
|
||||
date = run_command(GITS, ["show", "-s", "--format=%ci", "HEAD"],
|
||||
cwd=root)[0].strip()
|
||||
pieces["date"] = date.strip().replace(" ", "T", 1).replace(" ", "", 1)
|
||||
|
||||
return pieces
|
||||
|
||||
|
||||
def plus_or_dot(pieces):
|
||||
"""Return a + if we don't already have one, else return a ."""
|
||||
if "+" in pieces.get("closest-tag", ""):
|
||||
return "."
|
||||
return "+"
|
||||
|
||||
|
||||
def render_pep440(pieces):
|
||||
"""Build up version string, with post-release "local version identifier".
|
||||
|
||||
Our goal: TAG[+DISTANCE.gHEX[.dirty]] . Note that if you
|
||||
get a tagged build and then dirty it, you'll get TAG+0.gHEX.dirty
|
||||
|
||||
Exceptions:
|
||||
1: no tags. git_describe was just HEX. 0+untagged.DISTANCE.gHEX[.dirty]
|
||||
"""
|
||||
if pieces["closest-tag"]:
|
||||
rendered = pieces["closest-tag"]
|
||||
if pieces["distance"] or pieces["dirty"]:
|
||||
rendered += plus_or_dot(pieces)
|
||||
rendered += "%d.g%s" % (pieces["distance"], pieces["short"])
|
||||
if pieces["dirty"]:
|
||||
rendered += ".dirty"
|
||||
else:
|
||||
# exception #1
|
||||
rendered = "0+untagged.%d.g%s" % (pieces["distance"],
|
||||
pieces["short"])
|
||||
if pieces["dirty"]:
|
||||
rendered += ".dirty"
|
||||
return rendered
|
||||
|
||||
|
||||
def render_pep440_pre(pieces):
|
||||
"""TAG[.post.devDISTANCE] -- No -dirty.
|
||||
|
||||
Exceptions:
|
||||
1: no tags. 0.post.devDISTANCE
|
||||
"""
|
||||
if pieces["closest-tag"]:
|
||||
rendered = pieces["closest-tag"]
|
||||
if pieces["distance"]:
|
||||
rendered += ".post.dev%d" % pieces["distance"]
|
||||
else:
|
||||
# exception #1
|
||||
rendered = "0.post.dev%d" % pieces["distance"]
|
||||
return rendered
|
||||
|
||||
|
||||
def render_pep440_post(pieces):
|
||||
"""TAG[.postDISTANCE[.dev0]+gHEX] .
|
||||
|
||||
The ".dev0" means dirty. Note that .dev0 sorts backwards
|
||||
(a dirty tree will appear "older" than the corresponding clean one),
|
||||
but you shouldn't be releasing software with -dirty anyways.
|
||||
|
||||
Exceptions:
|
||||
1: no tags. 0.postDISTANCE[.dev0]
|
||||
"""
|
||||
if pieces["closest-tag"]:
|
||||
rendered = pieces["closest-tag"]
|
||||
if pieces["distance"] or pieces["dirty"]:
|
||||
rendered += ".post%d" % pieces["distance"]
|
||||
if pieces["dirty"]:
|
||||
rendered += ".dev0"
|
||||
rendered += plus_or_dot(pieces)
|
||||
rendered += "g%s" % pieces["short"]
|
||||
else:
|
||||
# exception #1
|
||||
rendered = "0.post%d" % pieces["distance"]
|
||||
if pieces["dirty"]:
|
||||
rendered += ".dev0"
|
||||
rendered += "+g%s" % pieces["short"]
|
||||
return rendered
|
||||
|
||||
|
||||
def render_pep440_old(pieces):
|
||||
"""TAG[.postDISTANCE[.dev0]] .
|
||||
|
||||
The ".dev0" means dirty.
|
||||
|
||||
Eexceptions:
|
||||
1: no tags. 0.postDISTANCE[.dev0]
|
||||
"""
|
||||
if pieces["closest-tag"]:
|
||||
rendered = pieces["closest-tag"]
|
||||
if pieces["distance"] or pieces["dirty"]:
|
||||
rendered += ".post%d" % pieces["distance"]
|
||||
if pieces["dirty"]:
|
||||
rendered += ".dev0"
|
||||
else:
|
||||
# exception #1
|
||||
rendered = "0.post%d" % pieces["distance"]
|
||||
if pieces["dirty"]:
|
||||
rendered += ".dev0"
|
||||
return rendered
|
||||
|
||||
|
||||
def render_git_describe(pieces):
|
||||
"""TAG[-DISTANCE-gHEX][-dirty].
|
||||
|
||||
Like 'git describe --tags --dirty --always'.
|
||||
|
||||
Exceptions:
|
||||
1: no tags. HEX[-dirty] (note: no 'g' prefix)
|
||||
"""
|
||||
if pieces["closest-tag"]:
|
||||
rendered = pieces["closest-tag"]
|
||||
if pieces["distance"]:
|
||||
rendered += "-%d-g%s" % (pieces["distance"], pieces["short"])
|
||||
else:
|
||||
# exception #1
|
||||
rendered = pieces["short"]
|
||||
if pieces["dirty"]:
|
||||
rendered += "-dirty"
|
||||
return rendered
|
||||
|
||||
|
||||
def render_git_describe_long(pieces):
|
||||
"""TAG-DISTANCE-gHEX[-dirty].
|
||||
|
||||
Like 'git describe --tags --dirty --always -long'.
|
||||
The distance/hash is unconditional.
|
||||
|
||||
Exceptions:
|
||||
1: no tags. HEX[-dirty] (note: no 'g' prefix)
|
||||
"""
|
||||
if pieces["closest-tag"]:
|
||||
rendered = pieces["closest-tag"]
|
||||
rendered += "-%d-g%s" % (pieces["distance"], pieces["short"])
|
||||
else:
|
||||
# exception #1
|
||||
rendered = pieces["short"]
|
||||
if pieces["dirty"]:
|
||||
rendered += "-dirty"
|
||||
return rendered
|
||||
|
||||
|
||||
def render(pieces, style):
|
||||
"""Render the given version pieces into the requested style."""
|
||||
if pieces["error"]:
|
||||
return {"version": "unknown",
|
||||
"full-revisionid": pieces.get("long"),
|
||||
"dirty": None,
|
||||
"error": pieces["error"],
|
||||
"date": None}
|
||||
|
||||
if not style or style == "default":
|
||||
style = "pep440" # the default
|
||||
|
||||
if style == "pep440":
|
||||
rendered = render_pep440(pieces)
|
||||
elif style == "pep440-pre":
|
||||
rendered = render_pep440_pre(pieces)
|
||||
elif style == "pep440-post":
|
||||
rendered = render_pep440_post(pieces)
|
||||
elif style == "pep440-old":
|
||||
rendered = render_pep440_old(pieces)
|
||||
elif style == "git-describe":
|
||||
rendered = render_git_describe(pieces)
|
||||
elif style == "git-describe-long":
|
||||
rendered = render_git_describe_long(pieces)
|
||||
else:
|
||||
raise ValueError("unknown style '%s'" % style)
|
||||
|
||||
return {"version": rendered, "full-revisionid": pieces["long"],
|
||||
"dirty": pieces["dirty"], "error": None,
|
||||
"date": pieces.get("date")}
|
||||
|
||||
|
||||
def get_versions():
|
||||
"""Get version information or return default if unable to do so."""
|
||||
# I am in _version.py, which lives at ROOT/VERSIONFILE_SOURCE. If we have
|
||||
# __file__, we can work backwards from there to the root. Some
|
||||
# py2exe/bbfreeze/non-CPython implementations don't do __file__, in which
|
||||
# case we can only use expanded keywords.
|
||||
|
||||
cfg = get_config()
|
||||
verbose = cfg.verbose
|
||||
|
||||
try:
|
||||
return git_versions_from_keywords(get_keywords(), cfg.tag_prefix,
|
||||
verbose)
|
||||
except NotThisMethod:
|
||||
pass
|
||||
|
||||
try:
|
||||
root = os.path.realpath(__file__)
|
||||
# versionfile_source is the relative path from the top of the source
|
||||
# tree (where the .git directory might live) to this file. Invert
|
||||
# this to find the root from __file__.
|
||||
for i in cfg.versionfile_source.split('/'):
|
||||
root = os.path.dirname(root)
|
||||
except NameError:
|
||||
return {"version": "0+unknown", "full-revisionid": None,
|
||||
"dirty": None,
|
||||
"error": "unable to find root of source tree",
|
||||
"date": None}
|
||||
|
||||
try:
|
||||
pieces = git_pieces_from_vcs(cfg.tag_prefix, root, verbose)
|
||||
return render(pieces, cfg.style)
|
||||
except NotThisMethod:
|
||||
pass
|
||||
|
||||
try:
|
||||
if cfg.parentdir_prefix:
|
||||
return versions_from_parentdir(cfg.parentdir_prefix, root, verbose)
|
||||
except NotThisMethod:
|
||||
pass
|
||||
|
||||
return {"version": "0+unknown", "full-revisionid": None,
|
||||
"dirty": None,
|
||||
"error": "unable to compute version", "date": None}
|
||||
|
|
|
|||
|
|
@ -1,96 +1,22 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
from PyQt5 import QtWidgets, QtCore, QtGui
|
||||
from PyQt5 import QtWidgets
|
||||
|
||||
from artiq.applets.simple import SimpleApplet
|
||||
from artiq.tools import scale_from_metadata
|
||||
from artiq.gui.tools import LayoutWidget
|
||||
|
||||
|
||||
class QResponsiveLCDNumber(QtWidgets.QLCDNumber):
|
||||
doubleClicked = QtCore.pyqtSignal()
|
||||
|
||||
def mouseDoubleClickEvent(self, event):
|
||||
self.doubleClicked.emit()
|
||||
|
||||
|
||||
class QCancellableLineEdit(QtWidgets.QLineEdit):
|
||||
editCancelled = QtCore.pyqtSignal()
|
||||
|
||||
def keyPressEvent(self, event):
|
||||
if event.key() == QtCore.Qt.Key_Escape:
|
||||
self.editCancelled.emit()
|
||||
else:
|
||||
super().keyPressEvent(event)
|
||||
|
||||
|
||||
class NumberWidget(LayoutWidget):
|
||||
def __init__(self, args, req):
|
||||
LayoutWidget.__init__(self)
|
||||
class NumberWidget(QtWidgets.QLCDNumber):
|
||||
def __init__(self, args):
|
||||
QtWidgets.QLCDNumber.__init__(self)
|
||||
self.setDigitCount(args.digit_count)
|
||||
self.dataset_name = args.dataset
|
||||
self.req = req
|
||||
self.metadata = dict()
|
||||
|
||||
self.number_area = QtWidgets.QStackedWidget()
|
||||
self.addWidget(self.number_area, 0, 0)
|
||||
|
||||
self.unit_area = QtWidgets.QLabel()
|
||||
self.unit_area.setAlignment(QtCore.Qt.AlignRight | QtCore.Qt.AlignTop)
|
||||
self.addWidget(self.unit_area, 0, 1)
|
||||
|
||||
self.lcd_widget = QResponsiveLCDNumber()
|
||||
self.lcd_widget.setDigitCount(args.digit_count)
|
||||
self.lcd_widget.doubleClicked.connect(self.start_edit)
|
||||
self.number_area.addWidget(self.lcd_widget)
|
||||
|
||||
self.edit_widget = QCancellableLineEdit()
|
||||
self.edit_widget.setValidator(QtGui.QDoubleValidator())
|
||||
self.edit_widget.setAlignment(QtCore.Qt.AlignRight | QtCore.Qt.AlignVCenter)
|
||||
self.edit_widget.editCancelled.connect(self.cancel_edit)
|
||||
self.edit_widget.returnPressed.connect(self.confirm_edit)
|
||||
self.number_area.addWidget(self.edit_widget)
|
||||
|
||||
font = QtGui.QFont()
|
||||
font.setPointSize(60)
|
||||
self.edit_widget.setFont(font)
|
||||
|
||||
unit_font = QtGui.QFont()
|
||||
unit_font.setPointSize(20)
|
||||
self.unit_area.setFont(unit_font)
|
||||
|
||||
self.number_area.setCurrentWidget(self.lcd_widget)
|
||||
|
||||
def start_edit(self):
|
||||
# QLCDNumber value property contains the value of zero
|
||||
# if the displayed value is not a number.
|
||||
self.edit_widget.setText(str(self.lcd_widget.value()))
|
||||
self.edit_widget.selectAll()
|
||||
self.edit_widget.setFocus()
|
||||
self.number_area.setCurrentWidget(self.edit_widget)
|
||||
|
||||
def confirm_edit(self):
|
||||
scale = scale_from_metadata(self.metadata)
|
||||
val = float(self.edit_widget.text())
|
||||
val *= scale
|
||||
self.req.set_dataset(self.dataset_name, val, **self.metadata)
|
||||
self.number_area.setCurrentWidget(self.lcd_widget)
|
||||
|
||||
def cancel_edit(self):
|
||||
self.number_area.setCurrentWidget(self.lcd_widget)
|
||||
|
||||
def data_changed(self, value, metadata, persist, mods):
|
||||
def data_changed(self, data, mods):
|
||||
try:
|
||||
self.metadata = metadata[self.dataset_name]
|
||||
# This applet will degenerate other scalar types to native float on edit
|
||||
# Use the dashboard ChangeEditDialog for consistent type casting
|
||||
val = float(value[self.dataset_name])
|
||||
scale = scale_from_metadata(self.metadata)
|
||||
val /= scale
|
||||
n = float(data[self.dataset_name][1])
|
||||
except (KeyError, ValueError, TypeError):
|
||||
val = "---"
|
||||
|
||||
unit = self.metadata.get("unit", "")
|
||||
self.unit_area.setText(unit)
|
||||
self.lcd_widget.display(val)
|
||||
n = "---"
|
||||
self.display(n)
|
||||
|
||||
|
||||
def main():
|
||||
|
|
|
|||
|
|
@ -7,13 +7,13 @@ from artiq.applets.simple import SimpleApplet
|
|||
|
||||
|
||||
class Image(pyqtgraph.ImageView):
|
||||
def __init__(self, args, req):
|
||||
def __init__(self, args):
|
||||
pyqtgraph.ImageView.__init__(self)
|
||||
self.args = args
|
||||
|
||||
def data_changed(self, value, metadata, persist, mods):
|
||||
def data_changed(self, data, mods):
|
||||
try:
|
||||
img = value[self.args.img]
|
||||
img = data[self.args.img][1]
|
||||
except KeyError:
|
||||
return
|
||||
self.setImage(img)
|
||||
|
|
|
|||
|
|
@ -1,47 +1,33 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import PyQt5 # make sure pyqtgraph imports Qt5
|
||||
from PyQt5.QtCore import QTimer
|
||||
import PyQt5 # make sure pyqtgraph imports Qt5
|
||||
import pyqtgraph
|
||||
|
||||
from artiq.applets.simple import TitleApplet
|
||||
|
||||
|
||||
class HistogramPlot(pyqtgraph.PlotWidget):
|
||||
def __init__(self, args, req):
|
||||
def __init__(self, args):
|
||||
pyqtgraph.PlotWidget.__init__(self)
|
||||
self.args = args
|
||||
self.timer = QTimer()
|
||||
self.timer.setSingleShot(True)
|
||||
self.timer.timeout.connect(self.length_warning)
|
||||
|
||||
def data_changed(self, value, metadata, persist, mods, title):
|
||||
def data_changed(self, data, mods, title):
|
||||
try:
|
||||
y = value[self.args.y]
|
||||
y = data[self.args.y][1]
|
||||
if self.args.x is None:
|
||||
x = None
|
||||
else:
|
||||
x = value[self.args.x]
|
||||
x = data[self.args.x][1]
|
||||
except KeyError:
|
||||
return
|
||||
if x is None:
|
||||
x = list(range(len(y)+1))
|
||||
|
||||
if len(y) and len(x) == len(y) + 1:
|
||||
self.timer.stop()
|
||||
self.clear()
|
||||
self.plot(x, y, stepMode=True, fillLevel=0,
|
||||
brush=(0, 0, 255, 150))
|
||||
self.setTitle(title)
|
||||
else:
|
||||
if not self.timer.isActive():
|
||||
self.timer.start(1000)
|
||||
|
||||
def length_warning(self):
|
||||
self.clear()
|
||||
text = "⚠️ dataset lengths mismatch:\n"\
|
||||
"There should be one more bin boundaries than there are Y values"
|
||||
self.addItem(pyqtgraph.TextItem(text))
|
||||
|
||||
|
||||
def main():
|
||||
|
|
|
|||
|
|
@ -2,58 +2,39 @@
|
|||
|
||||
import numpy as np
|
||||
import PyQt5 # make sure pyqtgraph imports Qt5
|
||||
from PyQt5.QtCore import QTimer
|
||||
import pyqtgraph
|
||||
|
||||
from artiq.applets.simple import TitleApplet
|
||||
|
||||
|
||||
class XYPlot(pyqtgraph.PlotWidget):
|
||||
def __init__(self, args, req):
|
||||
def __init__(self, args):
|
||||
pyqtgraph.PlotWidget.__init__(self)
|
||||
self.args = args
|
||||
self.timer = QTimer()
|
||||
self.timer.setSingleShot(True)
|
||||
self.timer.timeout.connect(self.length_warning)
|
||||
self.mismatch = {'X values': False,
|
||||
'Error bars': False,
|
||||
'Fit values': False}
|
||||
|
||||
def data_changed(self, value, metadata, persist, mods, title):
|
||||
def data_changed(self, data, mods, title):
|
||||
try:
|
||||
y = value[self.args.y]
|
||||
y = data[self.args.y][1]
|
||||
except KeyError:
|
||||
return
|
||||
x = value.get(self.args.x, (False, None))
|
||||
x = data.get(self.args.x, (False, None))[1]
|
||||
if x is None:
|
||||
x = np.arange(len(y))
|
||||
error = value.get(self.args.error, (False, None))
|
||||
fit = value.get(self.args.fit, (False, None))
|
||||
error = data.get(self.args.error, (False, None))[1]
|
||||
fit = data.get(self.args.fit, (False, None))[1]
|
||||
|
||||
if not len(y) or len(y) != len(x):
|
||||
self.mismatch['X values'] = True
|
||||
else:
|
||||
self.mismatch['X values'] = False
|
||||
return
|
||||
if error is not None and hasattr(error, "__len__"):
|
||||
if not len(error):
|
||||
error = None
|
||||
elif len(error) != len(y):
|
||||
self.mismatch['Error bars'] = True
|
||||
else:
|
||||
self.mismatch['Error bars'] = False
|
||||
return
|
||||
if fit is not None:
|
||||
if not len(fit):
|
||||
fit = None
|
||||
elif len(fit) != len(y):
|
||||
self.mismatch['Fit values'] = True
|
||||
else:
|
||||
self.mismatch['Fit values'] = False
|
||||
if not any(self.mismatch.values()):
|
||||
self.timer.stop()
|
||||
else:
|
||||
if not self.timer.isActive():
|
||||
self.timer.start(1000)
|
||||
return
|
||||
return
|
||||
|
||||
self.clear()
|
||||
self.plot(x, y, pen=None, symbol="x")
|
||||
|
|
@ -69,13 +50,6 @@ class XYPlot(pyqtgraph.PlotWidget):
|
|||
xi = np.argsort(x)
|
||||
self.plot(x[xi], fit[xi])
|
||||
|
||||
def length_warning(self):
|
||||
self.clear()
|
||||
text = "⚠️ dataset lengths mismatch:\n"
|
||||
errors = ', '.join([k for k, v in self.mismatch.items() if v])
|
||||
text = ' '.join([errors, "should have the same length as Y values"])
|
||||
self.addItem(pyqtgraph.TextItem(text))
|
||||
|
||||
|
||||
def main():
|
||||
applet = TitleApplet(XYPlot)
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@
|
|||
|
||||
import numpy as np
|
||||
from PyQt5 import QtWidgets
|
||||
from PyQt5.QtCore import QTimer
|
||||
import pyqtgraph
|
||||
|
||||
from artiq.applets.simple import SimpleApplet
|
||||
|
|
@ -22,7 +21,7 @@ def _compute_ys(histogram_bins, histograms_counts):
|
|||
# pyqtgraph.GraphicsWindow fails to behave like a regular Qt widget
|
||||
# and breaks embedding. Do not use as top widget.
|
||||
class XYHistPlot(QtWidgets.QSplitter):
|
||||
def __init__(self, args, req):
|
||||
def __init__(self, args):
|
||||
QtWidgets.QSplitter.__init__(self)
|
||||
self.resize(1000, 600)
|
||||
self.setWindowTitle("XY/Histogram")
|
||||
|
|
@ -38,10 +37,6 @@ class XYHistPlot(QtWidgets.QSplitter):
|
|||
self.hist_plot_data = None
|
||||
|
||||
self.args = args
|
||||
self.timer = QTimer()
|
||||
self.timer.setSingleShot(True)
|
||||
self.timer.timeout.connect(self.length_warning)
|
||||
self.mismatch = {'bins': False, 'xs': False}
|
||||
|
||||
def _set_full_data(self, xs, histogram_bins, histograms_counts):
|
||||
self.xy_plot.clear()
|
||||
|
|
@ -64,9 +59,9 @@ class XYHistPlot(QtWidgets.QSplitter):
|
|||
point.histogram_index = index
|
||||
point.histogram_counts = counts
|
||||
|
||||
text = "click on a data point at the left\n"\
|
||||
"to see the corresponding histogram"
|
||||
self.hist_plot.addItem(pyqtgraph.TextItem(text))
|
||||
self.hist_plot_data = self.hist_plot.plot(
|
||||
stepMode=True, fillLevel=0,
|
||||
brush=(0, 0, 255, 150))
|
||||
|
||||
def _set_partial_data(self, xs, histograms_counts):
|
||||
ys = _compute_ys(self.histogram_bins, histograms_counts)
|
||||
|
|
@ -92,17 +87,8 @@ class XYHistPlot(QtWidgets.QSplitter):
|
|||
else:
|
||||
self.arrow.setPos(position)
|
||||
self.selected_index = spot_item.histogram_index
|
||||
|
||||
if self.hist_plot_data is None:
|
||||
self.hist_plot.clear()
|
||||
self.hist_plot_data = self.hist_plot.plot(
|
||||
x=self.histogram_bins,
|
||||
y=spot_item.histogram_counts,
|
||||
stepMode=True, fillLevel=0,
|
||||
brush=(0, 0, 255, 150))
|
||||
else:
|
||||
self.hist_plot_data.setData(x=self.histogram_bins,
|
||||
y=spot_item.histogram_counts)
|
||||
self.hist_plot_data.setData(x=self.histogram_bins,
|
||||
y=spot_item.histogram_counts)
|
||||
|
||||
def _can_use_partial(self, mods):
|
||||
if self.hist_plot_data is None:
|
||||
|
|
@ -124,48 +110,18 @@ class XYHistPlot(QtWidgets.QSplitter):
|
|||
return False
|
||||
return True
|
||||
|
||||
def data_changed(self, value, metadata, persist, mods):
|
||||
def data_changed(self, data, mods):
|
||||
try:
|
||||
xs = value[self.args.xs]
|
||||
histogram_bins = value[self.args.histogram_bins]
|
||||
histograms_counts = value[self.args.histograms_counts]
|
||||
xs = data[self.args.xs][1]
|
||||
histogram_bins = data[self.args.histogram_bins][1]
|
||||
histograms_counts = data[self.args.histograms_counts][1]
|
||||
except KeyError:
|
||||
return
|
||||
if len(xs) != histograms_counts.shape[0]:
|
||||
self.mismatch['xs'] = True
|
||||
else:
|
||||
self.mismatch['xs'] = False
|
||||
if histograms_counts.shape[1] != len(histogram_bins) - 1:
|
||||
self.mismatch['bins'] = True
|
||||
else:
|
||||
self.mismatch['bins'] = False
|
||||
if any(self.mismatch.values()):
|
||||
if not self.timer.isActive():
|
||||
self.timer.start(1000)
|
||||
return
|
||||
else:
|
||||
self.timer.stop()
|
||||
if self._can_use_partial(mods):
|
||||
self._set_partial_data(xs, histograms_counts)
|
||||
else:
|
||||
self._set_full_data(xs, histogram_bins, histograms_counts)
|
||||
|
||||
def length_warning(self):
|
||||
self.xy_plot.clear()
|
||||
self.hist_plot.clear()
|
||||
text = "⚠️ dataset lengths mismatch:\n\n"
|
||||
if self.mismatch['bins']:
|
||||
text = ''.join([text,
|
||||
"bin boundaries should have the same length\n"
|
||||
"as the first dimension of histogram counts."])
|
||||
if self.mismatch['bins'] and self.mismatch['xs']:
|
||||
text = ''.join([text, '\n\n'])
|
||||
if self.mismatch['xs']:
|
||||
text = ''.join([text,
|
||||
"point abscissas should have the same length\n"
|
||||
"as the second dimension of histogram counts."])
|
||||
self.xy_plot.addItem(pyqtgraph.TextItem(text))
|
||||
|
||||
|
||||
def main():
|
||||
applet = SimpleApplet(XYHistPlot)
|
||||
|
|
|
|||
|
|
@ -1,34 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
from PyQt5 import QtWidgets
|
||||
|
||||
from artiq.applets.simple import SimpleApplet
|
||||
|
||||
|
||||
class ProgressWidget(QtWidgets.QProgressBar):
|
||||
def __init__(self, args, req):
|
||||
QtWidgets.QProgressBar.__init__(self)
|
||||
self.setMinimum(args.min)
|
||||
self.setMaximum(args.max)
|
||||
self.dataset_value = args.value
|
||||
|
||||
def data_changed(self, value, metadata, persist, mods):
|
||||
try:
|
||||
val = round(value[self.dataset_value])
|
||||
except (KeyError, ValueError, TypeError):
|
||||
val = 0
|
||||
self.setValue(val)
|
||||
|
||||
|
||||
|
||||
def main():
|
||||
applet = SimpleApplet(ProgressWidget)
|
||||
applet.add_dataset("value", "counter")
|
||||
applet.argparser.add_argument("--min", type=int, default=0,
|
||||
help="minimum (left) value of the bar")
|
||||
applet.argparser.add_argument("--max", type=int, default=100,
|
||||
help="maximum (right) value of the bar")
|
||||
applet.run()
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -4,115 +4,16 @@ import asyncio
|
|||
import os
|
||||
import string
|
||||
|
||||
from qasync import QEventLoop, QtWidgets, QtCore
|
||||
from quamash import QEventLoop, QtWidgets, QtCore
|
||||
|
||||
from sipyco.sync_struct import Subscriber, process_mod
|
||||
from sipyco.pc_rpc import AsyncioClient as RPCClient
|
||||
from sipyco import pyon
|
||||
from sipyco.pipe_ipc import AsyncioChildComm
|
||||
|
||||
from artiq.language.scan import ScanObject
|
||||
from artiq.protocols.sync_struct import Subscriber, process_mod
|
||||
from artiq.protocols import pyon
|
||||
from artiq.protocols.pipe_ipc import AsyncioChildComm
|
||||
|
||||
|
||||
logger = logging.getLogger(__name__)
|
||||
|
||||
|
||||
class _AppletRequestInterface:
|
||||
def __init__(self):
|
||||
raise NotImplementedError
|
||||
|
||||
def set_dataset(self, key, value, unit=None, scale=None, precision=None, persist=None):
|
||||
"""
|
||||
Set a dataset.
|
||||
See documentation of ``artiq.language.environment.set_dataset``.
|
||||
"""
|
||||
raise NotImplementedError
|
||||
|
||||
def mutate_dataset(self, key, index, value):
|
||||
"""
|
||||
Mutate a dataset.
|
||||
See documentation of ``artiq.language.environment.mutate_dataset``.
|
||||
"""
|
||||
raise NotImplementedError
|
||||
|
||||
def append_to_dataset(self, key, value):
|
||||
"""
|
||||
Append to a dataset.
|
||||
See documentation of ``artiq.language.environment.append_to_dataset``.
|
||||
"""
|
||||
raise NotImplementedError
|
||||
|
||||
def set_argument_value(self, expurl, name, value):
|
||||
"""
|
||||
Temporarily set the value of an argument in a experiment in the dashboard.
|
||||
The value resets to default value when recomputing the argument.
|
||||
|
||||
:param expurl: Experiment URL identifying the experiment in the dashboard. Example: 'repo:ArgumentsDemo'.
|
||||
:param name: Name of the argument in the experiment.
|
||||
:param value: Object representing the new temporary value of the argument. For ``Scannable`` arguments, this parameter
|
||||
should be a ``ScanObject``. The type of the ``ScanObject`` will be set as the selected type when this function is called.
|
||||
"""
|
||||
raise NotImplementedError
|
||||
|
||||
|
||||
class AppletRequestIPC(_AppletRequestInterface):
|
||||
def __init__(self, ipc):
|
||||
self.ipc = ipc
|
||||
|
||||
def set_dataset(self, key, value, unit=None, scale=None, precision=None, persist=None):
|
||||
metadata = {}
|
||||
if unit is not None:
|
||||
metadata["unit"] = unit
|
||||
if scale is not None:
|
||||
metadata["scale"] = scale
|
||||
if precision is not None:
|
||||
metadata["precision"] = precision
|
||||
self.ipc.set_dataset(key, value, metadata, persist)
|
||||
|
||||
def mutate_dataset(self, key, index, value):
|
||||
mod = {"action": "setitem", "path": [key, 1], "key": index, "value": value}
|
||||
self.ipc.update_dataset(mod)
|
||||
|
||||
def append_to_dataset(self, key, value):
|
||||
mod = {"action": "append", "path": [key, 1], "x": value}
|
||||
self.ipc.update_dataset(mod)
|
||||
|
||||
def set_argument_value(self, expurl, name, value):
|
||||
if isinstance(value, ScanObject):
|
||||
value = value.describe()
|
||||
self.ipc.set_argument_value(expurl, name, value)
|
||||
|
||||
|
||||
class AppletRequestRPC(_AppletRequestInterface):
|
||||
def __init__(self, loop, dataset_ctl):
|
||||
self.loop = loop
|
||||
self.dataset_ctl = dataset_ctl
|
||||
self.background_tasks = set()
|
||||
|
||||
def _background(self, coro, *args, **kwargs):
|
||||
task = self.loop.create_task(coro(*args, **kwargs))
|
||||
self.background_tasks.add(task)
|
||||
task.add_done_callback(self.background_tasks.discard)
|
||||
|
||||
def set_dataset(self, key, value, unit=None, scale=None, precision=None, persist=None):
|
||||
metadata = {}
|
||||
if unit is not None:
|
||||
metadata["unit"] = unit
|
||||
if scale is not None:
|
||||
metadata["scale"] = scale
|
||||
if precision is not None:
|
||||
metadata["precision"] = precision
|
||||
self._background(self.dataset_ctl.set, key, value, metadata=metadata, persist=persist)
|
||||
|
||||
def mutate_dataset(self, key, index, value):
|
||||
mod = {"action": "setitem", "path": [key, 1], "key": index, "value": value}
|
||||
self._background(self.dataset_ctl.update, mod)
|
||||
|
||||
def append_to_dataset(self, key, value):
|
||||
mod = {"action": "append", "path": [key, 1], "x": value}
|
||||
self._background(self.dataset_ctl.update, mod)
|
||||
|
||||
|
||||
class AppletIPCClient(AsyncioChildComm):
|
||||
def set_close_cb(self, close_cb):
|
||||
self.close_cb = close_cb
|
||||
|
|
@ -163,30 +64,12 @@ class AppletIPCClient(AsyncioChildComm):
|
|||
exc_info=True)
|
||||
self.close_cb()
|
||||
|
||||
def subscribe(self, datasets, init_cb, mod_cb, dataset_prefixes=[], *, loop):
|
||||
def subscribe(self, datasets, init_cb, mod_cb):
|
||||
self.write_pyon({"action": "subscribe",
|
||||
"datasets": datasets,
|
||||
"dataset_prefixes": dataset_prefixes})
|
||||
"datasets": datasets})
|
||||
self.init_cb = init_cb
|
||||
self.mod_cb = mod_cb
|
||||
self.listen_task = loop.create_task(self.listen())
|
||||
|
||||
def set_dataset(self, key, value, metadata, persist=None):
|
||||
self.write_pyon({"action": "set_dataset",
|
||||
"key": key,
|
||||
"value": value,
|
||||
"metadata": metadata,
|
||||
"persist": persist})
|
||||
|
||||
def update_dataset(self, mod):
|
||||
self.write_pyon({"action": "update_dataset",
|
||||
"mod": mod})
|
||||
|
||||
def set_argument_value(self, expurl, name, value):
|
||||
self.write_pyon({"action": "set_argument_value",
|
||||
"expurl": expurl,
|
||||
"name": name,
|
||||
"value": value})
|
||||
asyncio.ensure_future(self.listen())
|
||||
|
||||
|
||||
class SimpleApplet:
|
||||
|
|
@ -208,11 +91,8 @@ class SimpleApplet:
|
|||
"for dataset notifications "
|
||||
"(ignored in embedded mode)")
|
||||
group.add_argument(
|
||||
"--port-notify", default=3250, type=int,
|
||||
help="TCP port to connect to for notifications (ignored in embedded mode)")
|
||||
group.add_argument(
|
||||
"--port-control", default=3251, type=int,
|
||||
help="TCP port to connect to for control (ignored in embedded mode)")
|
||||
"--port", default=3250, type=int,
|
||||
help="TCP port to connect to")
|
||||
|
||||
self._arggroup_datasets = self.argparser.add_argument_group("datasets")
|
||||
|
||||
|
|
@ -233,11 +113,8 @@ class SimpleApplet:
|
|||
self.embed = os.getenv("ARTIQ_APPLET_EMBED")
|
||||
self.datasets = {getattr(self.args, arg.replace("-", "_"))
|
||||
for arg in self.dataset_args}
|
||||
# Optional prefixes (dataset sub-trees) to match subscriptions against;
|
||||
# currently only used by out-of-tree subclasses (ndscan).
|
||||
self.dataset_prefixes = []
|
||||
|
||||
def qasync_init(self):
|
||||
def quamash_init(self):
|
||||
app = QtWidgets.QApplication([])
|
||||
self.loop = QEventLoop(app)
|
||||
asyncio.set_event_loop(self.loop)
|
||||
|
|
@ -251,21 +128,8 @@ class SimpleApplet:
|
|||
if self.embed is not None:
|
||||
self.ipc.close()
|
||||
|
||||
def req_init(self):
|
||||
if self.embed is None:
|
||||
dataset_ctl = RPCClient()
|
||||
self.loop.run_until_complete(dataset_ctl.connect_rpc(
|
||||
self.args.server, self.args.port_control, "master_dataset_db"))
|
||||
self.req = AppletRequestRPC(self.loop, dataset_ctl)
|
||||
else:
|
||||
self.req = AppletRequestIPC(self.ipc)
|
||||
|
||||
def req_close(self):
|
||||
if self.embed is None:
|
||||
self.req.dataset_ctl.close_rpc()
|
||||
|
||||
def create_main_widget(self):
|
||||
self.main_widget = self.main_widget_class(self.args, self.req)
|
||||
self.main_widget = self.main_widget_class(self.args)
|
||||
if self.embed is not None:
|
||||
self.ipc.set_close_cb(self.main_widget.close)
|
||||
if os.name == "nt":
|
||||
|
|
@ -298,14 +162,6 @@ class SimpleApplet:
|
|||
self.data = data
|
||||
return data
|
||||
|
||||
def is_dataset_subscribed(self, key):
|
||||
if key in self.datasets:
|
||||
return True
|
||||
for prefix in self.dataset_prefixes:
|
||||
if key.startswith(prefix):
|
||||
return True
|
||||
return False
|
||||
|
||||
def filter_mod(self, mod):
|
||||
if self.embed is not None:
|
||||
# the parent already filters for us
|
||||
|
|
@ -314,19 +170,14 @@ class SimpleApplet:
|
|||
if mod["action"] == "init":
|
||||
return True
|
||||
if mod["path"]:
|
||||
return self.is_dataset_subscribed(mod["path"][0])
|
||||
return mod["path"][0] in self.datasets
|
||||
elif mod["action"] in {"setitem", "delitem"}:
|
||||
return self.is_dataset_subscribed(mod["key"])
|
||||
return mod["key"] in self.datasets
|
||||
else:
|
||||
return False
|
||||
|
||||
def emit_data_changed(self, data, mod_buffer):
|
||||
persist = dict()
|
||||
value = dict()
|
||||
metadata = dict()
|
||||
for k, d in data.items():
|
||||
persist[k], value[k], metadata[k] = d
|
||||
self.main_widget.data_changed(value, metadata, persist, mod_buffer)
|
||||
self.main_widget.data_changed(data, mod_buffer)
|
||||
|
||||
def flush_mod_buffer(self):
|
||||
self.emit_data_changed(self.data, self.mod_buffer)
|
||||
|
|
@ -341,8 +192,8 @@ class SimpleApplet:
|
|||
self.mod_buffer.append(mod)
|
||||
else:
|
||||
self.mod_buffer = [mod]
|
||||
self.loop.call_later(self.args.update_delay,
|
||||
self.flush_mod_buffer)
|
||||
asyncio.get_event_loop().call_later(self.args.update_delay,
|
||||
self.flush_mod_buffer)
|
||||
else:
|
||||
self.emit_data_changed(self.data, [mod])
|
||||
|
||||
|
|
@ -351,11 +202,9 @@ class SimpleApplet:
|
|||
self.subscriber = Subscriber("datasets",
|
||||
self.sub_init, self.sub_mod)
|
||||
self.loop.run_until_complete(self.subscriber.connect(
|
||||
self.args.server, self.args.port_notify))
|
||||
self.args.server, self.args.port))
|
||||
else:
|
||||
self.ipc.subscribe(self.datasets, self.sub_init, self.sub_mod,
|
||||
dataset_prefixes=self.dataset_prefixes,
|
||||
loop=self.loop)
|
||||
self.ipc.subscribe(self.datasets, self.sub_init, self.sub_mod)
|
||||
|
||||
def unsubscribe(self):
|
||||
if self.embed is None:
|
||||
|
|
@ -363,20 +212,16 @@ class SimpleApplet:
|
|||
|
||||
def run(self):
|
||||
self.args_init()
|
||||
self.qasync_init()
|
||||
self.quamash_init()
|
||||
try:
|
||||
self.ipc_init()
|
||||
try:
|
||||
self.req_init()
|
||||
self.create_main_widget()
|
||||
self.subscribe()
|
||||
try:
|
||||
self.create_main_widget()
|
||||
self.subscribe()
|
||||
try:
|
||||
self.loop.run_forever()
|
||||
finally:
|
||||
self.unsubscribe()
|
||||
self.loop.run_forever()
|
||||
finally:
|
||||
self.req_close()
|
||||
self.unsubscribe()
|
||||
finally:
|
||||
self.ipc_close()
|
||||
finally:
|
||||
|
|
@ -415,9 +260,4 @@ class TitleApplet(SimpleApplet):
|
|||
title = self.args.title
|
||||
else:
|
||||
title = None
|
||||
persist = dict()
|
||||
value = dict()
|
||||
metadata = dict()
|
||||
for k, d in data.items():
|
||||
persist[k], value[k], metadata[k] = d
|
||||
self.main_widget.data_changed(value, metadata, persist, mod_buffer, title)
|
||||
self.main_widget.data_changed(data, mod_buffer, title)
|
||||
|
|
|
|||
|
|
@ -3,11 +3,10 @@ import asyncio
|
|||
|
||||
from PyQt5 import QtCore, QtWidgets
|
||||
|
||||
from sipyco.pc_rpc import AsyncioClient as RPCClient
|
||||
|
||||
from artiq.tools import short_format
|
||||
from artiq.gui.tools import LayoutWidget, QRecursiveFilterProxyModel
|
||||
from artiq.gui.models import DictSyncTreeSepModel
|
||||
from artiq.protocols.pc_rpc import AsyncioClient as RPCClient
|
||||
|
||||
# reduced read-only version of artiq.dashboard.datasets
|
||||
|
||||
|
|
@ -20,46 +19,11 @@ class Model(DictSyncTreeSepModel):
|
|||
DictSyncTreeSepModel.__init__(self, ".", ["Dataset", "Value"], init)
|
||||
|
||||
def convert(self, k, v, column):
|
||||
return short_format(v[1], v[2])
|
||||
|
||||
|
||||
class DatasetCtl:
|
||||
def __init__(self, master_host, master_port):
|
||||
self.master_host = master_host
|
||||
self.master_port = master_port
|
||||
|
||||
async def _execute_rpc(self, op_name, key_or_mod, value=None, persist=None, metadata=None):
|
||||
logger.info("Starting %s operation on %s", op_name, key_or_mod)
|
||||
try:
|
||||
remote = RPCClient()
|
||||
await remote.connect_rpc(self.master_host, self.master_port,
|
||||
"master_dataset_db")
|
||||
try:
|
||||
if op_name == "set":
|
||||
await remote.set(key_or_mod, value, persist, metadata)
|
||||
elif op_name == "update":
|
||||
await remote.update(key_or_mod)
|
||||
else:
|
||||
logger.error("Invalid operation: %s", op_name)
|
||||
return
|
||||
finally:
|
||||
remote.close_rpc()
|
||||
except:
|
||||
logger.error("Failed %s operation on %s", op_name,
|
||||
key_or_mod, exc_info=True)
|
||||
else:
|
||||
logger.info("Finished %s operation on %s", op_name,
|
||||
key_or_mod)
|
||||
|
||||
async def set(self, key, value, persist=None, metadata=None):
|
||||
await self._execute_rpc("set", key, value, persist, metadata)
|
||||
|
||||
async def update(self, mod):
|
||||
await self._execute_rpc("update", mod)
|
||||
return short_format(v[1])
|
||||
|
||||
|
||||
class DatasetsDock(QtWidgets.QDockWidget):
|
||||
def __init__(self, dataset_sub, dataset_ctl):
|
||||
def __init__(self, datasets_sub, master_host, master_port):
|
||||
QtWidgets.QDockWidget.__init__(self, "Datasets")
|
||||
self.setObjectName("Datasets")
|
||||
self.setFeatures(QtWidgets.QDockWidget.DockWidgetMovable |
|
||||
|
|
@ -97,9 +61,10 @@ class DatasetsDock(QtWidgets.QDockWidget):
|
|||
self.table.addAction(upload_action)
|
||||
|
||||
self.set_model(Model(dict()))
|
||||
dataset_sub.add_setmodel_callback(self.set_model)
|
||||
datasets_sub.add_setmodel_callback(self.set_model)
|
||||
|
||||
self.dataset_ctl = dataset_ctl
|
||||
self.master_host = master_host
|
||||
self.master_port = master_port
|
||||
|
||||
def _search_datasets(self):
|
||||
if hasattr(self, "table_model_filter"):
|
||||
|
|
@ -116,14 +81,30 @@ class DatasetsDock(QtWidgets.QDockWidget):
|
|||
self.table_model_filter.setSourceModel(self.table_model)
|
||||
self.table.setModel(self.table_model_filter)
|
||||
|
||||
async def _upload_dataset(self, name, value,):
|
||||
logger.info("Uploading dataset '%s' to master...", name)
|
||||
try:
|
||||
remote = RPCClient()
|
||||
await remote.connect_rpc(self.master_host, self.master_port,
|
||||
"master_dataset_db")
|
||||
try:
|
||||
await remote.set(name, value)
|
||||
finally:
|
||||
remote.close_rpc()
|
||||
except:
|
||||
logger.error("Failed uploading dataset '%s'",
|
||||
name, exc_info=True)
|
||||
else:
|
||||
logger.info("Finished uploading dataset '%s'", name)
|
||||
|
||||
def upload_clicked(self):
|
||||
idx = self.table.selectedIndexes()
|
||||
if idx:
|
||||
idx = self.table_model_filter.mapToSource(idx[0])
|
||||
key = self.table_model.index_to_key(idx)
|
||||
if key is not None:
|
||||
persist, value, metadata = self.table_model.backing_store[key]
|
||||
asyncio.ensure_future(self.dataset_ctl.set(key, value, metadata=metadata))
|
||||
persist, value = self.table_model.backing_store[key]
|
||||
asyncio.ensure_future(self._upload_dataset(key, value))
|
||||
|
||||
def save_state(self):
|
||||
return bytes(self.table.header().saveState())
|
||||
|
|
|
|||
|
|
@ -7,17 +7,24 @@ from collections import OrderedDict
|
|||
from PyQt5 import QtCore, QtGui, QtWidgets
|
||||
import h5py
|
||||
|
||||
from sipyco import pyon
|
||||
|
||||
from artiq import __artiq_dir__ as artiq_dir
|
||||
from artiq.gui.tools import (LayoutWidget, WheelFilter,
|
||||
log_level_to_name, get_open_file_name)
|
||||
from artiq.gui.tools import LayoutWidget, log_level_to_name, get_open_file_name
|
||||
from artiq.gui.entries import procdesc_to_entry
|
||||
from artiq.protocols import pyon
|
||||
from artiq.master.worker import Worker, log_worker_exception
|
||||
|
||||
logger = logging.getLogger(__name__)
|
||||
|
||||
|
||||
class _WheelFilter(QtCore.QObject):
|
||||
def eventFilter(self, obj, event):
|
||||
if (event.type() == QtCore.QEvent.Wheel and
|
||||
event.modifiers() != QtCore.Qt.NoModifier):
|
||||
event.ignore()
|
||||
return True
|
||||
return False
|
||||
|
||||
|
||||
class _ArgumentEditor(QtWidgets.QTreeWidget):
|
||||
def __init__(self, dock):
|
||||
QtWidgets.QTreeWidget.__init__(self)
|
||||
|
|
@ -38,7 +45,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
|
|||
self.setStyleSheet("QTreeWidget {background: " +
|
||||
self.palette().midlight().color().name() + " ;}")
|
||||
|
||||
self.viewport().installEventFilter(WheelFilter(self.viewport(), True))
|
||||
self.viewport().installEventFilter(_WheelFilter(self.viewport()))
|
||||
|
||||
self._groups = dict()
|
||||
self._arg_to_widgets = dict()
|
||||
|
|
@ -370,9 +377,9 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
|
||||
|
||||
class LocalDatasetDB:
|
||||
def __init__(self, dataset_sub):
|
||||
self.dataset_sub = dataset_sub
|
||||
dataset_sub.add_setmodel_callback(self.init)
|
||||
def __init__(self, datasets_sub):
|
||||
self.datasets_sub = datasets_sub
|
||||
datasets_sub.add_setmodel_callback(self.init)
|
||||
|
||||
def init(self, data):
|
||||
self._data = data
|
||||
|
|
@ -381,11 +388,11 @@ class LocalDatasetDB:
|
|||
return self._data.backing_store[key][1]
|
||||
|
||||
def update(self, mod):
|
||||
self.dataset_sub.update(mod)
|
||||
self.datasets_sub.update(mod)
|
||||
|
||||
|
||||
class ExperimentsArea(QtWidgets.QMdiArea):
|
||||
def __init__(self, root, dataset_sub):
|
||||
def __init__(self, root, datasets_sub):
|
||||
QtWidgets.QMdiArea.__init__(self)
|
||||
self.pixmap = QtGui.QPixmap(os.path.join(
|
||||
artiq_dir, "gui", "logo_ver.svg"))
|
||||
|
|
@ -394,11 +401,11 @@ class ExperimentsArea(QtWidgets.QMdiArea):
|
|||
|
||||
self.open_experiments = []
|
||||
|
||||
self._ddb = LocalDatasetDB(dataset_sub)
|
||||
self._ddb = LocalDatasetDB(datasets_sub)
|
||||
|
||||
self.worker_handlers = {
|
||||
"get_device_db": lambda: {},
|
||||
"get_device": lambda key, resolve_alias=False: {"type": "dummy"},
|
||||
"get_device": lambda k: {"type": "dummy"},
|
||||
"get_dataset": self._ddb.get,
|
||||
"update_dataset": self._ddb.update,
|
||||
}
|
||||
|
|
@ -508,9 +515,5 @@ class ExperimentsArea(QtWidgets.QMdiArea):
|
|||
self.open_experiments.append(dock)
|
||||
return dock
|
||||
|
||||
def set_argument_value(self, expurl, name, value):
|
||||
logger.warning("Unable to set argument '%s', dropping change. "
|
||||
"'set_argument_value' not supported in browser.", name)
|
||||
|
||||
def on_dock_closed(self, dock):
|
||||
self.open_experiments.remove(dock)
|
||||
|
|
|
|||
|
|
@ -5,8 +5,7 @@ from datetime import datetime
|
|||
import h5py
|
||||
from PyQt5 import QtCore, QtWidgets, QtGui
|
||||
|
||||
from sipyco import pyon
|
||||
|
||||
from artiq.protocols import pyon
|
||||
|
||||
logger = logging.getLogger(__name__)
|
||||
|
||||
|
|
@ -42,7 +41,7 @@ class ThumbnailIconProvider(QtWidgets.QFileIconProvider):
|
|||
except KeyError:
|
||||
return
|
||||
try:
|
||||
img = QtGui.QImage.fromData(t[()])
|
||||
img = QtGui.QImage.fromData(t.value)
|
||||
except:
|
||||
logger.warning("unable to read thumbnail from %s",
|
||||
info.filePath(), exc_info=True)
|
||||
|
|
@ -71,7 +70,7 @@ class ZoomIconView(QtWidgets.QListView):
|
|||
self._char_width = QtGui.QFontMetrics(self.font()).averageCharWidth()
|
||||
self.setViewMode(self.IconMode)
|
||||
w = self._char_width*self.default_size
|
||||
self.setIconSize(QtCore.QSize(w, int(w*self.aspect)))
|
||||
self.setIconSize(QtCore.QSize(w, w*self.aspect))
|
||||
self.setFlow(self.LeftToRight)
|
||||
self.setResizeMode(self.Adjust)
|
||||
self.setWrapping(True)
|
||||
|
|
@ -102,14 +101,13 @@ class Hdf5FileSystemModel(QtWidgets.QFileSystemModel):
|
|||
h5 = open_h5(info)
|
||||
if h5 is not None:
|
||||
try:
|
||||
expid = pyon.decode(h5["expid"][()]) if "expid" in h5 else dict()
|
||||
start_time = datetime.fromtimestamp(h5["start_time"][()]) if "start_time" in h5 else "<none>"
|
||||
expid = pyon.decode(h5["expid"].value)
|
||||
start_time = datetime.fromtimestamp(h5["start_time"].value)
|
||||
v = ("artiq_version: {}\nrepo_rev: {}\nfile: {}\n"
|
||||
"class_name: {}\nrid: {}\nstart_time: {}").format(
|
||||
h5["artiq_version"].asstr()[()] if "artiq_version" in h5 else "<none>",
|
||||
expid.get("repo_rev", "<none>"),
|
||||
expid.get("file", "<none>"), expid.get("class_name", "<none>"),
|
||||
h5["rid"][()] if "rid" in h5 else "<none>", start_time)
|
||||
h5["artiq_version"].value, expid["repo_rev"],
|
||||
expid["file"], expid["class_name"],
|
||||
h5["rid"].value, start_time)
|
||||
return v
|
||||
except:
|
||||
logger.warning("unable to read metadata from %s",
|
||||
|
|
@ -175,45 +173,31 @@ class FilesDock(QtWidgets.QDockWidget):
|
|||
logger.debug("loading datasets from %s", info.filePath())
|
||||
with f:
|
||||
try:
|
||||
expid = pyon.decode(f["expid"][()]) if "expid" in f else dict()
|
||||
start_time = datetime.fromtimestamp(f["start_time"][()]) if "start_time" in f else "<none>"
|
||||
expid = pyon.decode(f["expid"].value)
|
||||
start_time = datetime.fromtimestamp(f["start_time"].value)
|
||||
v = {
|
||||
"artiq_version": f["artiq_version"].asstr()[()] if "artiq_version" in f else "<none>",
|
||||
"repo_rev": expid.get("repo_rev", "<none>"),
|
||||
"file": expid.get("file", "<none>"),
|
||||
"class_name": expid.get("class_name", "<none>"),
|
||||
"rid": f["rid"][()] if "rid" in f else "<none>",
|
||||
"artiq_version": f["artiq_version"].value,
|
||||
"repo_rev": expid["repo_rev"],
|
||||
"file": expid["file"],
|
||||
"class_name": expid["class_name"],
|
||||
"rid": f["rid"].value,
|
||||
"start_time": start_time,
|
||||
}
|
||||
self.metadata_changed.emit(v)
|
||||
except:
|
||||
logger.warning("unable to read metadata from %s",
|
||||
info.filePath(), exc_info=True)
|
||||
|
||||
rd = {}
|
||||
rd = dict()
|
||||
if "archive" in f:
|
||||
def visitor(k, v):
|
||||
if isinstance(v, h5py.Dataset):
|
||||
# v.attrs is a non-serializable h5py.AttributeManager, need to convert to dict
|
||||
# See https://docs.h5py.org/en/stable/high/attr.html#h5py.AttributeManager
|
||||
rd[k] = (True, v[()], dict(v.attrs))
|
||||
|
||||
f["archive"].visititems(visitor)
|
||||
|
||||
rd = {k: (True, v.value) for k, v in f["archive"].items()}
|
||||
if "datasets" in f:
|
||||
def visitor(k, v):
|
||||
if isinstance(v, h5py.Dataset):
|
||||
if k in rd:
|
||||
logger.warning("dataset '%s' is both in archive "
|
||||
"and outputs", k)
|
||||
# v.attrs is a non-serializable h5py.AttributeManager, need to convert to dict
|
||||
# See https://docs.h5py.org/en/stable/high/attr.html#h5py.AttributeManager
|
||||
rd[k] = (True, v[()], dict(v.attrs))
|
||||
|
||||
f["datasets"].visititems(visitor)
|
||||
|
||||
self.datasets.init(rd)
|
||||
|
||||
for k, v in f["datasets"].items():
|
||||
if k in rd:
|
||||
logger.warning("dataset '%s' is both in archive and "
|
||||
"outputs", k)
|
||||
rd[k] = (True, v.value)
|
||||
if rd:
|
||||
self.datasets.init(rd)
|
||||
self.dataset_changed.emit(info.filePath())
|
||||
|
||||
def list_activated(self, idx):
|
||||
|
|
|
|||
|
|
@ -1,9 +1,7 @@
|
|||
import os
|
||||
import subprocess
|
||||
|
||||
from migen import *
|
||||
from migen.build.platforms.sinara import kasli
|
||||
from misoc.interconnect.csr import *
|
||||
from misoc.cores import identifier
|
||||
from misoc.integration.builder import *
|
||||
|
||||
from artiq.gateware.amp import AMPSoC
|
||||
|
|
@ -19,58 +17,33 @@ def get_identifier_string(soc, suffix="", add_class_name=True):
|
|||
if suffix or add_class_name:
|
||||
r += ";"
|
||||
if add_class_name:
|
||||
r += getattr(soc, "class_name_override", soc.__class__.__name__.lower())
|
||||
r += soc.__class__.__name__.lower()
|
||||
r += suffix
|
||||
return r
|
||||
|
||||
|
||||
class ReprogrammableIdentifier(Module, AutoCSR):
|
||||
def __init__(self, ident):
|
||||
self.address = CSRStorage(8)
|
||||
self.data = CSRStatus(8)
|
||||
|
||||
contents = list(ident.encode())
|
||||
l = len(contents)
|
||||
if l > 255:
|
||||
raise ValueError("Identifier string must be 255 characters or less")
|
||||
contents.insert(0, l)
|
||||
|
||||
for i in range(8):
|
||||
self.specials += Instance("ROM256X1", name="identifier_str"+str(i),
|
||||
i_A0=self.address.storage[0], i_A1=self.address.storage[1],
|
||||
i_A2=self.address.storage[2], i_A3=self.address.storage[3],
|
||||
i_A4=self.address.storage[4], i_A5=self.address.storage[5],
|
||||
i_A6=self.address.storage[6], i_A7=self.address.storage[7],
|
||||
o_O=self.data.status[i],
|
||||
p_INIT=sum(1 << j if c & (1 << i) else 0 for j, c in enumerate(contents)))
|
||||
|
||||
|
||||
def add_identifier(soc, *args, gateware_identifier_str=None, **kwargs):
|
||||
def add_identifier(soc, *args, **kwargs):
|
||||
if hasattr(soc, "identifier"):
|
||||
raise ValueError
|
||||
identifier_str = get_identifier_string(soc, *args, **kwargs)
|
||||
soc.submodules.identifier = ReprogrammableIdentifier(gateware_identifier_str or identifier_str)
|
||||
soc.submodules.identifier = identifier.Identifier(identifier_str)
|
||||
soc.config["IDENTIFIER_STR"] = identifier_str
|
||||
|
||||
|
||||
|
||||
def build_artiq_soc(soc, argdict):
|
||||
firmware_dir = os.path.join(artiq_dir, "firmware")
|
||||
builder = Builder(soc, **argdict)
|
||||
builder.software_packages = []
|
||||
builder.add_software_package("bootloader", os.path.join(firmware_dir, "bootloader"))
|
||||
is_kasli_v1 = isinstance(soc.platform, kasli.Platform) and soc.platform.hw_rev in ("v1.0", "v1.1")
|
||||
kernel_cpu_type = "vexriscv" if is_kasli_v1 else "vexriscv-g"
|
||||
builder.add_software_package("libm", cpu_type=kernel_cpu_type)
|
||||
builder.add_software_package("libprintf", cpu_type=kernel_cpu_type)
|
||||
builder.add_software_package("libunwind", cpu_type=kernel_cpu_type)
|
||||
builder.add_software_package("ksupport", os.path.join(firmware_dir, "ksupport"), cpu_type=kernel_cpu_type)
|
||||
# Generate unwinder for soft float target (ARTIQ runtime)
|
||||
# If the kernel lacks FPU, then the runtime unwinder is already generated
|
||||
if not is_kasli_v1:
|
||||
if isinstance(soc, AMPSoC):
|
||||
builder.add_software_package("libm")
|
||||
builder.add_software_package("libprintf")
|
||||
builder.add_software_package("libunwind")
|
||||
if not soc.config["DRTIO_ROLE"] == "satellite":
|
||||
builder.add_software_package("ksupport", os.path.join(firmware_dir, "ksupport"))
|
||||
builder.add_software_package("runtime", os.path.join(firmware_dir, "runtime"))
|
||||
else:
|
||||
# Assume DRTIO satellite.
|
||||
builder.add_software_package("satman", os.path.join(firmware_dir, "satman"))
|
||||
try:
|
||||
builder.build()
|
||||
|
|
|
|||
|
|
@ -21,19 +21,13 @@ class scoped(object):
|
|||
set of variables resolved as globals
|
||||
"""
|
||||
|
||||
class remote(object):
|
||||
"""
|
||||
:ivar remote_fn: (bool) whether function is ran on a remote device,
|
||||
meaning arguments are received remotely and return is sent remotely
|
||||
"""
|
||||
|
||||
# Typed versions of untyped nodes
|
||||
class argT(ast.arg, commontyped):
|
||||
pass
|
||||
|
||||
class ClassDefT(ast.ClassDef):
|
||||
_types = ("constructor_type",)
|
||||
class FunctionDefT(ast.FunctionDef, scoped, remote):
|
||||
class FunctionDefT(ast.FunctionDef, scoped):
|
||||
_types = ("signature_type",)
|
||||
class QuotedFunctionDefT(FunctionDefT):
|
||||
"""
|
||||
|
|
@ -64,7 +58,7 @@ class BinOpT(ast.BinOp, commontyped):
|
|||
pass
|
||||
class BoolOpT(ast.BoolOp, commontyped):
|
||||
pass
|
||||
class CallT(ast.Call, commontyped, remote):
|
||||
class CallT(ast.Call, commontyped):
|
||||
"""
|
||||
:ivar iodelay: (:class:`iodelay.Expr`)
|
||||
:ivar arg_exprs: (dict of str to :class:`iodelay.Expr`)
|
||||
|
|
|
|||
|
|
@ -38,9 +38,6 @@ class TInt(types.TMono):
|
|||
def one():
|
||||
return 1
|
||||
|
||||
def TInt8():
|
||||
return TInt(types.TValue(8))
|
||||
|
||||
def TInt32():
|
||||
return TInt(types.TValue(32))
|
||||
|
||||
|
|
@ -85,27 +82,13 @@ class TList(types.TMono):
|
|||
super().__init__("list", {"elt": elt})
|
||||
|
||||
class TArray(types.TMono):
|
||||
def __init__(self, elt=None, num_dims=1):
|
||||
def __init__(self, elt=None):
|
||||
if elt is None:
|
||||
elt = types.TVar()
|
||||
if isinstance(num_dims, int):
|
||||
# Make TArray more convenient to instantiate from (ARTIQ) user code.
|
||||
num_dims = types.TValue(num_dims)
|
||||
# For now, enforce number of dimensions to be known, as we'd otherwise
|
||||
# need to implement custom unification logic for the type of `shape`.
|
||||
# Default to 1 to keep compatibility with old user code from before
|
||||
# multidimensional array support.
|
||||
assert isinstance(num_dims.value, int), "Number of dimensions must be resolved"
|
||||
|
||||
super().__init__("array", {"elt": elt, "num_dims": num_dims})
|
||||
self.attributes = OrderedDict([
|
||||
("buffer", types._TPointer(elt)),
|
||||
("shape", types.TTuple([TInt32()] * num_dims.value)),
|
||||
])
|
||||
super().__init__("array", {"elt": elt})
|
||||
|
||||
def _array_printer(typ, printer, depth, max_depth):
|
||||
return "numpy.array(elt={}, num_dims={})".format(
|
||||
printer.name(typ["elt"], depth, max_depth), typ["num_dims"].value)
|
||||
return "numpy.array(elt={})".format(printer.name(typ["elt"], depth, max_depth))
|
||||
types.TypePrinter.custom_printers["array"] = _array_printer
|
||||
|
||||
class TRange(types.TMono):
|
||||
|
|
@ -126,23 +109,18 @@ class TException(types.TMono):
|
|||
# * File, line and column where it was raised (str, int, int).
|
||||
# * Message, which can contain substitutions {0}, {1} and {2} (str).
|
||||
# * Three 64-bit integers, parameterizing the message (numpy.int64).
|
||||
# These attributes are prefixed with `#` so that users cannot access them,
|
||||
# and we don't have to do string allocation in the runtime.
|
||||
# #__name__ is now a string key in the host. TStr may not be an actual
|
||||
# CSlice in the runtime, they might be a CSlice with length = i32::MAX and
|
||||
# ptr = string key in the host.
|
||||
|
||||
# Keep this in sync with the function ARTIQIRGenerator.alloc_exn.
|
||||
attributes = OrderedDict([
|
||||
("#__name__", TInt32()),
|
||||
("#__file__", TStr()),
|
||||
("#__line__", TInt32()),
|
||||
("#__col__", TInt32()),
|
||||
("#__func__", TStr()),
|
||||
("#__message__", TStr()),
|
||||
("#__param0__", TInt64()),
|
||||
("#__param1__", TInt64()),
|
||||
("#__param2__", TInt64()),
|
||||
("__name__", TStr()),
|
||||
("__file__", TStr()),
|
||||
("__line__", TInt32()),
|
||||
("__col__", TInt32()),
|
||||
("__func__", TStr()),
|
||||
("__message__", TStr()),
|
||||
("__param0__", TInt64()),
|
||||
("__param1__", TInt64()),
|
||||
("__param2__", TInt64()),
|
||||
])
|
||||
|
||||
def __init__(self, name="Exception", id=0):
|
||||
|
|
@ -177,9 +155,7 @@ def fn_list():
|
|||
return types.TConstructor(TList())
|
||||
|
||||
def fn_array():
|
||||
# numpy.array() is actually a "magic" macro that is expanded in-place, but
|
||||
# just as for builtin functions, we do not want to quote it, etc.
|
||||
return types.TBuiltinFunction("array")
|
||||
return types.TConstructor(TArray())
|
||||
|
||||
def fn_Exception():
|
||||
return types.TExceptionConstructor(TException("Exception"))
|
||||
|
|
@ -205,9 +181,6 @@ def fn_len():
|
|||
def fn_round():
|
||||
return types.TBuiltinFunction("round")
|
||||
|
||||
def fn_abs():
|
||||
return types.TBuiltinFunction("abs")
|
||||
|
||||
def fn_min():
|
||||
return types.TBuiltinFunction("min")
|
||||
|
||||
|
|
@ -232,6 +205,9 @@ def obj_interleave():
|
|||
def obj_sequential():
|
||||
return types.TBuiltin("sequential")
|
||||
|
||||
def fn_watchdog():
|
||||
return types.TBuiltinFunction("watchdog")
|
||||
|
||||
def fn_delay():
|
||||
return types.TBuiltinFunction("delay")
|
||||
|
||||
|
|
@ -247,12 +223,6 @@ def fn_at_mu():
|
|||
def fn_rtio_log():
|
||||
return types.TBuiltinFunction("rtio_log")
|
||||
|
||||
def fn_subkernel_await():
|
||||
return types.TBuiltinFunction("subkernel_await")
|
||||
|
||||
def fn_subkernel_preload():
|
||||
return types.TBuiltinFunction("subkernel_preload")
|
||||
|
||||
# Accessors
|
||||
|
||||
def is_none(typ):
|
||||
|
|
@ -331,12 +301,9 @@ def is_iterable(typ):
|
|||
return is_listish(typ) or is_range(typ)
|
||||
|
||||
def get_iterable_elt(typ):
|
||||
# TODO: Arrays count as listish, but this returns the innermost element type for
|
||||
# n-dimensional arrays, rather than the n-1 dimensional result of iterating over
|
||||
# the first axis, which makes the name a bit misleading.
|
||||
if is_str(typ) or is_bytes(typ) or is_bytearray(typ):
|
||||
return TInt8()
|
||||
elif types._is_pointer(typ) or is_iterable(typ):
|
||||
return TInt(types.TValue(8))
|
||||
elif is_iterable(typ):
|
||||
return typ.find()["elt"].find()
|
||||
else:
|
||||
assert False
|
||||
|
|
@ -350,6 +317,6 @@ def is_allocated(typ):
|
|||
return not (is_none(typ) or is_bool(typ) or is_int(typ) or
|
||||
is_float(typ) or is_range(typ) or
|
||||
types._is_pointer(typ) or types.is_function(typ) or
|
||||
types.is_external_function(typ) or types.is_rpc(typ) or
|
||||
types.is_subkernel(typ) or types.is_method(typ) or
|
||||
types.is_tuple(typ) or types.is_value(typ))
|
||||
types.is_c_function(typ) or types.is_rpc(typ) or
|
||||
types.is_method(typ) or types.is_tuple(typ) or
|
||||
types.is_value(typ))
|
||||
|
|
|
|||
|
|
@ -5,8 +5,7 @@ the references to the host objects and translates the functions
|
|||
annotated as ``@kernel`` when they are referenced.
|
||||
"""
|
||||
|
||||
import typing
|
||||
import os, re, linecache, inspect, textwrap, types as pytypes, numpy
|
||||
import sys, os, re, linecache, inspect, textwrap, types as pytypes, numpy
|
||||
from collections import OrderedDict, defaultdict
|
||||
|
||||
from pythonparser import ast, algorithm, source, diagnostic, parse_buffer
|
||||
|
|
@ -15,17 +14,10 @@ from pythonparser import lexer as source_lexer, parser as source_parser
|
|||
from Levenshtein import ratio as similarity, jaro_winkler
|
||||
|
||||
from ..language import core as language_core
|
||||
from . import types, builtins, asttyped, math_fns, prelude
|
||||
from . import types, builtins, asttyped, prelude
|
||||
from .transforms import ASTTypedRewriter, Inferencer, IntMonomorphizer, TypedtreePrinter
|
||||
from .transforms.asttyped_rewriter import LocalExtractor
|
||||
|
||||
try:
|
||||
# From numpy=1.25.0 dispatching for `__array_function__` is done via
|
||||
# a C wrapper: https://github.com/numpy/numpy/pull/23020
|
||||
from numpy.core._multiarray_umath import _ArrayFunctionDispatcher
|
||||
except ImportError:
|
||||
_ArrayFunctionDispatcher = None
|
||||
|
||||
|
||||
class SpecializedFunction:
|
||||
def __init__(self, instance_type, host_function):
|
||||
|
|
@ -53,48 +45,8 @@ class EmbeddingMap:
|
|||
self.object_forward_map = {}
|
||||
self.object_reverse_map = {}
|
||||
self.module_map = {}
|
||||
|
||||
# type_map connects the host Python `type` to the pair of associated
|
||||
# `(TInstance, TConstructor)`s. The `used_…_names` sets cache the
|
||||
# respective `.name`s for O(1) collision avoidance.
|
||||
self.type_map = {}
|
||||
self.used_instance_type_names = set()
|
||||
self.used_constructor_type_names = set()
|
||||
|
||||
self.function_map = {}
|
||||
self.str_forward_map = {}
|
||||
self.str_reverse_map = {}
|
||||
|
||||
self.preallocate_runtime_exception_names(["RuntimeError",
|
||||
"RTIOUnderflow",
|
||||
"RTIOOverflow",
|
||||
"RTIODestinationUnreachable",
|
||||
"DMAError",
|
||||
"I2CError",
|
||||
"CacheError",
|
||||
"SPIError",
|
||||
"0:ZeroDivisionError",
|
||||
"0:IndexError",
|
||||
"UnwrapNoneError",
|
||||
"SubkernelError"])
|
||||
|
||||
def preallocate_runtime_exception_names(self, names):
|
||||
for i, name in enumerate(names):
|
||||
if ":" not in name:
|
||||
name = "0:artiq.coredevice.exceptions." + name
|
||||
exn_id = self.store_str(name)
|
||||
assert exn_id == i
|
||||
|
||||
def store_str(self, s):
|
||||
if s in self.str_forward_map:
|
||||
return self.str_forward_map[s]
|
||||
str_id = len(self.str_forward_map)
|
||||
self.str_forward_map[s] = str_id
|
||||
self.str_reverse_map[str_id] = s
|
||||
return str_id
|
||||
|
||||
def retrieve_str(self, str_id):
|
||||
return self.str_reverse_map[str_id]
|
||||
|
||||
# Modules
|
||||
def store_module(self, module, module_type):
|
||||
|
|
@ -108,6 +60,16 @@ class EmbeddingMap:
|
|||
|
||||
# Types
|
||||
def store_type(self, host_type, instance_type, constructor_type):
|
||||
self._rename_type(instance_type)
|
||||
self.type_map[host_type] = (instance_type, constructor_type)
|
||||
|
||||
def retrieve_type(self, host_type):
|
||||
return self.type_map[host_type]
|
||||
|
||||
def has_type(self, host_type):
|
||||
return host_type in self.type_map
|
||||
|
||||
def _rename_type(self, new_instance_type):
|
||||
# Generally, user-defined types that have exact same name (which is to say, classes
|
||||
# defined inside functions) do not pose a problem to the compiler. The two places which
|
||||
# cannot handle this are:
|
||||
|
|
@ -116,29 +78,12 @@ class EmbeddingMap:
|
|||
# Since handling #2 requires renaming on ARTIQ side anyway, it's more straightforward
|
||||
# to do it once when embedding (since non-embedded code cannot define classes in
|
||||
# functions). Also, easier to debug.
|
||||
suffix = 0
|
||||
new_instance_name = instance_type.name
|
||||
new_constructor_name = constructor_type.name
|
||||
while True:
|
||||
if (new_instance_name not in self.used_instance_type_names
|
||||
and new_constructor_name not in self.used_constructor_type_names):
|
||||
break
|
||||
suffix += 1
|
||||
new_instance_name = f"{instance_type.name}.{suffix}"
|
||||
new_constructor_name = f"{constructor_type.name}.{suffix}"
|
||||
|
||||
self.used_instance_type_names.add(new_instance_name)
|
||||
instance_type.name = new_instance_name
|
||||
self.used_constructor_type_names.add(new_constructor_name)
|
||||
constructor_type.name = new_constructor_name
|
||||
|
||||
self.type_map[host_type] = (instance_type, constructor_type)
|
||||
|
||||
def retrieve_type(self, host_type):
|
||||
return self.type_map[host_type]
|
||||
|
||||
def has_type(self, host_type):
|
||||
return host_type in self.type_map
|
||||
n = 0
|
||||
for host_type in self.type_map:
|
||||
instance_type, constructor_type = self.type_map[host_type]
|
||||
if instance_type.name == new_instance_type.name:
|
||||
n += 1
|
||||
new_instance_type.name = "{}.{}".format(new_instance_type.name, n)
|
||||
|
||||
def attribute_count(self):
|
||||
count = 0
|
||||
|
|
@ -185,22 +130,7 @@ class EmbeddingMap:
|
|||
obj_typ, _ = self.type_map[type(obj_ref)]
|
||||
yield obj_id, obj_ref, obj_typ
|
||||
|
||||
def subkernels(self):
|
||||
subkernels = {}
|
||||
for k, v in self.object_forward_map.items():
|
||||
if hasattr(v, "artiq_embedded"):
|
||||
if v.artiq_embedded.destination is not None:
|
||||
subkernels[k] = v
|
||||
return subkernels
|
||||
|
||||
def has_rpc(self):
|
||||
return any(filter(
|
||||
lambda x: (inspect.isfunction(x) or inspect.ismethod(x)) and \
|
||||
(not hasattr(x, "artiq_embedded") or x.artiq_embedded.destination is None),
|
||||
self.object_forward_map.values()
|
||||
))
|
||||
|
||||
def has_rpc_or_subkernel(self):
|
||||
return any(filter(lambda x: inspect.isfunction(x) or inspect.ismethod(x),
|
||||
self.object_forward_map.values()))
|
||||
|
||||
|
|
@ -208,7 +138,6 @@ class EmbeddingMap:
|
|||
class ASTSynthesizer:
|
||||
def __init__(self, embedding_map, value_map, quote_function=None, expanded_from=None):
|
||||
self.source = ""
|
||||
self.source_last_new_line = 0
|
||||
self.source_buffer = source.Buffer(self.source, "<synthesized>")
|
||||
self.embedding_map = embedding_map
|
||||
self.value_map = value_map
|
||||
|
|
@ -227,90 +156,16 @@ class ASTSynthesizer:
|
|||
return source.Range(self.source_buffer, range_from, range_to,
|
||||
expanded_from=self.expanded_from)
|
||||
|
||||
def _add_iterable(self, fragment):
|
||||
# Since DILocation points on the beginning of the piece of source
|
||||
# we don't care if the fragment's end will overflow LLVM's limit.
|
||||
if len(self.source) - self.source_last_new_line >= 2**16:
|
||||
fragment = "\\\n" + fragment
|
||||
self.source_last_new_line = len(self.source) + 2
|
||||
return self._add(fragment)
|
||||
|
||||
def fast_quote_list(self, value):
|
||||
elts = [None] * len(value)
|
||||
is_T = False
|
||||
if len(value) > 0:
|
||||
v = value[0]
|
||||
is_T = True
|
||||
if isinstance(v, int):
|
||||
T = int
|
||||
elif isinstance(v, float):
|
||||
T = float
|
||||
elif isinstance(v, numpy.int32):
|
||||
T = numpy.int32
|
||||
elif isinstance(v, numpy.int64):
|
||||
T = numpy.int64
|
||||
else:
|
||||
is_T = False
|
||||
if is_T:
|
||||
for v in value:
|
||||
if not isinstance(v, T):
|
||||
is_T = False
|
||||
break
|
||||
if is_T:
|
||||
is_int = T != float
|
||||
if T == int:
|
||||
typ = builtins.TInt()
|
||||
elif T == float:
|
||||
typ = builtins.TFloat()
|
||||
elif T == numpy.int32:
|
||||
typ = builtins.TInt32()
|
||||
elif T == numpy.int64:
|
||||
typ = builtins.TInt64()
|
||||
else:
|
||||
assert False
|
||||
text = [repr(elt) for elt in value]
|
||||
start = len(self.source)
|
||||
self.source += ", ".join(text)
|
||||
if is_int:
|
||||
for i, (v, t) in enumerate(zip(value, text)):
|
||||
l = len(t)
|
||||
elts[i] = asttyped.NumT(
|
||||
n=int(v), ctx=None, type=typ,
|
||||
loc=source.Range(
|
||||
self.source_buffer, start, start + l,
|
||||
expanded_from=self.expanded_from))
|
||||
start += l + 2
|
||||
else:
|
||||
for i, (v, t) in enumerate(zip(value, text)):
|
||||
l = len(t)
|
||||
elts[i] = asttyped.NumT(
|
||||
n=v, ctx=None, type=typ,
|
||||
loc=source.Range(
|
||||
self.source_buffer, start, start + l,
|
||||
expanded_from=self.expanded_from))
|
||||
start += l + 2
|
||||
else:
|
||||
for index, elt in enumerate(value):
|
||||
elts[index] = self.quote(elt)
|
||||
if index < len(value) - 1:
|
||||
self._add_iterable(", ")
|
||||
return elts
|
||||
|
||||
def quote(self, value):
|
||||
"""Construct an AST fragment equal to `value`."""
|
||||
if value is None:
|
||||
typ = builtins.TNone()
|
||||
return asttyped.NameConstantT(value=value, type=typ,
|
||||
loc=self._add(repr(value)))
|
||||
elif isinstance(value, (bool, numpy.bool_)):
|
||||
elif value is True or value is False:
|
||||
typ = builtins.TBool()
|
||||
coerced = bool(value)
|
||||
return asttyped.NameConstantT(value=coerced, type=typ,
|
||||
loc=self._add(repr(coerced)))
|
||||
elif value is float:
|
||||
typ = builtins.fn_float()
|
||||
return asttyped.NameConstantT(value=None, type=typ,
|
||||
loc=self._add("float"))
|
||||
return asttyped.NameConstantT(value=value, type=typ,
|
||||
loc=self._add(repr(value)))
|
||||
elif value is numpy.int32:
|
||||
typ = builtins.fn_int32()
|
||||
return asttyped.NameConstantT(value=None, type=typ,
|
||||
|
|
@ -344,40 +199,43 @@ class ASTSynthesizer:
|
|||
loc=self._add(repr(value)))
|
||||
elif isinstance(value, str):
|
||||
return asttyped.StrT(s=value, ctx=None, type=builtins.TStr(),
|
||||
loc=self._add_iterable(repr(value)))
|
||||
loc=self._add(repr(value)))
|
||||
elif isinstance(value, bytes):
|
||||
return asttyped.StrT(s=value, ctx=None, type=builtins.TBytes(),
|
||||
loc=self._add_iterable(repr(value)))
|
||||
loc=self._add(repr(value)))
|
||||
elif isinstance(value, bytearray):
|
||||
quote_loc = self._add_iterable('`')
|
||||
repr_loc = self._add_iterable(repr(value))
|
||||
unquote_loc = self._add_iterable('`')
|
||||
quote_loc = self._add('`')
|
||||
repr_loc = self._add(repr(value))
|
||||
unquote_loc = self._add('`')
|
||||
loc = quote_loc.join(unquote_loc)
|
||||
|
||||
return asttyped.QuoteT(value=value, type=builtins.TByteArray(), loc=loc)
|
||||
elif isinstance(value, list):
|
||||
begin_loc = self._add_iterable("[")
|
||||
elts = self.fast_quote_list(value)
|
||||
end_loc = self._add_iterable("]")
|
||||
begin_loc = self._add("[")
|
||||
elts = []
|
||||
for index, elt in enumerate(value):
|
||||
elts.append(self.quote(elt))
|
||||
if index < len(value) - 1:
|
||||
self._add(", ")
|
||||
end_loc = self._add("]")
|
||||
return asttyped.ListT(elts=elts, ctx=None, type=builtins.TList(),
|
||||
begin_loc=begin_loc, end_loc=end_loc,
|
||||
loc=begin_loc.join(end_loc))
|
||||
elif isinstance(value, tuple):
|
||||
begin_loc = self._add_iterable("(")
|
||||
elts = self.fast_quote_list(value)
|
||||
end_loc = self._add_iterable(")")
|
||||
return asttyped.TupleT(elts=elts, ctx=None,
|
||||
type=types.TTuple([e.type for e in elts]),
|
||||
begin_loc=begin_loc, end_loc=end_loc,
|
||||
loc=begin_loc.join(end_loc))
|
||||
elif isinstance(value, numpy.ndarray):
|
||||
return self.call(numpy.array, [list(value)], {})
|
||||
begin_loc = self._add("numpy.array([")
|
||||
elts = []
|
||||
for index, elt in enumerate(value):
|
||||
elts.append(self.quote(elt))
|
||||
if index < len(value) - 1:
|
||||
self._add(", ")
|
||||
end_loc = self._add("])")
|
||||
|
||||
return asttyped.ListT(elts=elts, ctx=None, type=builtins.TArray(),
|
||||
begin_loc=begin_loc, end_loc=end_loc,
|
||||
loc=begin_loc.join(end_loc))
|
||||
elif inspect.isfunction(value) or inspect.ismethod(value) or \
|
||||
isinstance(value, pytypes.BuiltinFunctionType) or \
|
||||
isinstance(value, SpecializedFunction) or \
|
||||
isinstance(value, numpy.ufunc) or \
|
||||
(isinstance(value, _ArrayFunctionDispatcher) if
|
||||
_ArrayFunctionDispatcher is not None else False):
|
||||
isinstance(value, SpecializedFunction):
|
||||
if inspect.ismethod(value):
|
||||
quoted_self = self.quote(value.__self__)
|
||||
function_type = self.quote_function(value.__func__, self.expanded_from)
|
||||
|
|
@ -486,7 +344,7 @@ class ASTSynthesizer:
|
|||
return asttyped.QuoteT(value=value, type=instance_type,
|
||||
loc=loc)
|
||||
|
||||
def call(self, callee, args, kwargs, callback=None, remote_fn=False):
|
||||
def call(self, callee, args, kwargs, callback=None):
|
||||
"""
|
||||
Construct an AST fragment calling a function specified by
|
||||
an AST node `function_node`, with given arguments.
|
||||
|
|
@ -530,7 +388,7 @@ class ASTSynthesizer:
|
|||
starargs=None, kwargs=None,
|
||||
type=types.TVar(), iodelay=None, arg_exprs={},
|
||||
begin_loc=begin_loc, end_loc=end_loc, star_loc=None, dstar_loc=None,
|
||||
loc=callee_node.loc.join(end_loc), remote_fn=remote_fn)
|
||||
loc=callee_node.loc.join(end_loc))
|
||||
|
||||
if callback is not None:
|
||||
node = asttyped.CallT(
|
||||
|
|
@ -565,7 +423,7 @@ class StitchingASTTypedRewriter(ASTTypedRewriter):
|
|||
arg=node.arg, annotation=None,
|
||||
arg_loc=node.arg_loc, colon_loc=node.colon_loc, loc=node.loc)
|
||||
|
||||
def visit_quoted_function(self, node, function, remote_fn):
|
||||
def visit_quoted_function(self, node, function):
|
||||
extractor = LocalExtractor(env_stack=self.env_stack, engine=self.engine)
|
||||
extractor.visit(node)
|
||||
|
||||
|
|
@ -582,11 +440,11 @@ class StitchingASTTypedRewriter(ASTTypedRewriter):
|
|||
node = asttyped.QuotedFunctionDefT(
|
||||
typing_env=extractor.typing_env, globals_in_scope=extractor.global_,
|
||||
signature_type=types.TVar(), return_type=types.TVar(),
|
||||
name=node.name, args=node.args, returns=None,
|
||||
name=node.name, args=node.args, returns=node.returns,
|
||||
body=node.body, decorator_list=node.decorator_list,
|
||||
keyword_loc=node.keyword_loc, name_loc=node.name_loc,
|
||||
arrow_loc=node.arrow_loc, colon_loc=node.colon_loc, at_locs=node.at_locs,
|
||||
loc=node.loc, remote_fn=remote_fn)
|
||||
loc=node.loc)
|
||||
|
||||
try:
|
||||
self.env_stack.append(node.typing_env)
|
||||
|
|
@ -658,7 +516,7 @@ class StitchingInferencer(Inferencer):
|
|||
self.engine.process(diag)
|
||||
return
|
||||
|
||||
# Figure out the ARTIQ type of the value of the attribute.
|
||||
# Figure out what ARTIQ type does the value of the attribute have.
|
||||
# We do this by quoting it, as if to serialize. This has some
|
||||
# overhead (i.e. synthesizing a source buffer), but has the advantage
|
||||
# of having the host-to-ARTIQ mapping code in only one place and
|
||||
|
|
@ -794,7 +652,7 @@ class TypedtreeHasher(algorithm.Visitor):
|
|||
return hash(tuple(freeze(getattr(node, field_name)) for field_name in fields))
|
||||
|
||||
class Stitcher:
|
||||
def __init__(self, core, dmgr, engine=None, print_as_rpc=True, destination=0, subkernel_arg_types=[]):
|
||||
def __init__(self, core, dmgr, engine=None, print_as_rpc=True):
|
||||
self.core = core
|
||||
self.dmgr = dmgr
|
||||
if engine is None:
|
||||
|
|
@ -818,21 +676,12 @@ class Stitcher:
|
|||
|
||||
self.embedding_map = EmbeddingMap()
|
||||
self.value_map = defaultdict(lambda: [])
|
||||
self.definitely_changed = False
|
||||
|
||||
self.destination = destination
|
||||
self.first_call = True
|
||||
# for non-annotated subkernels:
|
||||
# main kernel inferencer output with types of arguments
|
||||
self.subkernel_arg_types = subkernel_arg_types
|
||||
|
||||
def stitch_call(self, function, args, kwargs, callback=None):
|
||||
# We synthesize source code for the initial call so that
|
||||
# diagnostics would have something meaningful to display to the user.
|
||||
synthesizer = self._synthesizer(self._function_loc(function.artiq_embedded.function))
|
||||
# first call of a subkernel will get its arguments from remote (DRTIO)
|
||||
remote_fn = self.destination != 0
|
||||
call_node = synthesizer.call(function, args, kwargs, callback, remote_fn=remote_fn)
|
||||
call_node = synthesizer.call(function, args, kwargs, callback)
|
||||
synthesizer.finalize()
|
||||
self.typedtree.append(call_node)
|
||||
|
||||
|
|
@ -847,19 +696,13 @@ class Stitcher:
|
|||
old_attr_count = None
|
||||
while True:
|
||||
inferencer.visit(self.typedtree)
|
||||
if self.definitely_changed:
|
||||
changed = True
|
||||
self.definitely_changed = False
|
||||
else:
|
||||
typedtree_hash = typedtree_hasher.visit(self.typedtree)
|
||||
attr_count = self.embedding_map.attribute_count()
|
||||
changed = old_attr_count != attr_count or \
|
||||
old_typedtree_hash != typedtree_hash
|
||||
old_typedtree_hash = typedtree_hash
|
||||
old_attr_count = attr_count
|
||||
typedtree_hash = typedtree_hasher.visit(self.typedtree)
|
||||
attr_count = self.embedding_map.attribute_count()
|
||||
|
||||
if not changed:
|
||||
if old_typedtree_hash == typedtree_hash and old_attr_count == attr_count:
|
||||
break
|
||||
old_typedtree_hash = typedtree_hash
|
||||
old_attr_count = attr_count
|
||||
|
||||
# After we've discovered every referenced attribute, check if any kernel_invariant
|
||||
# specifications refers to ones we didn't encounter.
|
||||
|
|
@ -911,9 +754,6 @@ class Stitcher:
|
|||
if hasattr(function, 'artiq_embedded') and function.artiq_embedded.function:
|
||||
function = function.artiq_embedded.function
|
||||
|
||||
if isinstance(function, str):
|
||||
return source.Range(source.Buffer(function, "<string>"), 0, 0)
|
||||
|
||||
filename = function.__code__.co_filename
|
||||
line = function.__code__.co_firstlineno
|
||||
name = function.__code__.co_name
|
||||
|
|
@ -944,10 +784,6 @@ class Stitcher:
|
|||
return [diagnostic.Diagnostic("note",
|
||||
"in kernel function here", {},
|
||||
call_loc)]
|
||||
elif fn_kind == 'subkernel':
|
||||
return [diagnostic.Diagnostic("note",
|
||||
"in subkernel call here", {},
|
||||
call_loc)]
|
||||
else:
|
||||
assert False
|
||||
else:
|
||||
|
|
@ -967,7 +803,7 @@ class Stitcher:
|
|||
self._function_loc(function),
|
||||
notes=self._call_site_note(loc, fn_kind))
|
||||
self.engine.process(diag)
|
||||
elif fn_kind == 'rpc' or fn_kind == 'subkernel' and param.default is not inspect.Parameter.empty:
|
||||
elif fn_kind == 'rpc' and param.default is not inspect.Parameter.empty:
|
||||
notes = []
|
||||
notes.append(diagnostic.Diagnostic("note",
|
||||
"expanded from here while trying to infer a type for an"
|
||||
|
|
@ -986,21 +822,11 @@ class Stitcher:
|
|||
Inferencer(engine=self.engine).visit(ast)
|
||||
IntMonomorphizer(engine=self.engine).visit(ast)
|
||||
return ast.type
|
||||
elif fn_kind == 'kernel' and self.first_call and self.destination != 0:
|
||||
# subkernels do not have access to the main kernel code to infer
|
||||
# arg types - so these are cached and passed onto subkernel
|
||||
# compilation, to avoid having to annotate them fully
|
||||
for name, typ in self.subkernel_arg_types:
|
||||
if param.name == name:
|
||||
return typ
|
||||
|
||||
# Let the rest of the program decide.
|
||||
return types.TVar()
|
||||
|
||||
def _quote_embedded_function(self, function, flags, remote_fn=False):
|
||||
# we are now parsing new functions... definitely changed the type
|
||||
self.definitely_changed = True
|
||||
else:
|
||||
# Let the rest of the program decide.
|
||||
return types.TVar()
|
||||
|
||||
def _quote_embedded_function(self, function, flags):
|
||||
if isinstance(function, SpecializedFunction):
|
||||
host_function = function.host_function
|
||||
else:
|
||||
|
|
@ -1011,20 +837,10 @@ class Stitcher:
|
|||
|
||||
# Extract function source.
|
||||
embedded_function = host_function.artiq_embedded.function
|
||||
if isinstance(embedded_function, str):
|
||||
# This is a function to be eval'd from the given source code in string form.
|
||||
# Mangle the host function's id() into the fully qualified name to make sure
|
||||
# there are no collisions.
|
||||
source_code = embedded_function
|
||||
embedded_function = host_function
|
||||
filename = "<string>"
|
||||
module_name = "__eval_{}".format(id(host_function))
|
||||
first_line = 1
|
||||
else:
|
||||
source_code = inspect.getsource(embedded_function)
|
||||
filename = embedded_function.__code__.co_filename
|
||||
module_name = embedded_function.__globals__['__name__']
|
||||
first_line = embedded_function.__code__.co_firstlineno
|
||||
source_code = inspect.getsource(embedded_function)
|
||||
filename = embedded_function.__code__.co_filename
|
||||
module_name = embedded_function.__globals__['__name__']
|
||||
first_line = embedded_function.__code__.co_firstlineno
|
||||
|
||||
# Extract function annotation.
|
||||
signature = inspect.signature(embedded_function)
|
||||
|
|
@ -1067,11 +883,13 @@ class Stitcher:
|
|||
|
||||
# Parse.
|
||||
source_buffer = source.Buffer(source_code, filename, first_line)
|
||||
lexer = source_lexer.Lexer(source_buffer, version=(3, 6), diagnostic_engine=self.engine)
|
||||
lexer = source_lexer.Lexer(source_buffer, version=sys.version_info[0:2],
|
||||
diagnostic_engine=self.engine)
|
||||
lexer.indent = [(initial_indent,
|
||||
source.Range(source_buffer, 0, len(initial_whitespace)),
|
||||
initial_whitespace)]
|
||||
parser = source_parser.Parser(lexer, version=(3, 6), diagnostic_engine=self.engine)
|
||||
parser = source_parser.Parser(lexer, version=sys.version_info[0:2],
|
||||
diagnostic_engine=self.engine)
|
||||
function_node = parser.file_input().body[0]
|
||||
|
||||
# Mangle the name, since we put everything into a single module.
|
||||
|
|
@ -1096,7 +914,7 @@ class Stitcher:
|
|||
engine=self.engine, prelude=self.prelude,
|
||||
globals=self.globals, host_environment=host_environment,
|
||||
quote=self._quote)
|
||||
function_node = asttyped_rewriter.visit_quoted_function(function_node, embedded_function, remote_fn)
|
||||
function_node = asttyped_rewriter.visit_quoted_function(function_node, embedded_function)
|
||||
function_node.flags = flags
|
||||
|
||||
# Add it into our typedtree so that it gets inferenced and codegen'd.
|
||||
|
|
@ -1108,108 +926,23 @@ class Stitcher:
|
|||
return function_node
|
||||
|
||||
def _extract_annot(self, function, annot, kind, call_loc, fn_kind):
|
||||
if isinstance(function, SpecializedFunction):
|
||||
host_function = function.host_function
|
||||
if not isinstance(annot, types.Type):
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
"type annotation for {kind}, '{annot}', is not an ARTIQ type",
|
||||
{"kind": kind, "annot": repr(annot)},
|
||||
self._function_loc(function),
|
||||
notes=self._call_site_note(call_loc, fn_kind))
|
||||
self.engine.process(diag)
|
||||
|
||||
return types.TVar()
|
||||
else:
|
||||
host_function = function
|
||||
|
||||
if hasattr(host_function, 'artiq_embedded'):
|
||||
embedded_function = host_function.artiq_embedded.function
|
||||
else:
|
||||
embedded_function = host_function
|
||||
|
||||
if isinstance(embedded_function, str):
|
||||
embedded_function = host_function
|
||||
|
||||
return self._to_artiq_type(
|
||||
annot,
|
||||
function=function,
|
||||
kind=kind,
|
||||
eval_in_scope=lambda x: eval(x, embedded_function.__globals__),
|
||||
call_loc=call_loc,
|
||||
fn_kind=fn_kind)
|
||||
|
||||
def _to_artiq_type(
|
||||
self, annot, *, function, kind: str, eval_in_scope, call_loc: str, fn_kind: str
|
||||
) -> types.Type:
|
||||
if isinstance(annot, str):
|
||||
try:
|
||||
annot = eval_in_scope(annot)
|
||||
except Exception:
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error",
|
||||
"type annotation for {kind}, {annot}, cannot be evaluated",
|
||||
{"kind": kind, "annot": repr(annot)},
|
||||
self._function_loc(function),
|
||||
notes=self._call_site_note(call_loc, fn_kind))
|
||||
self.engine.process(diag)
|
||||
|
||||
if isinstance(annot, types.Type):
|
||||
return annot
|
||||
|
||||
# Convert built-in Python types to ARTIQ ones.
|
||||
if annot is None:
|
||||
return builtins.TNone()
|
||||
elif annot is numpy.int64:
|
||||
return builtins.TInt64()
|
||||
elif annot is numpy.int32:
|
||||
return builtins.TInt32()
|
||||
elif annot is float:
|
||||
return builtins.TFloat()
|
||||
elif annot is bool:
|
||||
return builtins.TBool()
|
||||
elif annot is str:
|
||||
return builtins.TStr()
|
||||
elif annot is bytes:
|
||||
return builtins.TBytes()
|
||||
elif annot is bytearray:
|
||||
return builtins.TByteArray()
|
||||
|
||||
# Convert generic Python types to ARTIQ ones.
|
||||
generic_ty = typing.get_origin(annot)
|
||||
if generic_ty is not None:
|
||||
type_args = typing.get_args(annot)
|
||||
artiq_args = [
|
||||
self._to_artiq_type(
|
||||
x,
|
||||
function=function,
|
||||
kind=kind,
|
||||
eval_in_scope=eval_in_scope,
|
||||
call_loc=call_loc,
|
||||
fn_kind=fn_kind)
|
||||
for x in type_args
|
||||
]
|
||||
|
||||
if generic_ty is list and len(artiq_args) == 1:
|
||||
return builtins.TList(artiq_args[0])
|
||||
elif generic_ty is tuple:
|
||||
return types.TTuple(artiq_args)
|
||||
|
||||
# Otherwise report an unknown type and just use a fresh tyvar.
|
||||
|
||||
if annot is int:
|
||||
message = (
|
||||
"type annotation for {kind}, 'int' cannot be used as an ARTIQ type. "
|
||||
"Use numpy's int32 or int64 instead."
|
||||
)
|
||||
ty = builtins.TInt()
|
||||
else:
|
||||
message = "type annotation for {kind}, '{annot}', is not an ARTIQ type"
|
||||
ty = types.TVar()
|
||||
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
message,
|
||||
{"kind": kind, "annot": repr(annot)},
|
||||
self._function_loc(function),
|
||||
notes=self._call_site_note(call_loc, fn_kind))
|
||||
self.engine.process(diag)
|
||||
|
||||
return ty
|
||||
|
||||
def _quote_syscall(self, function, loc):
|
||||
signature = inspect.signature(function)
|
||||
|
||||
arg_types = OrderedDict()
|
||||
optarg_types = OrderedDict()
|
||||
for param in signature.parameters.values():
|
||||
if param.kind != inspect.Parameter.POSITIONAL_OR_KEYWORD:
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
|
|
@ -1241,43 +974,9 @@ class Stitcher:
|
|||
self.engine.process(diag)
|
||||
ret_type = types.TVar()
|
||||
|
||||
function_type = types.TExternalFunction(arg_types, ret_type,
|
||||
name=function.artiq_embedded.syscall,
|
||||
flags=function.artiq_embedded.flags)
|
||||
self.functions[function] = function_type
|
||||
return function_type
|
||||
|
||||
def _quote_subkernel(self, function, loc):
|
||||
if isinstance(function, SpecializedFunction):
|
||||
host_function = function.host_function
|
||||
else:
|
||||
host_function = function
|
||||
ret_type = builtins.TNone()
|
||||
signature = inspect.signature(host_function)
|
||||
|
||||
if signature.return_annotation is not inspect.Signature.empty:
|
||||
ret_type = self._extract_annot(host_function, signature.return_annotation,
|
||||
"return type", loc, fn_kind='subkernel')
|
||||
arg_types = OrderedDict()
|
||||
optarg_types = OrderedDict()
|
||||
for param in signature.parameters.values():
|
||||
if param.kind != inspect.Parameter.POSITIONAL_OR_KEYWORD:
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
"subkernels must only use positional arguments; '{argument}' isn't",
|
||||
{"argument": param.name},
|
||||
self._function_loc(function),
|
||||
notes=self._call_site_note(loc, fn_kind='subkernel'))
|
||||
self.engine.process(diag)
|
||||
|
||||
arg_type = self._type_of_param(function, loc, param, fn_kind='subkernel')
|
||||
if param.default is inspect.Parameter.empty:
|
||||
arg_types[param.name] = arg_type
|
||||
else:
|
||||
optarg_types[param.name] = arg_type
|
||||
|
||||
function_type = types.TSubkernel(arg_types, optarg_types, ret_type,
|
||||
sid=self.embedding_map.store_object(host_function),
|
||||
destination=host_function.artiq_embedded.destination)
|
||||
function_type = types.TCFunction(arg_types, ret_type,
|
||||
name=function.artiq_embedded.syscall,
|
||||
flags=function.artiq_embedded.flags)
|
||||
self.functions[function] = function_type
|
||||
return function_type
|
||||
|
||||
|
|
@ -1320,7 +1019,7 @@ class Stitcher:
|
|||
|
||||
function_type = types.TRPC(ret_type,
|
||||
service=self.embedding_map.store_object(host_function),
|
||||
is_async=is_async)
|
||||
async=is_async)
|
||||
self.functions[function] = function_type
|
||||
return function_type
|
||||
|
||||
|
|
@ -1331,27 +1030,13 @@ class Stitcher:
|
|||
host_function = function
|
||||
|
||||
if function in self.functions:
|
||||
return self.functions[function]
|
||||
|
||||
math_type = math_fns.match(function)
|
||||
if math_type is not None:
|
||||
self.functions[function] = math_type
|
||||
pass
|
||||
elif not hasattr(host_function, "artiq_embedded") or \
|
||||
(host_function.artiq_embedded.core_name is None and
|
||||
host_function.artiq_embedded.portable is False and
|
||||
host_function.artiq_embedded.syscall is None and
|
||||
host_function.artiq_embedded.destination is None and
|
||||
host_function.artiq_embedded.forbidden is False):
|
||||
self._quote_rpc(function, loc)
|
||||
elif host_function.artiq_embedded.destination is not None and \
|
||||
host_function.artiq_embedded.destination != self.destination:
|
||||
# treat subkernels as kernels if running on the same device
|
||||
if not 0 < host_function.artiq_embedded.destination <= 255:
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
"subkernel destination must be between 1 and 255 (inclusive)", {},
|
||||
self._function_loc(host_function))
|
||||
self.engine.process(diag)
|
||||
self._quote_subkernel(function, loc)
|
||||
elif host_function.artiq_embedded.function is not None:
|
||||
if host_function.__name__ == "<lambda>":
|
||||
note = diagnostic.Diagnostic("note",
|
||||
|
|
@ -1375,13 +1060,8 @@ class Stitcher:
|
|||
notes=[note])
|
||||
self.engine.process(diag)
|
||||
|
||||
destination = host_function.artiq_embedded.destination
|
||||
# remote_fn only for first call in subkernels
|
||||
remote_fn = destination is not None and self.first_call
|
||||
self._quote_embedded_function(function,
|
||||
flags=host_function.artiq_embedded.flags,
|
||||
remote_fn=remote_fn)
|
||||
self.first_call = False
|
||||
flags=host_function.artiq_embedded.flags)
|
||||
elif host_function.artiq_embedded.syscall is not None:
|
||||
# Insert a storage-less global whose type instructs the compiler
|
||||
# to perform a system call instead of a regular call.
|
||||
|
|
|
|||
|
|
@ -36,48 +36,6 @@ class TKeyword(types.TMono):
|
|||
def is_keyword(typ):
|
||||
return isinstance(typ, TKeyword)
|
||||
|
||||
|
||||
# See rpc_proto.rs and comm_kernel.py:_{send,receive}_rpc_value.
|
||||
def rpc_tag(typ, error_handler):
|
||||
typ = typ.find()
|
||||
if types.is_tuple(typ):
|
||||
assert len(typ.elts) < 256
|
||||
return b"t" + bytes([len(typ.elts)]) + \
|
||||
b"".join([rpc_tag(elt_type, error_handler)
|
||||
for elt_type in typ.elts])
|
||||
elif builtins.is_none(typ):
|
||||
return b"n"
|
||||
elif builtins.is_bool(typ):
|
||||
return b"b"
|
||||
elif builtins.is_int(typ, types.TValue(32)):
|
||||
return b"i"
|
||||
elif builtins.is_int(typ, types.TValue(64)):
|
||||
return b"I"
|
||||
elif builtins.is_float(typ):
|
||||
return b"f"
|
||||
elif builtins.is_str(typ):
|
||||
return b"s"
|
||||
elif builtins.is_bytes(typ):
|
||||
return b"B"
|
||||
elif builtins.is_bytearray(typ):
|
||||
return b"A"
|
||||
elif builtins.is_list(typ):
|
||||
return b"l" + rpc_tag(builtins.get_iterable_elt(typ), error_handler)
|
||||
elif builtins.is_array(typ):
|
||||
num_dims = typ["num_dims"].value
|
||||
return b"a" + bytes([num_dims]) + rpc_tag(typ["elt"], error_handler)
|
||||
elif builtins.is_range(typ):
|
||||
return b"r" + rpc_tag(builtins.get_iterable_elt(typ), error_handler)
|
||||
elif is_keyword(typ):
|
||||
return b"k" + rpc_tag(typ.params["value"], error_handler)
|
||||
elif types.is_function(typ) or types.is_method(typ) or types.is_rpc(typ):
|
||||
raise ValueError("RPC tag for functional value")
|
||||
elif '__objectid__' in typ.attributes:
|
||||
return b"O"
|
||||
else:
|
||||
error_handler(typ)
|
||||
|
||||
|
||||
class Value:
|
||||
"""
|
||||
An SSA value that keeps track of its uses.
|
||||
|
|
@ -135,7 +93,6 @@ class NamedValue(Value):
|
|||
def __init__(self, typ, name):
|
||||
super().__init__(typ)
|
||||
self.name, self.function = name, None
|
||||
self.is_removed = False
|
||||
|
||||
def set_name(self, new_name):
|
||||
if self.function is not None:
|
||||
|
|
@ -236,7 +193,7 @@ class Instruction(User):
|
|||
self.drop_references()
|
||||
# Check this after drop_references in case this
|
||||
# is a self-referencing phi.
|
||||
assert all(use.is_removed for use in self.uses)
|
||||
assert not any(self.uses)
|
||||
|
||||
def replace_with(self, value):
|
||||
self.replace_all_uses_with(value)
|
||||
|
|
@ -371,7 +328,7 @@ class BasicBlock(NamedValue):
|
|||
self.remove_from_parent()
|
||||
# Check this after erasing instructions in case the block
|
||||
# loops into itself.
|
||||
assert all(use.is_removed for use in self.uses)
|
||||
assert not any(self.uses)
|
||||
|
||||
def prepend(self, insn):
|
||||
assert isinstance(insn, Instruction)
|
||||
|
|
@ -706,81 +663,6 @@ class SetLocal(Instruction):
|
|||
def value(self):
|
||||
return self.operands[1]
|
||||
|
||||
class GetArgFromRemote(Instruction):
|
||||
"""
|
||||
An instruction that receives function arguments from remote
|
||||
(ie. subkernel in DRTIO context)
|
||||
|
||||
:ivar arg_name: (string) argument name
|
||||
:ivar arg_type: argument type
|
||||
"""
|
||||
|
||||
"""
|
||||
:param arg_name: (string) argument name
|
||||
:param arg_type: argument type
|
||||
"""
|
||||
def __init__(self, arg_name, arg_type, name=""):
|
||||
assert isinstance(arg_name, str)
|
||||
super().__init__([], arg_type, name)
|
||||
self.arg_name = arg_name
|
||||
self.arg_type = arg_type
|
||||
|
||||
def copy(self, mapper):
|
||||
self_copy = super().copy(mapper)
|
||||
self_copy.arg_name = self.arg_name
|
||||
self_copy.arg_type = self.arg_type
|
||||
return self_copy
|
||||
|
||||
def opcode(self):
|
||||
return "getargfromremote({})".format(repr(self.arg_name))
|
||||
|
||||
class GetOptArgFromRemote(GetArgFromRemote):
|
||||
"""
|
||||
An instruction that may or may not retrieve an optional function argument
|
||||
from remote, depending on number of values received by firmware.
|
||||
|
||||
:ivar rcv_count: number of received values,
|
||||
determined by firmware
|
||||
:ivar index: (integer) index of the current argument,
|
||||
in reference to remote arguments
|
||||
"""
|
||||
|
||||
"""
|
||||
:param rcv_count: number of received valuese
|
||||
:param index: (integer) index of the current argument,
|
||||
in reference to remote arguments
|
||||
"""
|
||||
def __init__(self, arg_name, arg_type, rcv_count, index, name=""):
|
||||
super().__init__(arg_name, arg_type, name)
|
||||
self.rcv_count = rcv_count
|
||||
self.index = index
|
||||
|
||||
def copy(self, mapper):
|
||||
self_copy = super().copy(mapper)
|
||||
self_copy.rcv_count = self.rcv_count
|
||||
self_copy.index = self.index
|
||||
return self_copy
|
||||
|
||||
def opcode(self):
|
||||
return "getoptargfromremote({})".format(repr(self.arg_name))
|
||||
|
||||
class SubkernelAwaitArgs(Instruction):
|
||||
"""
|
||||
A builtin instruction that takes min and max received messages as operands,
|
||||
and a list of received types.
|
||||
|
||||
:ivar arg_types: (list of types) types of passed arguments (including optional)
|
||||
"""
|
||||
|
||||
"""
|
||||
:param arg_types: (list of types) types of passed arguments (including optional)
|
||||
"""
|
||||
|
||||
def __init__(self, operands, arg_types, name=None):
|
||||
assert isinstance(arg_types, list)
|
||||
self.arg_types = arg_types
|
||||
super().__init__(operands, builtins.TNone(), name)
|
||||
|
||||
class GetAttr(Instruction):
|
||||
"""
|
||||
An intruction that loads an attribute from an object,
|
||||
|
|
@ -803,7 +685,7 @@ class GetAttr(Instruction):
|
|||
typ = obj.type.attributes[attr]
|
||||
else:
|
||||
typ = obj.type.constructor.attributes[attr]
|
||||
if types.is_function(typ) or types.is_rpc(typ) or types.is_subkernel(typ):
|
||||
if types.is_function(typ) or types.is_rpc(typ):
|
||||
typ = types.TMethod(obj.type, typ)
|
||||
super().__init__([obj], typ, name)
|
||||
self.attr = attr
|
||||
|
|
@ -856,33 +738,6 @@ class SetAttr(Instruction):
|
|||
def value(self):
|
||||
return self.operands[1]
|
||||
|
||||
class Offset(Instruction):
|
||||
"""
|
||||
An intruction that adds an offset to a pointer (indexes into a list).
|
||||
|
||||
This is used to represent internally generated pointer arithmetic, and must
|
||||
remain inside the same object (see :class:`GetElem` and LLVM's GetElementPtr).
|
||||
"""
|
||||
|
||||
"""
|
||||
:param lst: (:class:`Value`) list
|
||||
:param index: (:class:`Value`) index
|
||||
"""
|
||||
def __init__(self, base, offset, name=""):
|
||||
assert isinstance(base, Value)
|
||||
assert isinstance(offset, Value)
|
||||
typ = types._TPointer(builtins.get_iterable_elt(base.type))
|
||||
super().__init__([base, offset], typ, name)
|
||||
|
||||
def opcode(self):
|
||||
return "offset"
|
||||
|
||||
def base(self):
|
||||
return self.operands[0]
|
||||
|
||||
def index(self):
|
||||
return self.operands[1]
|
||||
|
||||
class GetElem(Instruction):
|
||||
"""
|
||||
An intruction that loads an element from a list.
|
||||
|
|
@ -900,7 +755,7 @@ class GetElem(Instruction):
|
|||
def opcode(self):
|
||||
return "getelem"
|
||||
|
||||
def base(self):
|
||||
def list(self):
|
||||
return self.operands[0]
|
||||
|
||||
def index(self):
|
||||
|
|
@ -926,7 +781,7 @@ class SetElem(Instruction):
|
|||
def opcode(self):
|
||||
return "setelem"
|
||||
|
||||
def base(self):
|
||||
def list(self):
|
||||
return self.operands[0]
|
||||
|
||||
def index(self):
|
||||
|
|
@ -985,7 +840,6 @@ class Arith(Instruction):
|
|||
def rhs(self):
|
||||
return self.operands[1]
|
||||
|
||||
|
||||
class Compare(Instruction):
|
||||
"""
|
||||
A comparison operation on numbers.
|
||||
|
|
@ -1265,18 +1119,14 @@ class IndirectBranch(Terminator):
|
|||
class Return(Terminator):
|
||||
"""
|
||||
A return instruction.
|
||||
:param remote_return: (bool)
|
||||
marks a return in subkernel context,
|
||||
where the return value is sent back through DRTIO
|
||||
"""
|
||||
|
||||
"""
|
||||
:param value: (:class:`Value`) return value
|
||||
"""
|
||||
def __init__(self, value, remote_return=False, name=""):
|
||||
def __init__(self, value, name=""):
|
||||
assert isinstance(value, Value)
|
||||
super().__init__([value], builtins.TNone(), name)
|
||||
self.remote_return = remote_return
|
||||
|
||||
def opcode(self):
|
||||
return "return"
|
||||
|
|
@ -1325,9 +1175,9 @@ class Raise(Terminator):
|
|||
if len(self.operands) > 1:
|
||||
return self.operands[1]
|
||||
|
||||
class Resume(Terminator):
|
||||
class Reraise(Terminator):
|
||||
"""
|
||||
A resume instruction.
|
||||
A reraise instruction.
|
||||
"""
|
||||
|
||||
"""
|
||||
|
|
@ -1341,7 +1191,7 @@ class Resume(Terminator):
|
|||
super().__init__(operands, builtins.TNone(), name)
|
||||
|
||||
def opcode(self):
|
||||
return "resume"
|
||||
return "reraise"
|
||||
|
||||
def exception_target(self):
|
||||
if len(self.operands) > 0:
|
||||
|
|
@ -1427,7 +1277,6 @@ class LandingPad(Terminator):
|
|||
def __init__(self, cleanup, name=""):
|
||||
super().__init__([cleanup], builtins.TException(), name)
|
||||
self.types = []
|
||||
self.has_cleanup = True
|
||||
|
||||
def copy(self, mapper):
|
||||
self_copy = super().copy(mapper)
|
||||
|
|
|
|||
|
|
@ -1,70 +0,0 @@
|
|||
/* Force ld to make the ELF header as loadable. */
|
||||
PHDRS
|
||||
{
|
||||
headers PT_LOAD FILEHDR PHDRS ;
|
||||
text PT_LOAD ;
|
||||
data PT_LOAD ;
|
||||
dynamic PT_DYNAMIC ;
|
||||
eh_frame PT_GNU_EH_FRAME ;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Push back .text section enough so that ld.lld not complain */
|
||||
. = SIZEOF_HEADERS;
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text .text.*)
|
||||
} : text
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata .rodata.*)
|
||||
}
|
||||
|
||||
.eh_frame :
|
||||
{
|
||||
KEEP(*(.eh_frame))
|
||||
} : text
|
||||
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
KEEP(*(.eh_frame_hdr))
|
||||
} : text : eh_frame
|
||||
|
||||
.got :
|
||||
{
|
||||
*(.got)
|
||||
} : text
|
||||
|
||||
.got.plt :
|
||||
{
|
||||
*(.got.plt)
|
||||
} : text
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
} : data
|
||||
|
||||
.dynamic :
|
||||
{
|
||||
*(.dynamic)
|
||||
} : data : dynamic
|
||||
|
||||
.bss (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
__bss_start = .;
|
||||
*(.sbss .sbss.* .bss .bss.*);
|
||||
. = ALIGN(4);
|
||||
_end = .;
|
||||
}
|
||||
|
||||
/* Kernel stack grows downward from end of memory, so put guard page after
|
||||
* all the program contents. Note: This requires all loaded sections (at
|
||||
* least those accessed) to be explicitly listed in the above!
|
||||
*/
|
||||
. = ALIGN(0x1000);
|
||||
_sstack_guard = .;
|
||||
}
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
r"""
|
||||
The :mod:`math_fns` module lists math-related functions from NumPy recognized
|
||||
by the ARTIQ compiler so host function objects can be :func:`match`\ ed to
|
||||
the compiler type metadata describing their core device analogue.
|
||||
"""
|
||||
|
||||
from collections import OrderedDict
|
||||
import numpy
|
||||
from . import builtins, types
|
||||
|
||||
# Some special mathematical functions are exposed via their scipy.special
|
||||
# equivalents. Since the rest of the ARTIQ core does not depend on SciPy,
|
||||
# gracefully handle it not being present, making the functions simply not
|
||||
# available.
|
||||
try:
|
||||
import scipy.special as scipy_special
|
||||
except ImportError:
|
||||
scipy_special = None
|
||||
|
||||
#: float -> float numpy.* math functions for which llvm.* intrinsics exist.
|
||||
unary_fp_intrinsics = [(name, "llvm." + name + ".f64") for name in [
|
||||
"sin",
|
||||
"cos",
|
||||
"exp",
|
||||
"exp2",
|
||||
"log",
|
||||
"log10",
|
||||
"log2",
|
||||
"fabs",
|
||||
"floor",
|
||||
"ceil",
|
||||
"trunc",
|
||||
"sqrt",
|
||||
]] + [
|
||||
# numpy.rint() seems to (NumPy 1.19.0, Python 3.8.5, Linux x86_64)
|
||||
# implement round-to-even, but unfortunately, rust-lang/libm only
|
||||
# provides round(), which always rounds away from zero.
|
||||
#
|
||||
# As there is no equivalent of the latter in NumPy (nor any other
|
||||
# basic rounding function), expose round() as numpy.rint anyway,
|
||||
# even if the rounding modes don't match up, so there is some way
|
||||
# to do rounding on the core device. (numpy.round() has entirely
|
||||
# different semantics; it rounds to a configurable number of
|
||||
# decimals.)
|
||||
("rint", "llvm.round.f64"),
|
||||
]
|
||||
|
||||
#: float -> float numpy.* math functions lowered to runtime calls.
|
||||
unary_fp_runtime_calls = [
|
||||
("tan", "tan"),
|
||||
("arcsin", "asin"),
|
||||
("arccos", "acos"),
|
||||
("arctan", "atan"),
|
||||
("sinh", "sinh"),
|
||||
("cosh", "cosh"),
|
||||
("tanh", "tanh"),
|
||||
("arcsinh", "asinh"),
|
||||
("arccosh", "acosh"),
|
||||
("arctanh", "atanh"),
|
||||
("expm1", "expm1"),
|
||||
("cbrt", "cbrt"),
|
||||
]
|
||||
|
||||
#: float -> float numpy.* math functions lowered to runtime calls.
|
||||
unary_fp_runtime_calls = [
|
||||
("tan", "tan"),
|
||||
("arcsin", "asin"),
|
||||
("arccos", "acos"),
|
||||
("arctan", "atan"),
|
||||
("sinh", "sinh"),
|
||||
("cosh", "cosh"),
|
||||
("tanh", "tanh"),
|
||||
("arcsinh", "asinh"),
|
||||
("arccosh", "acosh"),
|
||||
("arctanh", "atanh"),
|
||||
("expm1", "expm1"),
|
||||
("cbrt", "cbrt"),
|
||||
]
|
||||
|
||||
scipy_special_unary_runtime_calls = [
|
||||
("erf", "erf"),
|
||||
("erfc", "erfc"),
|
||||
("gamma", "tgamma"),
|
||||
("gammaln", "lgamma"),
|
||||
("j0", "j0"),
|
||||
("j1", "j1"),
|
||||
("y0", "y0"),
|
||||
("y1", "y1"),
|
||||
]
|
||||
# Not mapped: jv/yv, libm only supports integer orders.
|
||||
|
||||
#: (float, float) -> float numpy.* math functions lowered to runtime calls.
|
||||
binary_fp_runtime_calls = [
|
||||
("arctan2", "atan2"),
|
||||
("copysign", "copysign"),
|
||||
("fmax", "fmax"),
|
||||
("fmin", "fmin"),
|
||||
# ("ldexp", "ldexp"), # One argument is an int; would need a bit more plumbing.
|
||||
("hypot", "hypot"),
|
||||
("nextafter", "nextafter"),
|
||||
]
|
||||
|
||||
#: Array handling builtins (special treatment due to allocations).
|
||||
numpy_builtins = ["transpose"]
|
||||
|
||||
|
||||
def fp_runtime_type(name, arity):
|
||||
args = [("arg{}".format(i), builtins.TFloat()) for i in range(arity)]
|
||||
return types.TExternalFunction(
|
||||
OrderedDict(args),
|
||||
builtins.TFloat(),
|
||||
name,
|
||||
# errno isn't observable from ARTIQ Python.
|
||||
flags={"nounwind", "nowrite"},
|
||||
broadcast_across_arrays=True)
|
||||
|
||||
|
||||
math_fn_map = {
|
||||
getattr(numpy, symbol): fp_runtime_type(mangle, arity=1)
|
||||
for symbol, mangle in (unary_fp_intrinsics + unary_fp_runtime_calls)
|
||||
}
|
||||
for symbol, mangle in binary_fp_runtime_calls:
|
||||
math_fn_map[getattr(numpy, symbol)] = fp_runtime_type(mangle, arity=2)
|
||||
for name in numpy_builtins:
|
||||
math_fn_map[getattr(numpy, name)] = types.TBuiltinFunction("numpy." + name)
|
||||
if scipy_special is not None:
|
||||
for symbol, mangle in scipy_special_unary_runtime_calls:
|
||||
math_fn_map[getattr(scipy_special, symbol)] = fp_runtime_type(mangle, arity=1)
|
||||
|
||||
|
||||
def match(obj):
|
||||
return math_fn_map.get(obj, None)
|
||||
|
|
@ -10,7 +10,7 @@ string and infers types for it using a trivial :module:`prelude`.
|
|||
|
||||
import os
|
||||
from pythonparser import source, diagnostic, parse_buffer
|
||||
from . import prelude, types, transforms, analyses, validators, embedding
|
||||
from . import prelude, types, transforms, analyses, validators
|
||||
|
||||
class Source:
|
||||
def __init__(self, source_buffer, engine=None):
|
||||
|
|
@ -18,7 +18,7 @@ class Source:
|
|||
self.engine = diagnostic.Engine(all_errors_are_fatal=True)
|
||||
else:
|
||||
self.engine = engine
|
||||
self.embedding_map = embedding.EmbeddingMap()
|
||||
self.embedding_map = None
|
||||
self.name, _ = os.path.splitext(os.path.basename(source_buffer.name))
|
||||
|
||||
asttyped_rewriter = transforms.ASTTypedRewriter(engine=engine,
|
||||
|
|
@ -57,8 +57,7 @@ class Module:
|
|||
constness_validator = validators.ConstnessValidator(engine=self.engine)
|
||||
artiq_ir_generator = transforms.ARTIQIRGenerator(engine=self.engine,
|
||||
module_name=src.name,
|
||||
ref_period=ref_period,
|
||||
embedding_map=self.embedding_map)
|
||||
ref_period=ref_period)
|
||||
dead_code_eliminator = transforms.DeadCodeEliminator(engine=self.engine)
|
||||
local_access_validator = validators.LocalAccessValidator(engine=self.engine)
|
||||
local_demoter = transforms.LocalDemoter()
|
||||
|
|
@ -67,8 +66,8 @@ class Module:
|
|||
interleaver = transforms.Interleaver(engine=self.engine)
|
||||
invariant_detection = analyses.InvariantDetection(engine=self.engine)
|
||||
|
||||
int_monomorphizer.visit(src.typedtree)
|
||||
cast_monomorphizer.visit(src.typedtree)
|
||||
int_monomorphizer.visit(src.typedtree)
|
||||
inferencer.visit(src.typedtree)
|
||||
monomorphism_validator.visit(src.typedtree)
|
||||
escape_validator.visit(src.typedtree)
|
||||
|
|
@ -84,8 +83,6 @@ class Module:
|
|||
constant_hoister.process(self.artiq_ir)
|
||||
if remarks:
|
||||
invariant_detection.process(self.artiq_ir)
|
||||
# for subkernels: main kernel inferencer output, to be passed to further compilations
|
||||
self.subkernel_arg_types = inferencer.subkernel_arg_types
|
||||
|
||||
def build_llvm_ir(self, target):
|
||||
"""Compile the module to LLVM IR for the specified target."""
|
||||
|
|
|
|||
|
|
@ -25,19 +25,16 @@ def globals():
|
|||
"IndexError": builtins.fn_IndexError(),
|
||||
"ValueError": builtins.fn_ValueError(),
|
||||
"ZeroDivisionError": builtins.fn_ZeroDivisionError(),
|
||||
"RuntimeError": builtins.fn_RuntimeError(),
|
||||
|
||||
# Built-in Python functions
|
||||
"len": builtins.fn_len(),
|
||||
"round": builtins.fn_round(),
|
||||
"abs": builtins.fn_abs(),
|
||||
"min": builtins.fn_min(),
|
||||
"max": builtins.fn_max(),
|
||||
"print": builtins.fn_print(),
|
||||
|
||||
# ARTIQ decorators
|
||||
"kernel": builtins.fn_kernel(),
|
||||
"subkernel": builtins.fn_kernel(),
|
||||
"portable": builtins.fn_kernel(),
|
||||
"rpc": builtins.fn_kernel(),
|
||||
|
||||
|
|
@ -45,6 +42,7 @@ def globals():
|
|||
"parallel": builtins.obj_parallel(),
|
||||
"interleave": builtins.obj_interleave(),
|
||||
"sequential": builtins.obj_sequential(),
|
||||
"watchdog": builtins.fn_watchdog(),
|
||||
|
||||
# ARTIQ time management functions
|
||||
"delay": builtins.fn_delay(),
|
||||
|
|
@ -55,8 +53,4 @@ def globals():
|
|||
# ARTIQ utility functions
|
||||
"rtio_log": builtins.fn_rtio_log(),
|
||||
"core_log": builtins.fn_print(),
|
||||
|
||||
# ARTIQ subkernel utility functions
|
||||
"subkernel_await": builtins.fn_subkernel_await(),
|
||||
"subkernel_preload": builtins.fn_subkernel_preload(),
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
import os, sys, tempfile, subprocess, io
|
||||
from artiq.compiler import types, ir
|
||||
from llvmlite import ir as ll, binding as llvm
|
||||
from llvmlite_artiq import ir as ll, binding as llvm
|
||||
|
||||
llvm.initialize()
|
||||
llvm.initialize_all_targets()
|
||||
|
|
@ -28,10 +28,8 @@ class RunTool:
|
|||
for argument in self._pattern:
|
||||
cmdline.append(argument.format(**self._tempnames))
|
||||
|
||||
# https://bugs.python.org/issue17023
|
||||
windows = os.name == "nt"
|
||||
process = subprocess.Popen(cmdline, stdout=subprocess.PIPE, stderr=subprocess.PIPE,
|
||||
universal_newlines=True, shell=windows)
|
||||
universal_newlines=True)
|
||||
stdout, stderr = process.communicate()
|
||||
if process.returncode != 0:
|
||||
raise Exception("{} invocation failed: {}".
|
||||
|
|
@ -69,41 +67,29 @@ class Target:
|
|||
generated by the ARTIQ compiler will be deployed.
|
||||
|
||||
:var triple: (string)
|
||||
LLVM target triple, e.g. ``"riscv32"``
|
||||
LLVM target triple, e.g. ``"or1k"``
|
||||
:var data_layout: (string)
|
||||
LLVM target data layout, e.g. ``"E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32"``
|
||||
:var features: (list of string)
|
||||
LLVM target CPU features, e.g. ``["mul", "div", "ffl1"]``
|
||||
:var additional_linker_options: (list of string)
|
||||
Linker options for the target in addition to the target-independent ones, e.g. ``["--target2=rel"]``
|
||||
:var print_function: (string)
|
||||
Name of a formatted print functions (with the signature of ``printf``)
|
||||
provided by the target, e.g. ``"printf"``.
|
||||
:var now_pinning: (boolean)
|
||||
Whether the target implements the now-pinning RTIO optimization.
|
||||
"""
|
||||
triple = "unknown"
|
||||
data_layout = ""
|
||||
features = []
|
||||
additional_linker_options = []
|
||||
print_function = "printf"
|
||||
now_pinning = True
|
||||
|
||||
tool_ld = "ld.lld"
|
||||
tool_strip = "llvm-strip"
|
||||
tool_symbolizer = "llvm-symbolizer"
|
||||
tool_cxxfilt = "llvm-cxxfilt"
|
||||
|
||||
def __init__(self, subkernel_id=None):
|
||||
def __init__(self):
|
||||
self.llcontext = ll.Context()
|
||||
self.subkernel_id = subkernel_id
|
||||
|
||||
def target_machine(self):
|
||||
lltarget = llvm.Target.from_triple(self.triple)
|
||||
llmachine = lltarget.create_target_machine(
|
||||
features=",".join(["+{}".format(f) for f in self.features]),
|
||||
reloc="pic", codemodel="default",
|
||||
abiname="ilp32d" if isinstance(self, RV32GTarget) else "")
|
||||
reloc="pic", codemodel="default")
|
||||
llmachine.set_asm_verbosity(True)
|
||||
return llmachine
|
||||
|
||||
|
|
@ -149,8 +135,7 @@ class Target:
|
|||
ir.BasicBlock._dump_loc = False
|
||||
|
||||
type_printer = types.TypePrinter()
|
||||
suffix = "_subkernel_{}".format(self.subkernel_id) if self.subkernel_id is not None else ""
|
||||
_dump(os.getenv("ARTIQ_DUMP_IR"), "ARTIQ IR", suffix + ".txt",
|
||||
_dump(os.getenv("ARTIQ_DUMP_IR"), "ARTIQ IR", ".txt",
|
||||
lambda: "\n".join(fn.as_entity(type_printer) for fn in module.artiq_ir))
|
||||
|
||||
llmod = module.build_llvm_ir(self)
|
||||
|
|
@ -162,12 +147,12 @@ class Target:
|
|||
_dump("", "LLVM IR (broken)", ".ll", lambda: str(llmod))
|
||||
raise
|
||||
|
||||
_dump(os.getenv("ARTIQ_DUMP_UNOPT_LLVM"), "LLVM IR (generated)", suffix + "_unopt.ll",
|
||||
_dump(os.getenv("ARTIQ_DUMP_UNOPT_LLVM"), "LLVM IR (generated)", "_unopt.ll",
|
||||
lambda: str(llparsedmod))
|
||||
|
||||
self.optimize(llparsedmod)
|
||||
|
||||
_dump(os.getenv("ARTIQ_DUMP_LLVM"), "LLVM IR (optimized)", suffix + ".ll",
|
||||
_dump(os.getenv("ARTIQ_DUMP_LLVM"), "LLVM IR (optimized)", ".ll",
|
||||
lambda: str(llparsedmod))
|
||||
|
||||
return llparsedmod
|
||||
|
|
@ -185,11 +170,8 @@ class Target:
|
|||
|
||||
def link(self, objects):
|
||||
"""Link the relocatable objects into a shared library for this target."""
|
||||
with RunTool([self.tool_ld, "-shared", "--eh-frame-hdr"] +
|
||||
self.additional_linker_options +
|
||||
["-T" + os.path.join(os.path.dirname(__file__), "kernel.ld")] +
|
||||
with RunTool([self.triple + "-ld", "-shared", "--eh-frame-hdr"] +
|
||||
["{{obj{}}}".format(index) for index in range(len(objects))] +
|
||||
["-x"] +
|
||||
["-o", "{output}"],
|
||||
output=None,
|
||||
**{"obj{}".format(index): obj for index, obj in enumerate(objects)}) \
|
||||
|
|
@ -205,7 +187,7 @@ class Target:
|
|||
return self.link([self.assemble(self.compile(module)) for module in modules])
|
||||
|
||||
def strip(self, library):
|
||||
with RunTool([self.tool_strip, "--strip-debug", "{library}", "-o", "{output}"],
|
||||
with RunTool([self.triple + "-strip", "--strip-debug", "{library}", "-o", "{output}"],
|
||||
library=library, output=None) \
|
||||
as results:
|
||||
return results["output"].read()
|
||||
|
|
@ -218,10 +200,9 @@ class Target:
|
|||
# just after the call. Offset them back to get an address somewhere
|
||||
# inside the call instruction (or its delay slot), since that's what
|
||||
# the backtrace entry should point at.
|
||||
last_inlined = None
|
||||
offset_addresses = [hex(addr - 1) for addr in addresses]
|
||||
with RunTool([self.tool_symbolizer, "--addresses", "--functions", "--inlines",
|
||||
"--demangle", "--output-style=GNU", "--exe={library}"] + offset_addresses,
|
||||
with RunTool([self.triple + "-addr2line", "--addresses", "--functions", "--inlines",
|
||||
"--demangle", "--exe={library}"] + offset_addresses,
|
||||
library=library) \
|
||||
as results:
|
||||
lines = iter(results["__stdout__"].read().rstrip().split("\n"))
|
||||
|
|
@ -234,11 +215,9 @@ class Target:
|
|||
if address_or_function[:2] == "0x":
|
||||
address = int(address_or_function[2:], 16) + 1 # remove offset
|
||||
function = next(lines)
|
||||
inlined = False
|
||||
else:
|
||||
address = backtrace[-1][4] # inlined
|
||||
function = address_or_function
|
||||
inlined = True
|
||||
location = next(lines)
|
||||
|
||||
filename, line = location.rsplit(":", 1)
|
||||
|
|
@ -249,61 +228,21 @@ class Target:
|
|||
else:
|
||||
line = int(line)
|
||||
# can't get column out of addr2line D:
|
||||
if inlined:
|
||||
last_inlined.append((filename, line, -1, function, address))
|
||||
else:
|
||||
last_inlined = []
|
||||
backtrace.append((filename, line, -1, function, address,
|
||||
last_inlined))
|
||||
backtrace.append((filename, line, -1, function, address))
|
||||
return backtrace
|
||||
|
||||
def demangle(self, names):
|
||||
if not any(names):
|
||||
return names
|
||||
with RunTool([self.tool_cxxfilt] + names) as results:
|
||||
with RunTool([self.triple + "-c++filt"] + names) as results:
|
||||
return results["__stdout__"].read().rstrip().split("\n")
|
||||
|
||||
class NativeTarget(Target):
|
||||
def __init__(self):
|
||||
super().__init__()
|
||||
self.triple = llvm.get_default_triple()
|
||||
self.data_layout = str(llvm.targets.Target.from_default_triple().create_target_machine().target_data)
|
||||
|
||||
class RV32IMATarget(Target):
|
||||
triple = "riscv32-unknown-linux"
|
||||
data_layout = "e-m:e-p:32:32-i64:64-n32-S128"
|
||||
features = ["m", "a"]
|
||||
additional_linker_options = ["-m", "elf32lriscv"]
|
||||
class OR1KTarget(Target):
|
||||
triple = "or1k-linux"
|
||||
data_layout = "E-m:e-p:32:32-i8:8:8-i16:16:16-i64:32:32-" \
|
||||
"f64:32:32-v64:32:32-v128:32:32-a0:0:32-n32"
|
||||
features = ["mul", "div", "ffl1", "cmov", "addc"]
|
||||
print_function = "core_log"
|
||||
now_pinning = True
|
||||
|
||||
tool_ld = "ld.lld"
|
||||
tool_strip = "llvm-strip"
|
||||
tool_symbolizer = "llvm-symbolizer"
|
||||
tool_cxxfilt = "llvm-cxxfilt"
|
||||
|
||||
class RV32GTarget(Target):
|
||||
triple = "riscv32-unknown-linux"
|
||||
data_layout = "e-m:e-p:32:32-i64:64-n32-S128"
|
||||
features = ["m", "a", "f", "d"]
|
||||
additional_linker_options = ["-m", "elf32lriscv"]
|
||||
print_function = "core_log"
|
||||
now_pinning = True
|
||||
|
||||
tool_ld = "ld.lld"
|
||||
tool_strip = "llvm-strip"
|
||||
tool_symbolizer = "llvm-symbolizer"
|
||||
tool_cxxfilt = "llvm-cxxfilt"
|
||||
|
||||
class CortexA9Target(Target):
|
||||
triple = "armv7-unknown-linux-gnueabihf"
|
||||
data_layout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
|
||||
features = ["dsp", "fp16", "neon", "vfp3"]
|
||||
additional_linker_options = ["-m", "armelf_linux_eabi", "--target2=rel"]
|
||||
print_function = "core_log"
|
||||
now_pinning = False
|
||||
|
||||
tool_ld = "ld.lld"
|
||||
tool_strip = "llvm-strip"
|
||||
tool_symbolizer = "llvm-symbolizer"
|
||||
tool_cxxfilt = "llvm-cxxfilt"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
import os, sys, fileinput, ctypes
|
||||
from pythonparser import diagnostic
|
||||
from llvmlite import binding as llvm
|
||||
from llvmlite_artiq import binding as llvm
|
||||
from ..module import Module, Source
|
||||
from ..targets import NativeTarget
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
import sys, fileinput
|
||||
from pythonparser import diagnostic
|
||||
from llvmlite import ir as ll
|
||||
from llvmlite_artiq import ir as ll
|
||||
from ..module import Module, Source
|
||||
from ..targets import NativeTarget
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
import sys, os
|
||||
from pythonparser import diagnostic
|
||||
from ..module import Module, Source
|
||||
from ..targets import RV32GTarget
|
||||
from ..targets import OR1KTarget
|
||||
from . import benchmark
|
||||
|
||||
def main():
|
||||
|
|
@ -30,7 +30,7 @@ def main():
|
|||
benchmark(lambda: Module(source),
|
||||
"ARTIQ transforms and validators")
|
||||
|
||||
benchmark(lambda: RV32GTarget().compile_and_link([module]),
|
||||
benchmark(lambda: OR1KTarget().compile_and_link([module]),
|
||||
"LLVM optimization and linking")
|
||||
|
||||
if __name__ == "__main__":
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ from ...master.databases import DeviceDB, DatasetDB
|
|||
from ...master.worker_db import DeviceManager, DatasetManager
|
||||
from ..module import Module
|
||||
from ..embedding import Stitcher
|
||||
from ..targets import RV32GTarget
|
||||
from ..targets import OR1KTarget
|
||||
from . import benchmark
|
||||
|
||||
|
||||
|
|
@ -30,9 +30,8 @@ def main():
|
|||
device_db_path = os.path.join(os.path.dirname(sys.argv[1]), "device_db.py")
|
||||
device_mgr = DeviceManager(DeviceDB(device_db_path))
|
||||
|
||||
dataset_db_path = os.path.join(os.path.dirname(sys.argv[1]), "dataset_db.mdb")
|
||||
dataset_db = DatasetDB(dataset_db_path)
|
||||
dataset_mgr = DatasetManager()
|
||||
dataset_db_path = os.path.join(os.path.dirname(sys.argv[1]), "dataset_db.pyon")
|
||||
dataset_mgr = DatasetManager(DatasetDB(dataset_db_path))
|
||||
|
||||
argument_mgr = ProcessArgumentManager({})
|
||||
|
||||
|
|
@ -46,7 +45,7 @@ def main():
|
|||
|
||||
stitcher = embed()
|
||||
module = Module(stitcher)
|
||||
target = RV32GTarget()
|
||||
target = OR1KTarget()
|
||||
llvm_ir = target.compile(module)
|
||||
elf_obj = target.assemble(llvm_ir)
|
||||
elf_shlib = target.link([elf_obj])
|
||||
|
|
@ -69,7 +68,5 @@ def main():
|
|||
benchmark(lambda: target.strip(elf_shlib),
|
||||
"Stripping debug information")
|
||||
|
||||
dataset_db.close_db()
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
import sys, os
|
||||
from pythonparser import diagnostic
|
||||
from ..module import Module, Source
|
||||
from ..targets import RV32GTarget
|
||||
from ..targets import OR1KTarget
|
||||
|
||||
def main():
|
||||
if not len(sys.argv) > 1:
|
||||
|
|
@ -20,7 +20,7 @@ def main():
|
|||
for filename in sys.argv[1:]:
|
||||
modules.append(Module(Source.from_filename(filename, engine=engine)))
|
||||
|
||||
llobj = RV32GTarget().compile_and_link(modules)
|
||||
llobj = OR1KTarget().compile_and_link(modules)
|
||||
|
||||
basename, ext = os.path.splitext(sys.argv[-1])
|
||||
with open(basename + ".so", "wb") as f:
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -238,7 +238,7 @@ class ASTTypedRewriter(algorithm.Transformer):
|
|||
body=node.body, decorator_list=node.decorator_list,
|
||||
keyword_loc=node.keyword_loc, name_loc=node.name_loc,
|
||||
arrow_loc=node.arrow_loc, colon_loc=node.colon_loc, at_locs=node.at_locs,
|
||||
loc=node.loc, remote_fn=False)
|
||||
loc=node.loc)
|
||||
|
||||
try:
|
||||
self.env_stack.append(node.typing_env)
|
||||
|
|
@ -439,9 +439,8 @@ class ASTTypedRewriter(algorithm.Transformer):
|
|||
|
||||
def visit_Call(self, node):
|
||||
node = self.generic_visit(node)
|
||||
node = asttyped.CallT(type=types.TVar(), iodelay=None, arg_exprs={},
|
||||
remote_fn=False, func=node.func,
|
||||
args=node.args, keywords=node.keywords,
|
||||
node = asttyped.CallT(type=types.TVar(), iodelay=None, arg_exprs={},
|
||||
func=node.func, args=node.args, keywords=node.keywords,
|
||||
starargs=node.starargs, kwargs=node.kwargs,
|
||||
star_loc=node.star_loc, dstar_loc=node.dstar_loc,
|
||||
begin_loc=node.begin_loc, end_loc=node.end_loc, loc=node.loc)
|
||||
|
|
|
|||
|
|
@ -11,12 +11,13 @@ class CastMonomorphizer(algorithm.Visitor):
|
|||
self.engine = engine
|
||||
|
||||
def visit_CallT(self, node):
|
||||
self.generic_visit(node)
|
||||
|
||||
if (types.is_builtin(node.func.type, "int") or
|
||||
types.is_builtin(node.func.type, "int32") or
|
||||
types.is_builtin(node.func.type, "int64")):
|
||||
typ = node.type.find()
|
||||
if (not types.is_var(typ["width"]) and
|
||||
len(node.args) == 1 and
|
||||
builtins.is_int(node.args[0].type) and
|
||||
types.is_var(node.args[0].type.find()["width"])):
|
||||
if isinstance(node.args[0], asttyped.BinOpT):
|
||||
|
|
@ -28,20 +29,3 @@ class CastMonomorphizer(algorithm.Visitor):
|
|||
|
||||
node.args[0].type.unify(typ)
|
||||
|
||||
if types.is_builtin(node.func.type, "int") or \
|
||||
types.is_builtin(node.func.type, "round"):
|
||||
typ = node.type.find()
|
||||
if types.is_var(typ["width"]):
|
||||
typ["width"].unify(types.TValue(32))
|
||||
|
||||
self.generic_visit(node)
|
||||
|
||||
def visit_CoerceT(self, node):
|
||||
if isinstance(node.value, asttyped.NumT) and \
|
||||
builtins.is_int(node.type) and \
|
||||
builtins.is_int(node.value.type) and \
|
||||
not types.is_var(node.type["width"]) and \
|
||||
types.is_var(node.value.type["width"]):
|
||||
node.value.type.unify(node.type)
|
||||
|
||||
self.generic_visit(node)
|
||||
|
|
|
|||
|
|
@ -15,26 +15,13 @@ class DeadCodeEliminator:
|
|||
self.process_function(func)
|
||||
|
||||
def process_function(self, func):
|
||||
# defer removing those blocks, so our use checks will ignore deleted blocks
|
||||
preserve = [func.entry()]
|
||||
work_list = [func.entry()]
|
||||
while any(work_list):
|
||||
block = work_list.pop()
|
||||
for succ in block.successors():
|
||||
if succ not in preserve:
|
||||
preserve.append(succ)
|
||||
work_list.append(succ)
|
||||
|
||||
to_be_removed = []
|
||||
for block in func.basic_blocks:
|
||||
if block not in preserve:
|
||||
block.is_removed = True
|
||||
to_be_removed.append(block)
|
||||
for insn in block.instructions:
|
||||
insn.is_removed = True
|
||||
|
||||
for block in to_be_removed:
|
||||
self.remove_block(block)
|
||||
modified = True
|
||||
while modified:
|
||||
modified = False
|
||||
for block in list(func.basic_blocks):
|
||||
if not any(block.predecessors()) and block != func.entry():
|
||||
self.remove_block(block)
|
||||
modified = True
|
||||
|
||||
modified = True
|
||||
while modified:
|
||||
|
|
@ -46,8 +33,7 @@ class DeadCodeEliminator:
|
|||
# it also has to run after the interleaver, but interleaver
|
||||
# doesn't like to work with IR before DCE.
|
||||
if isinstance(insn, (ir.Phi, ir.Alloc, ir.GetAttr, ir.GetElem, ir.Coerce,
|
||||
ir.Arith, ir.Compare, ir.Select, ir.Quote, ir.Closure,
|
||||
ir.Offset)) \
|
||||
ir.Arith, ir.Compare, ir.Select, ir.Quote, ir.Closure)) \
|
||||
and not any(insn.uses):
|
||||
insn.erase()
|
||||
modified = True
|
||||
|
|
@ -55,8 +41,6 @@ class DeadCodeEliminator:
|
|||
def remove_block(self, block):
|
||||
# block.uses are updated while iterating
|
||||
for use in set(block.uses):
|
||||
if use.is_removed:
|
||||
continue
|
||||
if isinstance(use, ir.Phi):
|
||||
use.remove_incoming_block(block)
|
||||
if not any(use.operands):
|
||||
|
|
@ -71,8 +55,6 @@ class DeadCodeEliminator:
|
|||
|
||||
def remove_instruction(self, insn):
|
||||
for use in set(insn.uses):
|
||||
if use.is_removed:
|
||||
continue
|
||||
if isinstance(use, ir.Phi):
|
||||
use.remove_incoming_value(insn)
|
||||
if not any(use.operands):
|
||||
|
|
|
|||
|
|
@ -6,30 +6,6 @@ from collections import OrderedDict
|
|||
from pythonparser import algorithm, diagnostic, ast
|
||||
from .. import asttyped, types, builtins
|
||||
from .typedtree_printer import TypedtreePrinter
|
||||
from artiq.experiment import kernel
|
||||
|
||||
|
||||
def is_nested_empty_list(node):
|
||||
"""If the passed AST node is an empty list, or a regularly nested list thereof,
|
||||
returns the number of nesting layers, or ``None`` otherwise.
|
||||
|
||||
For instance, ``is_nested_empty_list([]) == 1`` and
|
||||
``is_nested_empty_list([[], []]) == 2``, but
|
||||
``is_nested_empty_list([[[]], []]) == None`` as the number of nesting layers doesn't
|
||||
match.
|
||||
"""
|
||||
if not isinstance(node, ast.List):
|
||||
return None
|
||||
if not node.elts:
|
||||
return 1
|
||||
result = is_nested_empty_list(node.elts[0])
|
||||
if result is None:
|
||||
return None
|
||||
for elt in node.elts[:1]:
|
||||
if result != is_nested_empty_list(elt):
|
||||
return None
|
||||
return result + 1
|
||||
|
||||
|
||||
class Inferencer(algorithm.Visitor):
|
||||
"""
|
||||
|
|
@ -46,7 +22,6 @@ class Inferencer(algorithm.Visitor):
|
|||
self.function = None # currently visited function, for Return inference
|
||||
self.in_loop = False
|
||||
self.has_return = False
|
||||
self.subkernel_arg_types = dict()
|
||||
|
||||
def _unify(self, typea, typeb, loca, locb, makenotes=None, when=""):
|
||||
try:
|
||||
|
|
@ -179,7 +154,7 @@ class Inferencer(algorithm.Visitor):
|
|||
# Convert to a method.
|
||||
attr_type = types.TMethod(object_type, attr_type)
|
||||
self._unify_method_self(attr_type, attr_name, attr_loc, loc, value_node.loc)
|
||||
elif types.is_rpc(attr_type) or types.is_subkernel(attr_type):
|
||||
elif types.is_rpc(attr_type):
|
||||
# Convert to a method. We don't have to bother typechecking
|
||||
# the self argument, since for RPCs anything goes.
|
||||
attr_type = types.TMethod(object_type, attr_type)
|
||||
|
|
@ -208,14 +183,6 @@ class Inferencer(algorithm.Visitor):
|
|||
if builtins.is_bytes(collection.type) or builtins.is_bytearray(collection.type):
|
||||
self._unify(element.type, builtins.get_iterable_elt(collection.type),
|
||||
element.loc, None)
|
||||
elif builtins.is_array(collection.type):
|
||||
array_type = collection.type.find()
|
||||
elem_dims = array_type["num_dims"].value - 1
|
||||
if elem_dims > 0:
|
||||
elem_type = builtins.TArray(array_type["elt"], types.TValue(elem_dims))
|
||||
else:
|
||||
elem_type = array_type["elt"]
|
||||
self._unify(element.type, elem_type, element.loc, collection.loc)
|
||||
elif builtins.is_iterable(collection.type) and not builtins.is_str(collection.type):
|
||||
rhs_type = collection.type.find()
|
||||
rhs_wrapped_lhs_type = types.TMono(rhs_type.name, {"elt": element.type})
|
||||
|
|
@ -232,15 +199,15 @@ class Inferencer(algorithm.Visitor):
|
|||
self.generic_visit(node)
|
||||
value = node.value
|
||||
if types.is_tuple(value.type):
|
||||
for elt in value.type.find().elts:
|
||||
self._unify(elt, builtins.TInt(),
|
||||
value.loc, None)
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
"multi-dimensional slices are not supported", {},
|
||||
node.loc, [])
|
||||
self.engine.process(diag)
|
||||
else:
|
||||
self._unify(value.type, builtins.TInt(),
|
||||
value.loc, None)
|
||||
|
||||
def visit_SliceT(self, node):
|
||||
self.generic_visit(node)
|
||||
if (node.lower, node.upper, node.step) == (None, None, None):
|
||||
self._unify(node.type, builtins.TInt32(),
|
||||
node.loc, None)
|
||||
|
|
@ -260,78 +227,16 @@ class Inferencer(algorithm.Visitor):
|
|||
|
||||
def visit_SubscriptT(self, node):
|
||||
self.generic_visit(node)
|
||||
|
||||
if types.is_tuple(node.value.type):
|
||||
if (not isinstance(node.slice, ast.Index) or
|
||||
not isinstance(node.slice.value, ast.Num)):
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error", "tuples can only be indexed by a constant", {},
|
||||
node.slice.loc, []
|
||||
)
|
||||
self.engine.process(diag)
|
||||
return
|
||||
|
||||
tuple_type = node.value.type.find()
|
||||
index = node.slice.value.n
|
||||
if index < 0 or index >= len(tuple_type.elts):
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error",
|
||||
"index {index} is out of range for tuple of size {size}",
|
||||
{"index": index, "size": len(tuple_type.elts)},
|
||||
node.slice.loc, []
|
||||
)
|
||||
self.engine.process(diag)
|
||||
return
|
||||
|
||||
self._unify(node.type, tuple_type.elts[index], node.loc, node.value.loc)
|
||||
elif isinstance(node.slice, ast.Index):
|
||||
if types.is_tuple(node.slice.value.type):
|
||||
if types.is_var(node.value.type):
|
||||
return
|
||||
if not builtins.is_array(node.value.type):
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error",
|
||||
"multi-dimensional indexing only supported for arrays, not {type}",
|
||||
{"type": types.TypePrinter().name(node.value.type)},
|
||||
node.loc, [])
|
||||
self.engine.process(diag)
|
||||
return
|
||||
num_idxs = len(node.slice.value.type.find().elts)
|
||||
array_type = node.value.type.find()
|
||||
num_dims = array_type["num_dims"].value
|
||||
remaining_dims = num_dims - num_idxs
|
||||
if remaining_dims < 0:
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error",
|
||||
"too many indices for array of dimension {num_dims}",
|
||||
{"num_dims": num_dims}, node.slice.loc, [])
|
||||
self.engine.process(diag)
|
||||
return
|
||||
if remaining_dims == 0:
|
||||
self._unify(node.type, array_type["elt"], node.loc,
|
||||
node.value.loc)
|
||||
else:
|
||||
self._unify(
|
||||
node.type,
|
||||
builtins.TArray(array_type["elt"], remaining_dims))
|
||||
else:
|
||||
self._unify_iterable(element=node, collection=node.value)
|
||||
if isinstance(node.slice, ast.Index):
|
||||
self._unify_iterable(element=node, collection=node.value)
|
||||
elif isinstance(node.slice, ast.Slice):
|
||||
if builtins.is_array(node.value.type):
|
||||
if node.slice.step is not None:
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error",
|
||||
"strided slicing not yet supported for NumPy arrays", {},
|
||||
node.slice.step.loc, [])
|
||||
self.engine.process(diag)
|
||||
return
|
||||
self._unify(node.type, node.value.type, node.loc, node.value.loc)
|
||||
else: # ExtSlice
|
||||
pass # error emitted above
|
||||
self._unify(node.type, node.value.type,
|
||||
node.loc, node.value.loc)
|
||||
else: # ExtSlice
|
||||
pass # error emitted above
|
||||
|
||||
def visit_IfExpT(self, node):
|
||||
self.generic_visit(node)
|
||||
self._unify(node.test.type, builtins.TBool(), node.test.loc, None)
|
||||
self._unify(node.body.type, node.orelse.type,
|
||||
node.body.loc, node.orelse.loc)
|
||||
self._unify(node.type, node.body.type,
|
||||
|
|
@ -360,36 +265,21 @@ class Inferencer(algorithm.Visitor):
|
|||
node.operand.loc)
|
||||
self.engine.process(diag)
|
||||
else: # UAdd, USub
|
||||
if types.is_var(operand_type):
|
||||
return
|
||||
|
||||
if builtins.is_numeric(operand_type):
|
||||
self._unify(node.type, operand_type, node.loc, None)
|
||||
return
|
||||
|
||||
if builtins.is_array(operand_type):
|
||||
elt = operand_type.find()["elt"]
|
||||
if builtins.is_numeric(elt):
|
||||
self._unify(node.type, operand_type, node.loc, None)
|
||||
return
|
||||
if types.is_var(elt):
|
||||
return
|
||||
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
"expected unary '{op}' operand to be of numeric type, not {type}",
|
||||
{"op": node.op.loc.source(),
|
||||
"type": types.TypePrinter().name(operand_type)},
|
||||
node.operand.loc)
|
||||
self.engine.process(diag)
|
||||
self._unify(node.type, operand_type,
|
||||
node.loc, None)
|
||||
elif not types.is_var(operand_type):
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
"expected unary '{op}' operand to be of numeric type, not {type}",
|
||||
{"op": node.op.loc.source(),
|
||||
"type": types.TypePrinter().name(operand_type)},
|
||||
node.operand.loc)
|
||||
self.engine.process(diag)
|
||||
|
||||
def visit_CoerceT(self, node):
|
||||
self.generic_visit(node)
|
||||
if builtins.is_numeric(node.type) and builtins.is_numeric(node.value.type):
|
||||
pass
|
||||
elif (builtins.is_array(node.type) and builtins.is_array(node.value.type)
|
||||
and builtins.is_numeric(node.type.find()["elt"])
|
||||
and builtins.is_numeric(node.value.type.find()["elt"])):
|
||||
pass
|
||||
else:
|
||||
printer = types.TypePrinter()
|
||||
note = diagnostic.Diagnostic("note",
|
||||
|
|
@ -415,7 +305,7 @@ class Inferencer(algorithm.Visitor):
|
|||
self.visit(node)
|
||||
return node
|
||||
|
||||
def _coerce_numeric(self, nodes, map_return=lambda typ: typ, map_node_type =lambda typ:typ):
|
||||
def _coerce_numeric(self, nodes, map_return=lambda typ: typ):
|
||||
# See https://docs.python.org/3/library/stdtypes.html#numeric-types-int-float-complex.
|
||||
node_types = []
|
||||
for node in nodes:
|
||||
|
|
@ -431,7 +321,6 @@ class Inferencer(algorithm.Visitor):
|
|||
node_types.append(node.type)
|
||||
else:
|
||||
node_types.append(node.type)
|
||||
node_types = [map_node_type(typ) for typ in node_types]
|
||||
if any(map(types.is_var, node_types)): # not enough info yet
|
||||
return
|
||||
elif not all(map(builtins.is_numeric, node_types)):
|
||||
|
|
@ -463,125 +352,8 @@ class Inferencer(algorithm.Visitor):
|
|||
else:
|
||||
assert False
|
||||
|
||||
def _coerce_binary_broadcast_op(self, left, right, map_return_elt, op_loc):
|
||||
def num_dims(typ):
|
||||
if builtins.is_array(typ):
|
||||
# TODO: If number of dimensions is ever made a non-fixed parameter,
|
||||
# need to acutally unify num_dims in _coerce_binop/….
|
||||
return typ.find()["num_dims"].value
|
||||
return 0
|
||||
|
||||
left_dims = num_dims(left.type)
|
||||
right_dims = num_dims(right.type)
|
||||
if left_dims != right_dims and left_dims != 0 and right_dims != 0:
|
||||
# Mismatch (only scalar broadcast supported for now).
|
||||
note1 = diagnostic.Diagnostic("note", "operand of dimension {num_dims}",
|
||||
{"num_dims": left_dims}, left.loc)
|
||||
note2 = diagnostic.Diagnostic("note", "operand of dimension {num_dims}",
|
||||
{"num_dims": right_dims}, right.loc)
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error", "dimensions of '{op}' array operands must match",
|
||||
{"op": op_loc.source()}, op_loc, [left.loc, right.loc], [note1, note2])
|
||||
self.engine.process(diag)
|
||||
return
|
||||
|
||||
def map_node_type(typ):
|
||||
if not builtins.is_array(typ):
|
||||
# This is a single value broadcast across the array.
|
||||
return typ
|
||||
return typ.find()["elt"]
|
||||
|
||||
# Figure out result type, handling broadcasts.
|
||||
result_dims = left_dims if left_dims else right_dims
|
||||
def map_return(typ):
|
||||
elt = map_return_elt(typ)
|
||||
result = builtins.TArray(elt=elt, num_dims=result_dims)
|
||||
left = builtins.TArray(elt=elt, num_dims=left_dims) if left_dims else elt
|
||||
right = builtins.TArray(elt=elt, num_dims=right_dims) if right_dims else elt
|
||||
return (result, left, right)
|
||||
|
||||
return self._coerce_numeric((left, right),
|
||||
map_return=map_return,
|
||||
map_node_type=map_node_type)
|
||||
|
||||
def _coerce_binop(self, op, left, right):
|
||||
if isinstance(op, ast.MatMult):
|
||||
if types.is_var(left.type) or types.is_var(right.type):
|
||||
return
|
||||
|
||||
def num_dims(operand):
|
||||
if not builtins.is_array(operand.type):
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error",
|
||||
"expected matrix multiplication operand to be of array type, not {type}",
|
||||
{
|
||||
"op": op.loc.source(),
|
||||
"type": types.TypePrinter().name(operand.type)
|
||||
}, op.loc, [operand.loc])
|
||||
self.engine.process(diag)
|
||||
return
|
||||
num_dims = operand.type.find()["num_dims"].value
|
||||
if num_dims not in (1, 2):
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error",
|
||||
"expected matrix multiplication operand to be 1- or 2-dimensional, not {type}",
|
||||
{
|
||||
"op": op.loc.source(),
|
||||
"type": types.TypePrinter().name(operand.type)
|
||||
}, op.loc, [operand.loc])
|
||||
self.engine.process(diag)
|
||||
return
|
||||
return num_dims
|
||||
|
||||
left_dims = num_dims(left)
|
||||
if not left_dims:
|
||||
return
|
||||
right_dims = num_dims(right)
|
||||
if not right_dims:
|
||||
return
|
||||
|
||||
def map_node_type(typ):
|
||||
return typ.find()["elt"]
|
||||
|
||||
def map_return(typ):
|
||||
if left_dims == 1:
|
||||
if right_dims == 1:
|
||||
result_dims = 0
|
||||
else:
|
||||
result_dims = 1
|
||||
elif right_dims == 1:
|
||||
result_dims = 1
|
||||
else:
|
||||
result_dims = 2
|
||||
result = typ if result_dims == 0 else builtins.TArray(
|
||||
typ, result_dims)
|
||||
return (result, builtins.TArray(typ, left_dims),
|
||||
builtins.TArray(typ, right_dims))
|
||||
|
||||
return self._coerce_numeric((left, right),
|
||||
map_return=map_return,
|
||||
map_node_type=map_node_type)
|
||||
elif builtins.is_array(left.type) or builtins.is_array(right.type):
|
||||
# Operations on arrays are element-wise (possibly using broadcasting).
|
||||
|
||||
# TODO: Allow only for integer arrays.
|
||||
# allowed_int_array_ops = (ast.BitAnd, ast.BitOr, ast.BitXor, ast.LShift,
|
||||
# ast.RShift)
|
||||
allowed_array_ops = (ast.Add, ast.Mult, ast.FloorDiv, ast.Mod,
|
||||
ast.Pow, ast.Sub, ast.Div)
|
||||
if not isinstance(op, allowed_array_ops):
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error", "operator '{op}' not valid for array types",
|
||||
{"op": op.loc.source()}, op.loc)
|
||||
self.engine.process(diag)
|
||||
return
|
||||
|
||||
def map_result(typ):
|
||||
if isinstance(op, ast.Div):
|
||||
return builtins.TFloat()
|
||||
return typ
|
||||
return self._coerce_binary_broadcast_op(left, right, map_result, op.loc)
|
||||
elif isinstance(op, (ast.BitAnd, ast.BitOr, ast.BitXor,
|
||||
if isinstance(op, (ast.BitAnd, ast.BitOr, ast.BitXor,
|
||||
ast.LShift, ast.RShift)):
|
||||
# bitwise operators require integers
|
||||
for operand in (left, right):
|
||||
|
|
@ -680,7 +452,7 @@ class Inferencer(algorithm.Visitor):
|
|||
# division always returns a float
|
||||
return self._coerce_numeric((left, right),
|
||||
lambda typ: (builtins.TFloat(), builtins.TFloat(), builtins.TFloat()))
|
||||
else:
|
||||
else: # MatMult
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
"operator '{op}' is not supported", {"op": op.loc.source()},
|
||||
op.loc)
|
||||
|
|
@ -923,111 +695,28 @@ class Inferencer(algorithm.Visitor):
|
|||
"strings currently cannot be constructed", {},
|
||||
node.loc)
|
||||
self.engine.process(diag)
|
||||
elif types.is_builtin(typ, "array"):
|
||||
valid_forms = lambda: [
|
||||
valid_form("array(x:'a) -> array(elt='b) where 'a is iterable"),
|
||||
valid_form("array(x:'a, dtype:'b) -> array(elt='b) where 'a is iterable")
|
||||
]
|
||||
elif types.is_builtin(typ, "list") or types.is_builtin(typ, "array"):
|
||||
if types.is_builtin(typ, "list"):
|
||||
valid_forms = lambda: [
|
||||
valid_form("list() -> list(elt='a)"),
|
||||
valid_form("list(x:'a) -> list(elt='b) where 'a is iterable")
|
||||
]
|
||||
|
||||
explicit_dtype = None
|
||||
keywords_acceptable = False
|
||||
if len(node.keywords) == 0:
|
||||
keywords_acceptable = True
|
||||
elif len(node.keywords) == 1:
|
||||
if node.keywords[0].arg == "dtype":
|
||||
keywords_acceptable = True
|
||||
explicit_dtype = node.keywords[0].value
|
||||
if len(node.args) == 1 and keywords_acceptable:
|
||||
arg, = node.args
|
||||
self._unify(node.type, builtins.TList(),
|
||||
node.loc, None)
|
||||
elif types.is_builtin(typ, "array"):
|
||||
valid_forms = lambda: [
|
||||
valid_form("array() -> array(elt='a)"),
|
||||
valid_form("array(x:'a) -> array(elt='b) where 'a is iterable")
|
||||
]
|
||||
|
||||
num_empty_dims = is_nested_empty_list(arg)
|
||||
if num_empty_dims is not None:
|
||||
# As a special case, following the behaviour of numpy.array (and
|
||||
# repr() on ndarrays), consider empty lists to be exactly of the
|
||||
# number of dimensions given, instead of potentially containing an
|
||||
# unknown number of extra dimensions.
|
||||
num_dims = num_empty_dims
|
||||
|
||||
# The ultimate element type will be TVar initially, but we might be
|
||||
# able to resolve it from context.
|
||||
elt = arg.type
|
||||
for _ in range(num_dims):
|
||||
assert builtins.is_list(elt)
|
||||
elt = elt.find()["elt"]
|
||||
else:
|
||||
# In the absence of any other information (there currently isn't a way
|
||||
# to specify any), assume that all iterables are expandable into a
|
||||
# (runtime-checked) rectangular array of the innermost element type.
|
||||
elt = arg.type
|
||||
num_dims = 0
|
||||
expected_dims = (node.type.find()["num_dims"].value
|
||||
if builtins.is_array(node.type) else -1)
|
||||
while True:
|
||||
if num_dims == expected_dims:
|
||||
# If we already know the number of dimensions of the result,
|
||||
# stop so we can disambiguate the (innermost) element type of
|
||||
# the argument if it is still unknown.
|
||||
break
|
||||
if types.is_var(elt):
|
||||
# Can't make progress here because we don't know how many more
|
||||
# dimensions might be "hidden" inside.
|
||||
return
|
||||
if not builtins.is_iterable(elt) or builtins.is_str(elt):
|
||||
break
|
||||
if builtins.is_array(elt):
|
||||
num_dims += elt.find()["num_dims"].value
|
||||
else:
|
||||
num_dims += 1
|
||||
elt = builtins.get_iterable_elt(elt)
|
||||
|
||||
if explicit_dtype is not None:
|
||||
# TODO: Factor out type detection; support quoted type constructors
|
||||
# (TList(TInt32), …)?
|
||||
typ = explicit_dtype.type
|
||||
if types.is_builtin(typ, "int32"):
|
||||
elt = builtins.TInt32()
|
||||
elif types.is_builtin(typ, "int64"):
|
||||
elt = builtins.TInt64()
|
||||
elif types.is_constructor(typ):
|
||||
elt = typ.find().instance
|
||||
else:
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error",
|
||||
"dtype argument of {builtin}() must be a valid constructor",
|
||||
{"builtin": typ.find().name},
|
||||
node.func.loc,
|
||||
notes=[note])
|
||||
self.engine.process(diag)
|
||||
return
|
||||
|
||||
if num_dims == 0:
|
||||
note = diagnostic.Diagnostic(
|
||||
"note", "this expression has type {type}",
|
||||
{"type": types.TypePrinter().name(arg.type)}, arg.loc)
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error",
|
||||
"the argument of {builtin}() must be of an iterable type",
|
||||
{"builtin": typ.find().name},
|
||||
node.func.loc,
|
||||
notes=[note])
|
||||
self.engine.process(diag)
|
||||
return
|
||||
|
||||
self._unify(node.type,
|
||||
builtins.TArray(elt, types.TValue(num_dims)),
|
||||
node.loc, arg.loc)
|
||||
self._unify(node.type, builtins.TArray(),
|
||||
node.loc, None)
|
||||
else:
|
||||
diagnose(valid_forms())
|
||||
elif types.is_builtin(typ, "list"):
|
||||
valid_forms = lambda: [
|
||||
valid_form("list() -> list(elt='a)"),
|
||||
valid_form("list(x:'a) -> list(elt='b) where 'a is iterable")
|
||||
]
|
||||
|
||||
self._unify(node.type, builtins.TList(), node.loc, None)
|
||||
assert False
|
||||
|
||||
if len(node.args) == 0 and len(node.keywords) == 0:
|
||||
pass # []
|
||||
pass # []
|
||||
elif len(node.args) == 1 and len(node.keywords) == 0:
|
||||
arg, = node.args
|
||||
|
||||
|
|
@ -1122,28 +811,6 @@ class Inferencer(algorithm.Visitor):
|
|||
arg.loc, None)
|
||||
else:
|
||||
diagnose(valid_forms())
|
||||
elif types.is_builtin(typ, "abs"):
|
||||
fn = typ.name
|
||||
|
||||
valid_forms = lambda: [
|
||||
valid_form("abs(x:numpy.int?) -> numpy.int?"),
|
||||
valid_form("abs(x:float) -> float")
|
||||
]
|
||||
|
||||
if len(node.args) == 1 and len(node.keywords) == 0:
|
||||
(arg,) = node.args
|
||||
if builtins.is_int(arg.type) or builtins.is_float(arg.type):
|
||||
self._unify(arg.type, node.type,
|
||||
arg.loc, node.loc)
|
||||
elif types.is_var(arg.type):
|
||||
pass # undetermined yet
|
||||
else:
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
"the arguments of abs() must be of a numeric type", {},
|
||||
node.func.loc)
|
||||
self.engine.process(diag)
|
||||
else:
|
||||
diagnose(valid_forms())
|
||||
elif types.is_builtin(typ, "min") or types.is_builtin(typ, "max"):
|
||||
fn = typ.name
|
||||
|
||||
|
|
@ -1190,69 +857,21 @@ class Inferencer(algorithm.Visitor):
|
|||
diagnose(valid_forms())
|
||||
elif types.is_builtin(typ, "make_array"):
|
||||
valid_forms = lambda: [
|
||||
valid_form("numpy.full(count:int32, value:'a) -> array(elt='a, num_dims=1)"),
|
||||
valid_form("numpy.full(shape:(int32,)*'b, value:'a) -> array(elt='a, num_dims='b)"),
|
||||
valid_form("numpy.full(count:int32, value:'a) -> numpy.array(elt='a)")
|
||||
]
|
||||
|
||||
self._unify(node.type, builtins.TArray(),
|
||||
node.loc, None)
|
||||
|
||||
if len(node.args) == 2 and len(node.keywords) == 0:
|
||||
arg0, arg1 = node.args
|
||||
|
||||
if types.is_var(arg0.type):
|
||||
return # undetermined yet
|
||||
elif types.is_tuple(arg0.type):
|
||||
num_dims = len(arg0.type.find().elts)
|
||||
self._unify(arg0.type, types.TTuple([builtins.TInt32()] * num_dims),
|
||||
arg0.loc, None)
|
||||
else:
|
||||
num_dims = 1
|
||||
self._unify(arg0.type, builtins.TInt32(),
|
||||
arg0.loc, None)
|
||||
|
||||
self._unify(node.type, builtins.TArray(num_dims=num_dims),
|
||||
node.loc, None)
|
||||
self._unify(arg0.type, builtins.TInt32(),
|
||||
arg0.loc, None)
|
||||
self._unify(arg1.type, node.type.find()["elt"],
|
||||
arg1.loc, None)
|
||||
else:
|
||||
diagnose(valid_forms())
|
||||
elif types.is_builtin(typ, "numpy.transpose"):
|
||||
valid_forms = lambda: [
|
||||
valid_form("transpose(x: array(elt='a, num_dims=1)) -> array(elt='a, num_dims=1)"),
|
||||
valid_form("transpose(x: array(elt='a, num_dims=2)) -> array(elt='a, num_dims=2)")
|
||||
]
|
||||
|
||||
if len(node.args) == 1 and len(node.keywords) == 0:
|
||||
arg, = node.args
|
||||
|
||||
if types.is_var(arg.type):
|
||||
pass # undetermined yet
|
||||
elif not builtins.is_array(arg.type):
|
||||
note = diagnostic.Diagnostic(
|
||||
"note", "this expression has type {type}",
|
||||
{"type": types.TypePrinter().name(arg.type)}, arg.loc)
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error",
|
||||
"the argument of {builtin}() must be an array",
|
||||
{"builtin": typ.find().name},
|
||||
node.func.loc,
|
||||
notes=[note])
|
||||
self.engine.process(diag)
|
||||
else:
|
||||
num_dims = arg.type.find()["num_dims"].value
|
||||
if num_dims not in (1, 2):
|
||||
note = diagnostic.Diagnostic(
|
||||
"note", "argument is {num_dims}-dimensional",
|
||||
{"num_dims": num_dims}, arg.loc)
|
||||
diag = diagnostic.Diagnostic(
|
||||
"error",
|
||||
"{builtin}() is currently only supported for up to "
|
||||
"two-dimensional arrays", {"builtin": typ.find().name},
|
||||
node.func.loc,
|
||||
notes=[note])
|
||||
self.engine.process(diag)
|
||||
else:
|
||||
self._unify(node.type, arg.type, node.loc, None)
|
||||
else:
|
||||
diagnose(valid_forms())
|
||||
elif types.is_builtin(typ, "rtio_log"):
|
||||
valid_forms = lambda: [
|
||||
valid_form("rtio_log(channel:str, args...) -> None"),
|
||||
|
|
@ -1286,6 +905,9 @@ class Inferencer(algorithm.Visitor):
|
|||
elif types.is_builtin(typ, "at_mu"):
|
||||
simple_form("at_mu(time_mu:numpy.int64) -> None",
|
||||
[builtins.TInt64()])
|
||||
elif types.is_builtin(typ, "watchdog"):
|
||||
simple_form("watchdog(time:float) -> [builtin context manager]",
|
||||
[builtins.TFloat()], builtins.TNone())
|
||||
elif types.is_constructor(typ):
|
||||
# An user-defined class.
|
||||
self._unify(node.type, typ.find().instance,
|
||||
|
|
@ -1294,55 +916,6 @@ class Inferencer(algorithm.Visitor):
|
|||
# Ignored.
|
||||
self._unify(node.type, builtins.TNone(),
|
||||
node.loc, None)
|
||||
elif types.is_builtin(typ, "subkernel_await"):
|
||||
valid_forms = lambda: [
|
||||
valid_form("subkernel_await(f: subkernel) -> f return type"),
|
||||
valid_form("subkernel_await(f: subkernel, timeout: numpy.int64) -> f return type")
|
||||
]
|
||||
if 1 <= len(node.args) <= 2:
|
||||
arg0 = node.args[0].type
|
||||
if types.is_var(arg0):
|
||||
pass # undetermined yet
|
||||
else:
|
||||
if types.is_method(arg0):
|
||||
fn = types.get_method_function(arg0)
|
||||
elif types.is_function(arg0) or types.is_subkernel(arg0):
|
||||
fn = arg0
|
||||
else:
|
||||
diagnose(valid_forms())
|
||||
self._unify(node.type, fn.ret,
|
||||
node.loc, None)
|
||||
if len(node.args) == 2:
|
||||
arg1 = node.args[1]
|
||||
if types.is_var(arg1.type):
|
||||
pass
|
||||
elif builtins.is_int(arg1.type):
|
||||
# promote to TInt64
|
||||
self._unify(arg1.type, builtins.TInt64(),
|
||||
arg1.loc, None)
|
||||
else:
|
||||
diagnose(valid_forms())
|
||||
else:
|
||||
diagnose(valid_forms())
|
||||
elif types.is_builtin(typ, "subkernel_preload"):
|
||||
valid_forms = lambda: [
|
||||
valid_form("subkernel_preload(f: subkernel) -> None")
|
||||
]
|
||||
if len(node.args) == 1:
|
||||
arg0 = node.args[0].type
|
||||
if types.is_var(arg0):
|
||||
pass # undetermined yet
|
||||
else:
|
||||
if types.is_method(arg0):
|
||||
fn = types.get_method_function(arg0)
|
||||
elif types.is_function(arg0) or types.is_subkernel(arg0):
|
||||
fn = arg0
|
||||
else:
|
||||
diagnose(valid_forms())
|
||||
self._unify(node.type, fn.ret,
|
||||
node.loc, None)
|
||||
else:
|
||||
diagnose(valid_forms())
|
||||
else:
|
||||
assert False
|
||||
|
||||
|
|
@ -1381,7 +954,6 @@ class Inferencer(algorithm.Visitor):
|
|||
typ_args = typ.args
|
||||
typ_optargs = typ.optargs
|
||||
typ_ret = typ.ret
|
||||
typ_func = typ
|
||||
else:
|
||||
typ_self = types.get_method_self(typ)
|
||||
typ_func = types.get_method_function(typ)
|
||||
|
|
@ -1419,43 +991,11 @@ class Inferencer(algorithm.Visitor):
|
|||
self.engine.process(diag)
|
||||
return
|
||||
|
||||
# Array broadcasting for functions explicitly marked as such.
|
||||
if len(node.args) == typ_arity and types.is_broadcast_across_arrays(typ):
|
||||
if typ_arity == 1:
|
||||
arg_type = node.args[0].type.find()
|
||||
if builtins.is_array(arg_type):
|
||||
typ_arg, = typ_args.values()
|
||||
self._unify(typ_arg, arg_type["elt"], node.args[0].loc, None)
|
||||
self._unify(node.type, builtins.TArray(typ_ret, arg_type["num_dims"]),
|
||||
node.loc, None)
|
||||
return
|
||||
elif typ_arity == 2:
|
||||
if any(builtins.is_array(arg.type) for arg in node.args):
|
||||
ret, arg0, arg1 = self._coerce_binary_broadcast_op(
|
||||
node.args[0], node.args[1], lambda t: typ_ret, node.loc)
|
||||
node.args[0] = self._coerce_one(arg0, node.args[0],
|
||||
other_node=node.args[1])
|
||||
node.args[1] = self._coerce_one(arg1, node.args[1],
|
||||
other_node=node.args[0])
|
||||
self._unify(node.type, ret, node.loc, None)
|
||||
return
|
||||
if types.is_subkernel(typ_func) and typ_func.sid not in self.subkernel_arg_types:
|
||||
self.subkernel_arg_types[typ_func.sid] = []
|
||||
|
||||
for actualarg, (formalname, formaltyp) in \
|
||||
zip(node.args, list(typ_args.items()) + list(typ_optargs.items())):
|
||||
self._unify(actualarg.type, formaltyp,
|
||||
actualarg.loc, None)
|
||||
passed_args[formalname] = actualarg.loc
|
||||
if types.is_subkernel(typ_func):
|
||||
if types.is_instance(actualarg.type):
|
||||
# objects cannot be passed to subkernels, as rpc code doesn't support them
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
"argument '{name}' of type: {typ} is not supported in subkernels",
|
||||
{"name": formalname, "typ": actualarg.type},
|
||||
actualarg.loc, [])
|
||||
self.engine.process(diag)
|
||||
self.subkernel_arg_types[typ_func.sid].append((formalname, formaltyp))
|
||||
|
||||
for keyword in node.keywords:
|
||||
if keyword.arg in passed_args:
|
||||
|
|
@ -1486,7 +1026,7 @@ class Inferencer(algorithm.Visitor):
|
|||
passed_args[keyword.arg] = keyword.arg_loc
|
||||
|
||||
for formalname in typ_args:
|
||||
if formalname not in passed_args and not node.remote_fn:
|
||||
if formalname not in passed_args:
|
||||
note = diagnostic.Diagnostic("note",
|
||||
"the called function is of type {type}",
|
||||
{"type": types.TypePrinter().name(node.func.type)},
|
||||
|
|
@ -1591,7 +1131,9 @@ class Inferencer(algorithm.Visitor):
|
|||
|
||||
typ = node.context_expr.type
|
||||
if (types.is_builtin(typ, "interleave") or types.is_builtin(typ, "sequential") or
|
||||
types.is_builtin(typ, "parallel")):
|
||||
types.is_builtin(typ, "parallel") or
|
||||
(isinstance(node.context_expr, asttyped.CallT) and
|
||||
types.is_builtin(node.context_expr.func.type, "watchdog"))):
|
||||
# builtin context managers
|
||||
if node.optional_vars is not None:
|
||||
self._unify(node.optional_vars.type, builtins.TNone(),
|
||||
|
|
@ -1749,14 +1291,7 @@ class Inferencer(algorithm.Visitor):
|
|||
|
||||
def visit_FunctionDefT(self, node):
|
||||
for index, decorator in enumerate(node.decorator_list):
|
||||
def eval_attr(attr):
|
||||
if isinstance(attr.value, asttyped.QuoteT):
|
||||
return getattr(attr.value.value, attr.attr)
|
||||
return getattr(eval_attr(attr.value), attr.attr)
|
||||
if isinstance(decorator, asttyped.AttributeT):
|
||||
decorator = eval_attr(decorator)
|
||||
if id(decorator) == id(kernel) or \
|
||||
types.is_builtin(decorator.type, "kernel") or \
|
||||
if types.is_builtin(decorator.type, "kernel") or \
|
||||
isinstance(decorator, asttyped.CallT) and \
|
||||
types.is_builtin(decorator.func.type, "kernel"):
|
||||
continue
|
||||
|
|
|
|||
|
|
@ -26,3 +26,22 @@ class IntMonomorphizer(algorithm.Visitor):
|
|||
return
|
||||
|
||||
node.type["width"].unify(types.TValue(width))
|
||||
|
||||
def visit_CallT(self, node):
|
||||
self.generic_visit(node)
|
||||
|
||||
if types.is_builtin(node.func.type, "int") or \
|
||||
types.is_builtin(node.func.type, "round"):
|
||||
typ = node.type.find()
|
||||
if types.is_var(typ["width"]):
|
||||
typ["width"].unify(types.TValue(32))
|
||||
|
||||
def visit_CoerceT(self, node):
|
||||
if isinstance(node.value, asttyped.NumT) and \
|
||||
builtins.is_int(node.type) and \
|
||||
builtins.is_int(node.value.type) and \
|
||||
not types.is_var(node.type["width"]) and \
|
||||
types.is_var(node.value.type["width"]):
|
||||
node.value.type.unify(node.type)
|
||||
|
||||
self.generic_visit(node)
|
||||
|
|
|
|||
|
|
@ -280,7 +280,7 @@ class IODelayEstimator(algorithm.Visitor):
|
|||
context="as an argument for delay_mu()")
|
||||
call_delay = value
|
||||
elif not types.is_builtin(typ):
|
||||
if types.is_function(typ) or types.is_rpc(typ) or types.is_subkernel(typ):
|
||||
if types.is_function(typ) or types.is_rpc(typ):
|
||||
offset = 0
|
||||
elif types.is_method(typ):
|
||||
offset = 1
|
||||
|
|
@ -288,7 +288,7 @@ class IODelayEstimator(algorithm.Visitor):
|
|||
else:
|
||||
assert False
|
||||
|
||||
if types.is_rpc(typ) or types.is_subkernel(typ):
|
||||
if types.is_rpc(typ):
|
||||
call_delay = iodelay.Const(0)
|
||||
else:
|
||||
delay = typ.find().delay.find()
|
||||
|
|
@ -311,20 +311,13 @@ class IODelayEstimator(algorithm.Visitor):
|
|||
args[arg_name] = arg_node
|
||||
|
||||
free_vars = delay.duration.free_vars()
|
||||
try:
|
||||
node.arg_exprs = {
|
||||
arg: self.evaluate(args[arg], abort=abort,
|
||||
context="in the expression for argument '{}' "
|
||||
"that affects I/O delay".format(arg))
|
||||
for arg in free_vars
|
||||
}
|
||||
call_delay = delay.duration.fold(node.arg_exprs)
|
||||
except KeyError as e:
|
||||
if getattr(node, "remote_fn", False):
|
||||
note = diagnostic.Diagnostic("note",
|
||||
"function called here", {},
|
||||
node.loc)
|
||||
self.abort("due to arguments passed remotely", node.loc, note)
|
||||
node.arg_exprs = {
|
||||
arg: self.evaluate(args[arg], abort=abort,
|
||||
context="in the expression for argument '{}' "
|
||||
"that affects I/O delay".format(arg))
|
||||
for arg in free_vars
|
||||
}
|
||||
call_delay = delay.duration.fold(node.arg_exprs)
|
||||
else:
|
||||
assert False
|
||||
else:
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -3,7 +3,6 @@ The :mod:`types` module contains the classes describing the types
|
|||
in :mod:`asttyped`.
|
||||
"""
|
||||
|
||||
import builtins
|
||||
import string
|
||||
from collections import OrderedDict
|
||||
from . import iodelay
|
||||
|
|
@ -56,39 +55,38 @@ class TVar(Type):
|
|||
|
||||
def __init__(self):
|
||||
self.parent = self
|
||||
self.rank = 0
|
||||
|
||||
def find(self):
|
||||
parent = self.parent
|
||||
if parent is self:
|
||||
if self.parent is self:
|
||||
return self
|
||||
else:
|
||||
# The recursive find() invocation is turned into a loop
|
||||
# because paths resulting from unification of large arrays
|
||||
# can easily cause a stack overflow.
|
||||
root = self
|
||||
while parent.__class__ == TVar and root is not parent:
|
||||
_, parent = root, root.parent = parent, parent.parent
|
||||
return root.parent
|
||||
while root.__class__ == TVar:
|
||||
if root is root.parent:
|
||||
break
|
||||
else:
|
||||
root = root.parent
|
||||
|
||||
# path compression
|
||||
iter = self
|
||||
while iter.__class__ == TVar:
|
||||
if iter is iter.parent:
|
||||
break
|
||||
else:
|
||||
iter, iter.parent = iter.parent, root
|
||||
|
||||
return root
|
||||
|
||||
def unify(self, other):
|
||||
if other is self:
|
||||
return
|
||||
x = other.find()
|
||||
y = self.find()
|
||||
if x is y:
|
||||
return
|
||||
if y.__class__ == TVar:
|
||||
if x.__class__ == TVar:
|
||||
if x.rank < y.rank:
|
||||
x, y = y, x
|
||||
y.parent = x
|
||||
if x.rank == y.rank:
|
||||
x.rank += 1
|
||||
else:
|
||||
y.parent = x
|
||||
other = other.find()
|
||||
|
||||
if self.parent is self:
|
||||
self.parent = other
|
||||
else:
|
||||
y.unify(x)
|
||||
self.find().unify(other)
|
||||
|
||||
def fold(self, accum, fn):
|
||||
if self.parent is self:
|
||||
|
|
@ -97,8 +95,6 @@ class TVar(Type):
|
|||
return self.find().fold(accum, fn)
|
||||
|
||||
def __repr__(self):
|
||||
if getattr(builtins, "__in_sphinx__", False):
|
||||
return str(self)
|
||||
if self.parent is self:
|
||||
return "<artiq.compiler.types.TVar %d>" % id(self)
|
||||
else:
|
||||
|
|
@ -128,8 +124,6 @@ class TMono(Type):
|
|||
return self
|
||||
|
||||
def unify(self, other):
|
||||
if other is self:
|
||||
return
|
||||
if isinstance(other, TMono) and self.name == other.name:
|
||||
assert self.params.keys() == other.params.keys()
|
||||
for param in self.params:
|
||||
|
|
@ -145,8 +139,6 @@ class TMono(Type):
|
|||
return fn(accum, self)
|
||||
|
||||
def __repr__(self):
|
||||
if getattr(builtins, "__in_sphinx__", False):
|
||||
return str(self)
|
||||
return "artiq.compiler.types.TMono(%s, %s)" % (repr(self.name), repr(self.params))
|
||||
|
||||
def __getitem__(self, param):
|
||||
|
|
@ -179,8 +171,6 @@ class TTuple(Type):
|
|||
return self
|
||||
|
||||
def unify(self, other):
|
||||
if other is self:
|
||||
return
|
||||
if isinstance(other, TTuple) and len(self.elts) == len(other.elts):
|
||||
for selfelt, otherelt in zip(self.elts, other.elts):
|
||||
selfelt.unify(otherelt)
|
||||
|
|
@ -195,8 +185,6 @@ class TTuple(Type):
|
|||
return fn(accum, self)
|
||||
|
||||
def __repr__(self):
|
||||
if getattr(builtins, "__in_sphinx__", False):
|
||||
return str(self)
|
||||
return "artiq.compiler.types.TTuple(%s)" % repr(self.elts)
|
||||
|
||||
def __eq__(self, other):
|
||||
|
|
@ -210,10 +198,8 @@ class TTuple(Type):
|
|||
return hash(tuple(self.elts))
|
||||
|
||||
class _TPointer(TMono):
|
||||
def __init__(self, elt=None):
|
||||
if elt is None:
|
||||
elt = TMono("int", {"width": 8}) # i8*
|
||||
super().__init__("pointer", params={"elt": elt})
|
||||
def __init__(self):
|
||||
super().__init__("pointer")
|
||||
|
||||
class TFunction(Type):
|
||||
"""
|
||||
|
|
@ -251,8 +237,6 @@ class TFunction(Type):
|
|||
return self
|
||||
|
||||
def unify(self, other):
|
||||
if other is self:
|
||||
return
|
||||
if isinstance(other, TFunction) and \
|
||||
self.args.keys() == other.args.keys() and \
|
||||
self.optargs.keys() == other.optargs.keys():
|
||||
|
|
@ -275,8 +259,6 @@ class TFunction(Type):
|
|||
return fn(accum, self)
|
||||
|
||||
def __repr__(self):
|
||||
if getattr(builtins, "__in_sphinx__", False):
|
||||
return str(self)
|
||||
return "artiq.compiler.types.TFunction({}, {}, {})".format(
|
||||
repr(self.args), repr(self.optargs), repr(self.ret))
|
||||
|
||||
|
|
@ -291,29 +273,20 @@ class TFunction(Type):
|
|||
def __hash__(self):
|
||||
return hash((_freeze(self.args), _freeze(self.optargs), self.ret))
|
||||
|
||||
class TExternalFunction(TFunction):
|
||||
class TCFunction(TFunction):
|
||||
"""
|
||||
A type of an externally-provided function.
|
||||
A function type of a runtime-provided C function.
|
||||
|
||||
This can be any function following the C ABI, such as provided by the
|
||||
C/Rust runtime, or a compiler backend intrinsic. The mangled name to link
|
||||
against is encoded as part of the type.
|
||||
|
||||
:ivar name: (str) external symbol name.
|
||||
This will be the symbol linked against (following any extra C name
|
||||
mangling rules).
|
||||
:ivar flags: (set of str) function flags.
|
||||
:ivar name: (str) C function name
|
||||
:ivar flags: (set of str) C function flags.
|
||||
Flag ``nounwind`` means the function never raises an exception.
|
||||
Flag ``nowrite`` means the function never accesses any memory
|
||||
Flag ``nowrite`` means the function never writes any memory
|
||||
that the ARTIQ Python code can observe.
|
||||
:ivar broadcast_across_arrays: (bool)
|
||||
If True, the function is transparently applied element-wise when called
|
||||
with TArray arguments.
|
||||
"""
|
||||
|
||||
attributes = OrderedDict()
|
||||
|
||||
def __init__(self, args, ret, name, flags=set(), broadcast_across_arrays=False):
|
||||
def __init__(self, args, ret, name, flags={}):
|
||||
assert isinstance(flags, set)
|
||||
for flag in flags:
|
||||
assert flag in {'nounwind', 'nowrite'}
|
||||
|
|
@ -321,12 +294,9 @@ class TExternalFunction(TFunction):
|
|||
self.name = name
|
||||
self.delay = TFixedDelay(iodelay.Const(0))
|
||||
self.flags = flags
|
||||
self.broadcast_across_arrays = broadcast_across_arrays
|
||||
|
||||
def unify(self, other):
|
||||
if other is self:
|
||||
return
|
||||
if isinstance(other, TExternalFunction) and \
|
||||
if isinstance(other, TCFunction) and \
|
||||
self.name == other.name:
|
||||
super().unify(other)
|
||||
elif isinstance(other, TVar):
|
||||
|
|
@ -341,24 +311,22 @@ class TRPC(Type):
|
|||
:ivar ret: (:class:`Type`)
|
||||
return type
|
||||
:ivar service: (int) RPC service number
|
||||
:ivar is_async: (bool) whether the RPC blocks until return
|
||||
:ivar async: (bool) whether the RPC blocks until return
|
||||
"""
|
||||
|
||||
attributes = OrderedDict()
|
||||
|
||||
def __init__(self, ret, service, is_async=False):
|
||||
def __init__(self, ret, service, async=False):
|
||||
assert isinstance(ret, Type)
|
||||
self.ret, self.service, self.is_async = ret, service, is_async
|
||||
self.ret, self.service, self.async = ret, service, async
|
||||
|
||||
def find(self):
|
||||
return self
|
||||
|
||||
def unify(self, other):
|
||||
if other is self:
|
||||
return
|
||||
if isinstance(other, TRPC) and \
|
||||
self.service == other.service and \
|
||||
self.is_async == other.is_async:
|
||||
self.async == other.async:
|
||||
self.ret.unify(other.ret)
|
||||
elif isinstance(other, TVar):
|
||||
other.unify(self)
|
||||
|
|
@ -370,14 +338,12 @@ class TRPC(Type):
|
|||
return fn(accum, self)
|
||||
|
||||
def __repr__(self):
|
||||
if getattr(builtins, "__in_sphinx__", False):
|
||||
return str(self)
|
||||
return "artiq.compiler.types.TRPC({})".format(repr(self.ret))
|
||||
|
||||
def __eq__(self, other):
|
||||
return isinstance(other, TRPC) and \
|
||||
self.service == other.service and \
|
||||
self.is_async == other.is_async
|
||||
self.async == other.async
|
||||
|
||||
def __ne__(self, other):
|
||||
return not (self == other)
|
||||
|
|
@ -385,50 +351,6 @@ class TRPC(Type):
|
|||
def __hash__(self):
|
||||
return hash(self.service)
|
||||
|
||||
class TSubkernel(TFunction):
|
||||
"""
|
||||
A kernel to be run on a satellite.
|
||||
|
||||
:ivar args: (:class:`collections.OrderedDict` of string to :class:`Type`)
|
||||
function arguments
|
||||
:ivar ret: (:class:`Type`)
|
||||
return type
|
||||
:ivar sid: (int) subkernel ID number
|
||||
:ivar destination: (int) satellite destination number
|
||||
"""
|
||||
|
||||
attributes = OrderedDict()
|
||||
|
||||
def __init__(self, args, optargs, ret, sid, destination):
|
||||
assert isinstance(ret, Type)
|
||||
super().__init__(args, optargs, ret)
|
||||
self.sid, self.destination = sid, destination
|
||||
self.delay = TFixedDelay(iodelay.Const(0))
|
||||
|
||||
def unify(self, other):
|
||||
if other is self:
|
||||
return
|
||||
if isinstance(other, TSubkernel) and \
|
||||
self.sid == other.sid and \
|
||||
self.destination == other.destination:
|
||||
self.ret.unify(other.ret)
|
||||
elif isinstance(other, TVar):
|
||||
other.unify(self)
|
||||
else:
|
||||
raise UnificationError(self, other)
|
||||
|
||||
def __repr__(self):
|
||||
if getattr(builtins, "__in_sphinx__", False):
|
||||
return str(self)
|
||||
return "artiq.compiler.types.TSubkernel({})".format(repr(self.ret))
|
||||
|
||||
def __eq__(self, other):
|
||||
return isinstance(other, TSubkernel) and \
|
||||
self.sid == other.sid
|
||||
|
||||
def __hash__(self):
|
||||
return hash(self.sid)
|
||||
|
||||
class TBuiltin(Type):
|
||||
"""
|
||||
An instance of builtin type. Every instance of a builtin
|
||||
|
|
@ -444,8 +366,6 @@ class TBuiltin(Type):
|
|||
return self
|
||||
|
||||
def unify(self, other):
|
||||
if other is self:
|
||||
return
|
||||
if self != other:
|
||||
raise UnificationError(self, other)
|
||||
|
||||
|
|
@ -453,8 +373,6 @@ class TBuiltin(Type):
|
|||
return fn(accum, self)
|
||||
|
||||
def __repr__(self):
|
||||
if getattr(builtins, "__in_sphinx__", False):
|
||||
return str(self)
|
||||
return "artiq.compiler.types.{}({})".format(type(self).__name__, repr(self.name))
|
||||
|
||||
def __eq__(self, other):
|
||||
|
|
@ -470,11 +388,6 @@ class TBuiltin(Type):
|
|||
class TBuiltinFunction(TBuiltin):
|
||||
"""
|
||||
A type of a builtin function.
|
||||
|
||||
Builtin functions are treated specially throughout all stages of the
|
||||
compilation process according to their name (e.g. calls may not actually
|
||||
lower to a function call). See :class:`TExternalFunction` for externally
|
||||
defined functions that are otherwise regular.
|
||||
"""
|
||||
|
||||
class TConstructor(TBuiltin):
|
||||
|
|
@ -515,8 +428,6 @@ class TInstance(TMono):
|
|||
self.constant_attributes = set()
|
||||
|
||||
def __repr__(self):
|
||||
if getattr(builtins, "__in_sphinx__", False):
|
||||
return str(self)
|
||||
return "artiq.compiler.types.TInstance({}, {})".format(
|
||||
repr(self.name), repr(self.attributes))
|
||||
|
||||
|
|
@ -532,8 +443,6 @@ class TModule(TMono):
|
|||
self.constant_attributes = set()
|
||||
|
||||
def __repr__(self):
|
||||
if getattr(builtins, "__in_sphinx__", False):
|
||||
return str(self)
|
||||
return "artiq.compiler.types.TModule({}, {})".format(
|
||||
repr(self.name), repr(self.attributes))
|
||||
|
||||
|
|
@ -562,8 +471,6 @@ class TValue(Type):
|
|||
return self
|
||||
|
||||
def unify(self, other):
|
||||
if other is self:
|
||||
return
|
||||
if isinstance(other, TVar):
|
||||
other.unify(self)
|
||||
elif self != other:
|
||||
|
|
@ -573,8 +480,6 @@ class TValue(Type):
|
|||
return fn(accum, self)
|
||||
|
||||
def __repr__(self):
|
||||
if getattr(builtins, "__in_sphinx__", False):
|
||||
return str(self)
|
||||
return "artiq.compiler.types.TValue(%s)" % repr(self.value)
|
||||
|
||||
def __eq__(self, other):
|
||||
|
|
@ -633,8 +538,6 @@ class TDelay(Type):
|
|||
return not (self == other)
|
||||
|
||||
def __repr__(self):
|
||||
if getattr(builtins, "__in_sphinx__", False):
|
||||
return str(self)
|
||||
if self.duration is None:
|
||||
return "<{}.TIndeterminateDelay>".format(__name__)
|
||||
elif self.cause is None:
|
||||
|
|
@ -658,15 +561,13 @@ def is_mono(typ, name=None, **params):
|
|||
if not isinstance(typ, TMono):
|
||||
return False
|
||||
|
||||
if name is not None and typ.name != name:
|
||||
return False
|
||||
|
||||
params_match = True
|
||||
for param in params:
|
||||
if param not in typ.params:
|
||||
return False
|
||||
if typ.params[param].find() != params[param].find():
|
||||
return False
|
||||
return True
|
||||
params_match = params_match and \
|
||||
typ.params[param].find() == params[param].find()
|
||||
return name is None or (typ.name == name and params_match)
|
||||
|
||||
def is_polymorphic(typ):
|
||||
return typ.fold(False, lambda accum, typ: accum or is_var(typ))
|
||||
|
|
@ -688,15 +589,12 @@ def is_function(typ):
|
|||
def is_rpc(typ):
|
||||
return isinstance(typ.find(), TRPC)
|
||||
|
||||
def is_subkernel(typ):
|
||||
return isinstance(typ.find(), TSubkernel)
|
||||
|
||||
def is_external_function(typ, name=None):
|
||||
def is_c_function(typ, name=None):
|
||||
typ = typ.find()
|
||||
if name is None:
|
||||
return isinstance(typ, TExternalFunction)
|
||||
return isinstance(typ, TCFunction)
|
||||
else:
|
||||
return isinstance(typ, TExternalFunction) and \
|
||||
return isinstance(typ, TCFunction) and \
|
||||
typ.name == name
|
||||
|
||||
def is_builtin(typ, name=None):
|
||||
|
|
@ -715,15 +613,6 @@ def is_builtin_function(typ, name=None):
|
|||
return isinstance(typ, TBuiltinFunction) and \
|
||||
typ.name == name
|
||||
|
||||
def is_broadcast_across_arrays(typ):
|
||||
# For now, broadcasting is only exposed to predefined external functions, and
|
||||
# statically selected. Might be extended to user-defined functions if the design
|
||||
# pans out.
|
||||
typ = typ.find()
|
||||
if not isinstance(typ, TExternalFunction):
|
||||
return False
|
||||
return typ.broadcast_across_arrays
|
||||
|
||||
def is_constructor(typ, name=None):
|
||||
typ = typ.find()
|
||||
if name is not None:
|
||||
|
|
@ -828,14 +717,12 @@ class TypePrinter(object):
|
|||
else:
|
||||
return "%s(%s)" % (typ.name, ", ".join(
|
||||
["%s=%s" % (k, self.name(typ.params[k], depth + 1)) for k in typ.params]))
|
||||
elif isinstance(typ, _TPointer):
|
||||
return "{}*".format(self.name(typ["elt"], depth + 1))
|
||||
elif isinstance(typ, TTuple):
|
||||
if len(typ.elts) == 1:
|
||||
return "(%s,)" % self.name(typ.elts[0], depth + 1)
|
||||
else:
|
||||
return "(%s)" % ", ".join([self.name(typ, depth + 1) for typ in typ.elts])
|
||||
elif isinstance(typ, (TFunction, TExternalFunction)):
|
||||
elif isinstance(typ, (TFunction, TCFunction)):
|
||||
args = []
|
||||
args += [ "%s:%s" % (arg, self.name(typ.args[arg], depth + 1))
|
||||
for arg in typ.args]
|
||||
|
|
@ -849,18 +736,14 @@ class TypePrinter(object):
|
|||
elif not (delay.is_fixed() and iodelay.is_zero(delay.duration)):
|
||||
signature += " " + self.name(delay, depth + 1)
|
||||
|
||||
if isinstance(typ, TExternalFunction):
|
||||
if isinstance(typ, TCFunction):
|
||||
return "[ffi {}]{}".format(repr(typ.name), signature)
|
||||
elif isinstance(typ, TFunction):
|
||||
return signature
|
||||
elif isinstance(typ, TRPC):
|
||||
return "[rpc{} #{}](...)->{}".format(typ.service,
|
||||
" async" if typ.is_async else "",
|
||||
" async" if typ.async else "",
|
||||
self.name(typ.ret, depth + 1))
|
||||
elif isinstance(typ, TSubkernel):
|
||||
return "<subkernel{} dest#{}>->{}".format(typ.sid,
|
||||
typ.destination,
|
||||
self.name(typ.ret, depth + 1))
|
||||
elif isinstance(typ, TBuiltinFunction):
|
||||
return "<function {}>".format(typ.name)
|
||||
elif isinstance(typ, (TConstructor, TExceptionConstructor)):
|
||||
|
|
|
|||
|
|
@ -50,9 +50,3 @@ class ConstnessValidator(algorithm.Visitor):
|
|||
node.loc)
|
||||
self.engine.process(diag)
|
||||
return
|
||||
if builtins.is_array(typ):
|
||||
diag = diagnostic.Diagnostic("error",
|
||||
"array attributes cannot be assigned to",
|
||||
{}, node.loc)
|
||||
self.engine.process(diag)
|
||||
return
|
||||
|
|
|
|||
|
|
@ -51,6 +51,10 @@ class Region:
|
|||
(other.range.begin_pos <= self.range.begin_pos <= other.range.end_pos and \
|
||||
self.range.end_pos > other.range.end_pos)
|
||||
|
||||
def contract(self, other):
|
||||
if not self.range:
|
||||
self.range = other.range
|
||||
|
||||
def outlives(lhs, rhs):
|
||||
if not isinstance(lhs, Region): # lhs lives nonlexically
|
||||
return True
|
||||
|
|
@ -65,11 +69,8 @@ class Region:
|
|||
|
||||
class RegionOf(algorithm.Visitor):
|
||||
"""
|
||||
Visit an expression and return the region that must be alive for the
|
||||
expression to execute.
|
||||
|
||||
For expressions involving multiple regions, the shortest-lived one is
|
||||
returned.
|
||||
Visit an expression and return the list of regions that must
|
||||
be alive for the expression to execute.
|
||||
"""
|
||||
|
||||
def __init__(self, env_stack, youngest_region):
|
||||
|
|
@ -99,23 +100,11 @@ class RegionOf(algorithm.Visitor):
|
|||
visit_BinOpT = visit_sometimes_allocating
|
||||
|
||||
def visit_CallT(self, node):
|
||||
if types.is_external_function(node.func.type, "cache_get"):
|
||||
if types.is_c_function(node.func.type, "cache_get"):
|
||||
# The cache is borrow checked dynamically
|
||||
return Global()
|
||||
|
||||
if (types.is_builtin_function(node.func.type, "array")
|
||||
or types.is_builtin_function(node.func.type, "make_array")
|
||||
or types.is_builtin_function(node.func.type, "numpy.transpose")):
|
||||
# While lifetime tracking across function calls in general is currently
|
||||
# broken (see below), these special builtins that allocate an array on
|
||||
# the stack of the caller _always_ allocate regardless of the parameters,
|
||||
# and we can thus handle them without running into the precision issue
|
||||
# mentioned in commit ae999db.
|
||||
return self.visit_allocating(node)
|
||||
|
||||
# FIXME: Return statement missing here, but see m-labs/artiq#1497 and
|
||||
# commit ae999db.
|
||||
self.visit_sometimes_allocating(node)
|
||||
else:
|
||||
self.visit_sometimes_allocating(node)
|
||||
|
||||
# Value lives as long as the object/container, if it's mutable,
|
||||
# or else forever
|
||||
|
|
@ -168,7 +157,7 @@ class RegionOf(algorithm.Visitor):
|
|||
visit_NameConstantT = visit_immutable
|
||||
visit_NumT = visit_immutable
|
||||
visit_EllipsisT = visit_immutable
|
||||
visit_UnaryOpT = visit_sometimes_allocating # possibly array op
|
||||
visit_UnaryOpT = visit_immutable
|
||||
visit_CompareT = visit_immutable
|
||||
|
||||
# Value lives forever
|
||||
|
|
@ -312,20 +301,17 @@ class EscapeValidator(algorithm.Visitor):
|
|||
def visit_assignment(self, target, value):
|
||||
value_region = self._region_of(value)
|
||||
|
||||
# If this is a variable, we might need to contract the live range.
|
||||
if isinstance(value_region, Region):
|
||||
for name in self._names_of(target):
|
||||
region = self._region_of(name)
|
||||
if isinstance(region, Region):
|
||||
region.contract(value_region)
|
||||
|
||||
# If we assign to an attribute of a quoted value, there will be no names
|
||||
# in the assignment lhs.
|
||||
target_names = self._names_of(target) or []
|
||||
|
||||
# Adopt the value region for any variables declared on the lhs.
|
||||
for name in target_names:
|
||||
region = self._region_of(name)
|
||||
if isinstance(region, Region) and not region.present():
|
||||
# Find the name's environment to overwrite the region.
|
||||
for env in self.env_stack[::-1]:
|
||||
if name.id in env:
|
||||
env[name.id] = value_region
|
||||
break
|
||||
|
||||
# The assigned value should outlive the assignee
|
||||
target_regions = [self._region_of(name) for name in target_names]
|
||||
for target_region in target_regions:
|
||||
|
|
|
|||
|
|
@ -80,30 +80,21 @@ def ad53xx_cmd_read_ch(channel, op):
|
|||
return AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_READ | (op + (channel << 7))
|
||||
|
||||
|
||||
# maintain function definition for backward compatibility
|
||||
@portable
|
||||
def voltage_to_mu(voltage, offset_dacs=0x2000, vref=5.):
|
||||
"""Returns the 16-bit DAC register value required to produce a given output
|
||||
"""Returns the DAC register value required to produce a given output
|
||||
voltage, assuming offset and gain errors have been trimmed out.
|
||||
|
||||
The 16-bit register value may also be used with 14-bit DACs. The additional
|
||||
bits are disregarded by 14-bit DACs.
|
||||
|
||||
Also used to return offset register value required to produce a given
|
||||
voltage when the DAC register is set to mid-scale.
|
||||
An offset of V can be used to trim out a DAC offset error of -V.
|
||||
|
||||
:param voltage: Voltage in SI units.
|
||||
Valid voltages are: [-2*vref, + 2*vref - 1 LSB] + voltage offset.
|
||||
:param voltage: Voltage
|
||||
:param offset_dacs: Register value for the two offset DACs
|
||||
(default: 0x2000)
|
||||
:param vref: DAC reference voltage (default: 5.)
|
||||
:return: The 16-bit DAC register value
|
||||
"""
|
||||
code = int(round((1 << 16) * (voltage / (4. * vref)) + offset_dacs * 0x4))
|
||||
if code < 0x0 or code > 0xffff:
|
||||
raise ValueError("Invalid DAC voltage!")
|
||||
return code
|
||||
return int(round(0x10000*(voltage/(4.*vref)) + offset_dacs*0x4))
|
||||
|
||||
|
||||
class _DummyTTL:
|
||||
|
|
@ -127,9 +118,9 @@ class AD53xx:
|
|||
transactions (default: 1)
|
||||
:param div_write: SPI clock divider for write operations (default: 4,
|
||||
50MHz max SPI clock with {t_high, t_low} >=8ns)
|
||||
:param div_read: SPI clock divider for read operations (default: 16, not
|
||||
optimized for speed; datasheet says t22: 25ns min SCLK edge to SDO
|
||||
valid, and suggests the SPI speed for reads should be <=20 MHz)
|
||||
:param div_read: SPI clock divider for read operations (default: 8, not
|
||||
optimized for speed, but cf data sheet t22: 25ns min SCLK edge to SDO
|
||||
valid)
|
||||
:param vref: DAC reference voltage (default: 5.)
|
||||
:param offset_dacs: Initial register value for the two offset DACs, device
|
||||
dependent and must be set correctly for correct voltage to mu
|
||||
|
|
@ -178,16 +169,14 @@ class AD53xx:
|
|||
self.write_offset_dacs_mu(self.offset_dacs)
|
||||
if not blind:
|
||||
ctrl = self.read_reg(channel=0, op=AD53XX_READ_CONTROL)
|
||||
if ctrl == 0xffff:
|
||||
raise ValueError("DAC not found")
|
||||
if ctrl & 0b10000:
|
||||
raise ValueError("DAC over temperature")
|
||||
delay(25*us)
|
||||
delay(15*us)
|
||||
self.bus.write( # enable power and overtemperature shutdown
|
||||
(AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_CONTROL | 0b0010) << 8)
|
||||
if not blind:
|
||||
ctrl = self.read_reg(channel=0, op=AD53XX_READ_CONTROL)
|
||||
if (ctrl & 0b10111) != 0b00010:
|
||||
if ctrl != 0b0010:
|
||||
raise ValueError("DAC CONTROL readback mismatch")
|
||||
delay(15*us)
|
||||
|
||||
|
|
@ -233,7 +222,7 @@ class AD53xx:
|
|||
def write_gain_mu(self, channel, gain=0xffff):
|
||||
"""Program the gain register for a DAC channel.
|
||||
|
||||
The DAC output is not updated until LDAC is pulsed (see :meth:`load`).
|
||||
The DAC output is not updated until LDAC is pulsed (see :meth load:).
|
||||
This method advances the timeline by the duration of one SPI transfer.
|
||||
|
||||
:param gain: 16-bit gain register value (default: 0xffff)
|
||||
|
|
@ -245,7 +234,7 @@ class AD53xx:
|
|||
def write_offset_mu(self, channel, offset=0x8000):
|
||||
"""Program the offset register for a DAC channel.
|
||||
|
||||
The DAC output is not updated until LDAC is pulsed (see :meth:`load`).
|
||||
The DAC output is not updated until LDAC is pulsed (see :meth load:).
|
||||
This method advances the timeline by the duration of one SPI transfer.
|
||||
|
||||
:param offset: 16-bit offset register value (default: 0x8000)
|
||||
|
|
@ -258,7 +247,7 @@ class AD53xx:
|
|||
"""Program the DAC offset voltage for a channel.
|
||||
|
||||
An offset of +V can be used to trim out a DAC offset error of -V.
|
||||
The DAC output is not updated until LDAC is pulsed (see :meth:`load`).
|
||||
The DAC output is not updated until LDAC is pulsed (see :meth load:).
|
||||
This method advances the timeline by the duration of one SPI transfer.
|
||||
|
||||
:param voltage: the offset voltage
|
||||
|
|
@ -270,7 +259,7 @@ class AD53xx:
|
|||
def write_dac_mu(self, channel, value):
|
||||
"""Program the DAC input register for a channel.
|
||||
|
||||
The DAC output is not updated until LDAC is pulsed (see :meth:`load`).
|
||||
The DAC output is not updated until LDAC is pulsed (see :meth load:).
|
||||
This method advances the timeline by the duration of one SPI transfer.
|
||||
"""
|
||||
self.bus.write(
|
||||
|
|
@ -280,7 +269,7 @@ class AD53xx:
|
|||
def write_dac(self, channel, voltage):
|
||||
"""Program the DAC output voltage for a channel.
|
||||
|
||||
The DAC output is not updated until LDAC is pulsed (see :meth:`load`).
|
||||
The DAC output is not updated until LDAC is pulsed (see :meth load:).
|
||||
This method advances the timeline by the duration of one SPI transfer.
|
||||
"""
|
||||
self.write_dac_mu(channel, voltage_to_mu(voltage, self.offset_dacs,
|
||||
|
|
@ -313,7 +302,7 @@ class AD53xx:
|
|||
|
||||
If no LDAC device was defined, the LDAC pulse is skipped.
|
||||
|
||||
See :meth:`load`.
|
||||
See :meth load:.
|
||||
|
||||
:param values: list of DAC values to program
|
||||
:param channels: list of DAC channels to program. If not specified,
|
||||
|
|
@ -355,7 +344,7 @@ class AD53xx:
|
|||
""" Two-point calibration of a DAC channel.
|
||||
|
||||
Programs the offset and gain register to trim out DAC errors. Does not
|
||||
take effect until LDAC is pulsed (see :meth:`load`).
|
||||
take effect until LDAC is pulsed (see :meth load:).
|
||||
|
||||
Calibration consists of measuring the DAC output voltage for a channel
|
||||
with the DAC set to zero-scale (0x0000) and full-scale (0xffff).
|
||||
|
|
@ -377,17 +366,3 @@ class AD53xx:
|
|||
self.core.break_realtime()
|
||||
self.write_offset_mu(channel, 0x8000-offset_err)
|
||||
self.write_gain_mu(channel, 0xffff-gain_err)
|
||||
|
||||
@portable
|
||||
def voltage_to_mu(self, voltage):
|
||||
"""Returns the 16-bit DAC register value required to produce a given
|
||||
output voltage, assuming offset and gain errors have been trimmed out.
|
||||
|
||||
The 16-bit register value may also be used with 14-bit DACs. The
|
||||
additional bits are disregarded by 14-bit DACs.
|
||||
|
||||
:param voltage: Voltage in SI units.
|
||||
Valid voltages are: [-2*vref, + 2*vref - 1 LSB] + voltage offset.
|
||||
:return: The 16-bit DAC register value
|
||||
"""
|
||||
return voltage_to_mu(voltage, self.offset_dacs, self.vref)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,23 @@
|
|||
from artiq.language.core import kernel
|
||||
|
||||
|
||||
class AD9154:
|
||||
"""Kernel interface to AD9154 registers, using non-realtime SPI."""
|
||||
|
||||
def __init__(self, dmgr, spi_device, chip_select):
|
||||
self.core = dmgr.get("core")
|
||||
self.bus = dmgr.get(spi_device)
|
||||
self.chip_select = chip_select
|
||||
|
||||
@kernel
|
||||
def setup_bus(self, div=16):
|
||||
self.bus.set_config_mu(0, 24, div, self.chip_select)
|
||||
|
||||
@kernel
|
||||
def write(self, addr, data):
|
||||
self.bus.write((addr << 16) | (data<< 8))
|
||||
|
||||
@kernel
|
||||
def read(self, addr):
|
||||
self.write((1 << 15) | addr, 0)
|
||||
return self.bus.read()
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,8 +1,7 @@
|
|||
from numpy import int32, int64
|
||||
|
||||
from artiq.language.types import TInt32, TInt64, TFloat, TTuple, TBool
|
||||
from artiq.language.core import kernel, delay, portable
|
||||
from artiq.language.units import ms, us, ns
|
||||
from artiq.language.units import us, ns
|
||||
from artiq.coredevice.ad9912_reg import *
|
||||
|
||||
from artiq.coredevice import spi2 as spi
|
||||
|
|
@ -22,17 +21,14 @@ class AD9912:
|
|||
:param sw_device: Name of the RF switch device. The RF switch is a
|
||||
TTLOut channel available as the :attr:`sw` attribute of this instance.
|
||||
:param pll_n: DDS PLL multiplier. The DDS sample clock is
|
||||
f_ref/clk_div*pll_n where f_ref is the reference frequency and clk_div
|
||||
is the reference clock divider (both set in the parent Urukul CPLD
|
||||
instance).
|
||||
:param pll_en: PLL enable bit, set to 0 to bypass PLL (default: 1).
|
||||
Note that when bypassing the PLL the red front panel LED may remain on.
|
||||
f_ref*pll_n where f_ref is the reference frequency (set in the parent
|
||||
Urukul CPLD instance).
|
||||
"""
|
||||
kernel_invariants = {"chip_select", "cpld", "core", "bus",
|
||||
"ftw_per_hz", "sysclk", "pll_n"}
|
||||
|
||||
def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
|
||||
pll_n=10, pll_en=1):
|
||||
self.kernel_invariants = {"cpld", "core", "bus", "chip_select",
|
||||
"pll_n", "pll_en", "ftw_per_hz"}
|
||||
pll_n=10):
|
||||
self.cpld = dmgr.get(cpld_device)
|
||||
self.core = self.cpld.core
|
||||
self.bus = self.cpld.bus
|
||||
|
|
@ -41,17 +37,13 @@ class AD9912:
|
|||
if sw_device:
|
||||
self.sw = dmgr.get(sw_device)
|
||||
self.kernel_invariants.add("sw")
|
||||
self.pll_en = pll_en
|
||||
self.pll_n = pll_n
|
||||
if pll_en:
|
||||
sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n
|
||||
else:
|
||||
sysclk = self.cpld.refclk
|
||||
assert sysclk <= 1e9
|
||||
self.ftw_per_hz = 1 / sysclk * (int64(1) << 48)
|
||||
self.sysclk = self.cpld.refclk*pll_n
|
||||
assert self.sysclk <= 1e9
|
||||
self.ftw_per_hz = 1/self.sysclk*(int64(1) << 48)
|
||||
|
||||
@kernel
|
||||
def write(self, addr: TInt32, data: TInt32, length: TInt32):
|
||||
def write(self, addr, data, length):
|
||||
"""Variable length write to a register.
|
||||
Up to 4 bytes.
|
||||
|
||||
|
|
@ -62,14 +54,14 @@ class AD9912:
|
|||
assert length > 0
|
||||
assert length <= 4
|
||||
self.bus.set_config_mu(urukul.SPI_CONFIG, 16,
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
self.bus.write((addr | ((length - 1) << 13)) << 16)
|
||||
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, length * 8,
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
self.bus.write(data << (32 - length * 8))
|
||||
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, length*8,
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
self.bus.write(data << (32 - length*8))
|
||||
|
||||
@kernel
|
||||
def read(self, addr: TInt32, length: TInt32) -> TInt32:
|
||||
def read(self, addr, length):
|
||||
"""Variable length read from a register.
|
||||
Up to 4 bytes.
|
||||
|
||||
|
|
@ -80,15 +72,15 @@ class AD9912:
|
|||
assert length > 0
|
||||
assert length <= 4
|
||||
self.bus.set_config_mu(urukul.SPI_CONFIG, 16,
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
self.bus.write((addr | ((length - 1) << 13) | 0x8000) << 16)
|
||||
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END
|
||||
| spi.SPI_INPUT, length * 8,
|
||||
urukul.SPIT_DDS_RD, self.chip_select)
|
||||
| spi.SPI_INPUT, length*8,
|
||||
urukul.SPIT_DDS_RD, self.chip_select)
|
||||
self.bus.write(0)
|
||||
data = self.bus.read()
|
||||
if length < 4:
|
||||
data &= (1 << (length * 8)) - 1
|
||||
data &= (1 << (length*8)) - 1
|
||||
return data
|
||||
|
||||
@kernel
|
||||
|
|
@ -101,30 +93,25 @@ class AD9912:
|
|||
"""
|
||||
# SPI mode
|
||||
self.write(AD9912_SER_CONF, 0x99, length=1)
|
||||
self.cpld.io_update.pulse(2 * us)
|
||||
self.cpld.io_update.pulse(2*us)
|
||||
# Verify chip ID and presence
|
||||
prodid = self.read(AD9912_PRODIDH, length=2)
|
||||
if (prodid != 0x1982) and (prodid != 0x1902):
|
||||
raise ValueError("Urukul AD9912 product id mismatch")
|
||||
delay(50 * us)
|
||||
delay(50*us)
|
||||
# HSTL power down, CMOS power down
|
||||
pwrcntrl1 = 0x80 | ((~self.pll_en & 1) << 4)
|
||||
self.write(AD9912_PWRCNTRL1, pwrcntrl1, length=1)
|
||||
self.cpld.io_update.pulse(2 * us)
|
||||
if self.pll_en:
|
||||
self.write(AD9912_N_DIV, self.pll_n // 2 - 2, length=1)
|
||||
self.cpld.io_update.pulse(2 * us)
|
||||
# I_cp = 375 µA, VCO high range
|
||||
self.write(AD9912_PLLCFG, 0b00000101, length=1)
|
||||
self.cpld.io_update.pulse(2 * us)
|
||||
delay(1 * ms)
|
||||
self.write(AD9912_PWRCNTRL1, 0x80, length=1)
|
||||
self.cpld.io_update.pulse(2*us)
|
||||
self.write(AD9912_N_DIV, self.pll_n//2 - 2, length=1)
|
||||
self.cpld.io_update.pulse(2*us)
|
||||
# I_cp = 375 µA, VCO high range
|
||||
self.write(AD9912_PLLCFG, 0b00000101, length=1)
|
||||
self.cpld.io_update.pulse(2*us)
|
||||
|
||||
@kernel
|
||||
def set_att_mu(self, att: TInt32):
|
||||
def set_att_mu(self, att):
|
||||
"""Set digital step attenuator in machine units.
|
||||
|
||||
This method will write the attenuator settings of all four channels.
|
||||
|
||||
.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.set_att_mu`
|
||||
|
||||
:param att: Attenuation setting, 8 bit digital.
|
||||
|
|
@ -132,11 +119,9 @@ class AD9912:
|
|||
self.cpld.set_att_mu(self.chip_select - 4, att)
|
||||
|
||||
@kernel
|
||||
def set_att(self, att: TFloat):
|
||||
def set_att(self, att):
|
||||
"""Set digital step attenuator in SI units.
|
||||
|
||||
This method will write the attenuator settings of all four channels.
|
||||
|
||||
.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.set_att`
|
||||
|
||||
:param att: Attenuation in dB. Higher values mean more attenuation.
|
||||
|
|
@ -144,129 +129,56 @@ class AD9912:
|
|||
self.cpld.set_att(self.chip_select - 4, att)
|
||||
|
||||
@kernel
|
||||
def get_att_mu(self) -> TInt32:
|
||||
"""Get digital step attenuator value in machine units.
|
||||
|
||||
.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.get_channel_att_mu`
|
||||
|
||||
:return: Attenuation setting, 8 bit digital.
|
||||
"""
|
||||
return self.cpld.get_channel_att_mu(self.chip_select - 4)
|
||||
|
||||
@kernel
|
||||
def get_att(self) -> TFloat:
|
||||
"""Get digital step attenuator value in SI units.
|
||||
|
||||
.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.get_channel_att`
|
||||
|
||||
:return: Attenuation in dB.
|
||||
"""
|
||||
return self.cpld.get_channel_att(self.chip_select - 4)
|
||||
|
||||
@kernel
|
||||
def set_mu(self, ftw: TInt64, pow_: TInt32 = 0):
|
||||
def set_mu(self, ftw, pow):
|
||||
"""Set profile 0 data in machine units.
|
||||
|
||||
After the SPI transfer, the shared IO update pin is pulsed to
|
||||
activate the data.
|
||||
|
||||
:param ftw: Frequency tuning word: 48 bit unsigned.
|
||||
:param pow_: Phase tuning word: 16 bit unsigned.
|
||||
:param ftw: Frequency tuning word: 32 bit unsigned.
|
||||
:param pow: Phase tuning word: 16 bit unsigned.
|
||||
"""
|
||||
# streaming transfer of FTW and POW
|
||||
self.bus.set_config_mu(urukul.SPI_CONFIG, 16,
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
self.bus.write((AD9912_POW1 << 16) | (3 << 29))
|
||||
self.bus.set_config_mu(urukul.SPI_CONFIG, 32,
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
self.bus.write((pow_ << 16) | (int32(ftw >> 32) & 0xffff))
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
self.bus.write((pow << 16) | (int32(ftw >> 32) & 0xffff))
|
||||
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
urukul.SPIT_DDS_WR, self.chip_select)
|
||||
self.bus.write(int32(ftw))
|
||||
self.cpld.io_update.pulse(10 * ns)
|
||||
|
||||
@kernel
|
||||
def get_mu(self) -> TTuple([TInt64, TInt32]):
|
||||
"""Get the frequency tuning word and phase offset word.
|
||||
|
||||
.. seealso:: :meth:`get`
|
||||
|
||||
:return: A tuple ``(ftw, pow)``.
|
||||
"""
|
||||
|
||||
# Read data
|
||||
high = self.read(AD9912_POW1, 4)
|
||||
self.core.break_realtime() # Regain slack to perform second read
|
||||
low = self.read(AD9912_FTW3, 4)
|
||||
# Extract and return fields
|
||||
ftw = (int64(high & 0xffff) << 32) | (int64(low) & int64(0xffffffff))
|
||||
pow_ = (high >> 16) & 0x3fff
|
||||
return ftw, pow_
|
||||
self.cpld.io_update.pulse(10*ns)
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def frequency_to_ftw(self, frequency: TFloat) -> TInt64:
|
||||
"""Returns the 48-bit frequency tuning word corresponding to the given
|
||||
def frequency_to_ftw(self, frequency):
|
||||
"""Returns the frequency tuning word corresponding to the given
|
||||
frequency.
|
||||
"""
|
||||
return int64(round(self.ftw_per_hz * frequency)) & (
|
||||
(int64(1) << 48) - 1)
|
||||
return int64(round(self.ftw_per_hz*frequency))
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def ftw_to_frequency(self, ftw: TInt64) -> TFloat:
|
||||
def ftw_to_frequency(self, ftw):
|
||||
"""Returns the frequency corresponding to the given
|
||||
frequency tuning word.
|
||||
"""
|
||||
return ftw / self.ftw_per_hz
|
||||
return ftw/self.ftw_per_hz
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def turns_to_pow(self, phase: TFloat) -> TInt32:
|
||||
"""Returns the 16-bit phase offset word corresponding to the given
|
||||
def turns_to_pow(self, phase):
|
||||
"""Returns the phase offset word corresponding to the given
|
||||
phase.
|
||||
"""
|
||||
return int32(round((1 << 14) * phase)) & 0xffff
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def pow_to_turns(self, pow_: TInt32) -> TFloat:
|
||||
"""Return the phase in turns corresponding to a given phase offset
|
||||
word.
|
||||
|
||||
:param pow_: Phase offset word.
|
||||
:return: Phase in turns.
|
||||
"""
|
||||
return pow_ / (1 << 14)
|
||||
return int32(round((1 << 16)*phase))
|
||||
|
||||
@kernel
|
||||
def set(self, frequency: TFloat, phase: TFloat = 0.0):
|
||||
def set(self, frequency, phase=0.0):
|
||||
"""Set profile 0 data in SI units.
|
||||
|
||||
.. seealso:: :meth:`set_mu`
|
||||
|
||||
:param frequency: Frequency in Hz
|
||||
:param phase: Phase tuning word in turns
|
||||
:param ftw: Frequency in Hz
|
||||
:param pow: Phase tuning word in turns
|
||||
"""
|
||||
self.set_mu(self.frequency_to_ftw(frequency),
|
||||
self.turns_to_pow(phase))
|
||||
|
||||
@kernel
|
||||
def get(self) -> TTuple([TFloat, TFloat]):
|
||||
"""Get the frequency and phase.
|
||||
|
||||
.. seealso:: :meth:`get_mu`
|
||||
|
||||
:return: A tuple ``(frequency, phase)``.
|
||||
"""
|
||||
|
||||
# Get values
|
||||
ftw, pow_ = self.get_mu()
|
||||
# Convert and return
|
||||
return self.ftw_to_frequency(ftw), self.pow_to_turns(pow_)
|
||||
|
||||
@kernel
|
||||
def cfg_sw(self, state: TBool):
|
||||
"""Set CPLD CFG RF switch state. The RF switch is controlled by the
|
||||
logical or of the CPLD configuration shift register
|
||||
RF switch bit and the SW TTL line (if used).
|
||||
|
||||
:param state: CPLD CFG RF switch bit
|
||||
"""
|
||||
self.cpld.cfg_sw(self.chip_select - 4, state)
|
||||
self.turns_to_pow(phase))
|
||||
|
|
|
|||
|
|
@ -80,16 +80,11 @@ class AD9914:
|
|||
self.set_x_duration_mu = 7 * self.write_duration_mu
|
||||
self.exit_x_duration_mu = 3 * self.write_duration_mu
|
||||
|
||||
@staticmethod
|
||||
def get_rtio_channels(bus_channel, channel, **kwargs):
|
||||
# return only first entry, as there are several devices with the same RTIO channel
|
||||
if channel == 0:
|
||||
return [(bus_channel, None)]
|
||||
return []
|
||||
self.continuous_phase_comp = 0
|
||||
|
||||
@kernel
|
||||
def write(self, addr, data):
|
||||
rtio_output((self.bus_channel << 8) | addr, data)
|
||||
rtio_output(now_mu(), self.bus_channel, addr, data)
|
||||
delay_mu(self.write_duration_mu)
|
||||
|
||||
@kernel
|
||||
|
|
@ -167,29 +162,25 @@ class AD9914:
|
|||
def set_phase_mode(self, phase_mode):
|
||||
"""Sets the phase mode of the DDS channel. Supported phase modes are:
|
||||
|
||||
* :const:`PHASE_MODE_CONTINUOUS`: the phase accumulator is unchanged when
|
||||
* ``PHASE_MODE_CONTINUOUS``: the phase accumulator is unchanged when
|
||||
switching frequencies. The DDS phase is the sum of the phase
|
||||
accumulator and the phase offset. The only discrete jumps in the
|
||||
DDS output phase come from changes to the phase offset.
|
||||
|
||||
* :const:`PHASE_MODE_ABSOLUTE`: the phase accumulator is reset when
|
||||
* ``PHASE_MODE_ABSOLUTE``: the phase accumulator is reset when
|
||||
switching frequencies. Thus, the phase of the DDS at the time of
|
||||
the frequency change is equal to the phase offset.
|
||||
|
||||
* :const:`PHASE_MODE_TRACKING`: when switching frequencies, the phase
|
||||
* ``PHASE_MODE_TRACKING``: when switching frequencies, the phase
|
||||
accumulator is set to the value it would have if the DDS had been
|
||||
running at the specified frequency since the start of the
|
||||
experiment.
|
||||
|
||||
.. warning:: This setting may become inconsistent when used as part of
|
||||
a DMA recording. When using DMA, it is recommended to specify the
|
||||
phase mode explicitly when calling :meth:`set` or :meth:`set_mu`.
|
||||
"""
|
||||
self.phase_mode = phase_mode
|
||||
|
||||
@kernel
|
||||
def set_mu(self, ftw, pow=0, phase_mode=_PHASE_MODE_DEFAULT,
|
||||
asf=0x0fff, ref_time_mu=-1):
|
||||
asf=0x0fff, ref_time=-1):
|
||||
"""Sets the DDS channel to the specified frequency and phase.
|
||||
|
||||
This uses machine units (FTW and POW). The frequency tuning word width
|
||||
|
|
@ -202,18 +193,15 @@ class AD9914:
|
|||
:param ftw: frequency to generate.
|
||||
:param pow: adds an offset to the phase.
|
||||
:param phase_mode: if specified, overrides the default phase mode set
|
||||
by :meth:`set_phase_mode` for this call.
|
||||
:param ref_time_mu: reference time used to compute phase. Specifying this
|
||||
by ``set_phase_mode`` for this call.
|
||||
:param ref_time: reference time used to compute phase. Specifying this
|
||||
makes it easier to have a well-defined phase relationship between
|
||||
DDSes on the same bus that are updated at a similar time.
|
||||
:return: Resulting phase offset word after application of phase
|
||||
tracking offset. When using :const:`PHASE_MODE_CONTINUOUS` in
|
||||
subsequent calls, use this value as the "current" phase.
|
||||
DDSes on the same bus that are updated at a similar time.
|
||||
"""
|
||||
if phase_mode == _PHASE_MODE_DEFAULT:
|
||||
phase_mode = self.phase_mode
|
||||
if ref_time_mu < 0:
|
||||
ref_time_mu = now_mu()
|
||||
if ref_time < 0:
|
||||
ref_time = now_mu()
|
||||
delay_mu(-self.set_duration_mu)
|
||||
|
||||
self.write(AD9914_GPIO, (1 << self.channel) << 1)
|
||||
|
|
@ -227,26 +215,27 @@ class AD9914:
|
|||
# Do not clear phase accumulator on FUD
|
||||
# Disable autoclear phase accumulator and enables OSK.
|
||||
self.write(AD9914_REG_CFR1L, 0x0108)
|
||||
pow += self.continuous_phase_comp
|
||||
else:
|
||||
# Clear phase accumulator on FUD
|
||||
# Enable autoclear phase accumulator and enables OSK.
|
||||
self.write(AD9914_REG_CFR1L, 0x2108)
|
||||
fud_time = now_mu() + 2 * self.write_duration_mu
|
||||
pow -= int32((ref_time_mu - fud_time) * self.sysclk_per_mu * ftw >> (32 - 16))
|
||||
pow -= int32((ref_time - fud_time) * self.sysclk_per_mu * ftw >> (32 - 16))
|
||||
if phase_mode == PHASE_MODE_TRACKING:
|
||||
pow += int32(ref_time_mu * self.sysclk_per_mu * ftw >> (32 - 16))
|
||||
pow += int32(ref_time * self.sysclk_per_mu * ftw >> (32 - 16))
|
||||
self.continuous_phase_comp = pow
|
||||
|
||||
self.write(AD9914_REG_POW, pow)
|
||||
self.write(AD9914_REG_ASF, asf)
|
||||
self.write(AD9914_FUD, 0)
|
||||
return pow
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def frequency_to_ftw(self, frequency):
|
||||
"""Returns the 32-bit frequency tuning word corresponding to the given
|
||||
"""Returns the frequency tuning word corresponding to the given
|
||||
frequency.
|
||||
"""
|
||||
return int32(round(float(int64(2)**32*frequency/self.sysclk)))
|
||||
return round(float(int64(2)**32*frequency/self.sysclk))
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def ftw_to_frequency(self, ftw):
|
||||
|
|
@ -257,9 +246,9 @@ class AD9914:
|
|||
|
||||
@portable(flags={"fast-math"})
|
||||
def turns_to_pow(self, turns):
|
||||
"""Returns the 16-bit phase offset word corresponding to the given
|
||||
phase in turns."""
|
||||
return round(float(turns*2**16)) & 0xffff
|
||||
"""Returns the phase offset word corresponding to the given phase
|
||||
in turns."""
|
||||
return round(float(turns*2**16))
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def pow_to_turns(self, pow):
|
||||
|
|
@ -269,12 +258,8 @@ class AD9914:
|
|||
|
||||
@portable(flags={"fast-math"})
|
||||
def amplitude_to_asf(self, amplitude):
|
||||
"""Returns 12-bit amplitude scale factor corresponding to given
|
||||
amplitude."""
|
||||
code = round(float(amplitude * 0x0fff))
|
||||
if code < 0 or code > 0xfff:
|
||||
raise ValueError("Invalid AD9914 amplitude!")
|
||||
return code
|
||||
"""Returns amplitude scale factor corresponding to given amplitude."""
|
||||
return round(float(amplitude*0x0fff))
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def asf_to_amplitude(self, asf):
|
||||
|
|
@ -285,11 +270,10 @@ class AD9914:
|
|||
@kernel
|
||||
def set(self, frequency, phase=0.0, phase_mode=_PHASE_MODE_DEFAULT,
|
||||
amplitude=1.0):
|
||||
"""Like :meth:`set_mu`, but uses Hz and turns."""
|
||||
return self.pow_to_turns(
|
||||
self.set_mu(self.frequency_to_ftw(frequency),
|
||||
"""Like ``set_mu``, but uses Hz and turns."""
|
||||
self.set_mu(self.frequency_to_ftw(frequency),
|
||||
self.turns_to_pow(phase), phase_mode,
|
||||
self.amplitude_to_asf(amplitude)))
|
||||
self.amplitude_to_asf(amplitude))
|
||||
|
||||
# Extended-resolution functions
|
||||
@kernel
|
||||
|
|
@ -325,11 +309,10 @@ class AD9914:
|
|||
|
||||
@portable(flags={"fast-math"})
|
||||
def frequency_to_xftw(self, frequency):
|
||||
"""Returns the 63-bit frequency tuning word corresponding to the given
|
||||
"""Returns the frequency tuning word corresponding to the given
|
||||
frequency (extended resolution mode).
|
||||
"""
|
||||
return int64(round(2.0*float(int64(2)**62)*frequency/self.sysclk)) & (
|
||||
(int64(1) << 63) - 1)
|
||||
return int64(round(2.0*float(int64(2)**62)*frequency/self.sysclk))
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def xftw_to_frequency(self, xftw):
|
||||
|
|
@ -340,7 +323,7 @@ class AD9914:
|
|||
|
||||
@kernel
|
||||
def set_x(self, frequency, amplitude=1.0):
|
||||
"""Like :meth:`set_x_mu`, but uses Hz and turns.
|
||||
"""Like ``set_x_mu``, but uses Hz and turns.
|
||||
|
||||
Note that the precision of ``float`` is less than the precision
|
||||
of the extended frequency tuning word.
|
||||
|
|
|
|||
|
|
@ -1,598 +0,0 @@
|
|||
"""RTIO driver for the Analog Devices ADF[45]35[56] family of GHz PLLs
|
||||
on Mirny-style prefixed SPI buses.
|
||||
"""
|
||||
|
||||
# https://github.com/analogdevicesinc/linux/blob/master/Documentation/devicetree/bindings/iio/frequency/adf5355.txt
|
||||
# https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/frequency/adf5355.c
|
||||
# https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5355.pdf
|
||||
# https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5355.pdf
|
||||
# https://www.analog.com/media/en/technical-documentation/user-guides/EV-ADF5355SD1Z-UG-1087.pdf
|
||||
|
||||
|
||||
from artiq.language.core import kernel, portable, delay
|
||||
from artiq.language.units import us, GHz, MHz
|
||||
from artiq.language.types import TInt32, TInt64
|
||||
from artiq.coredevice import spi2 as spi
|
||||
from artiq.coredevice.adf5356_reg import *
|
||||
|
||||
from numpy import int32, int64, floor, ceil
|
||||
|
||||
|
||||
SPI_CONFIG = (
|
||||
0 * spi.SPI_OFFLINE
|
||||
| 0 * spi.SPI_END
|
||||
| 0 * spi.SPI_INPUT
|
||||
| 1 * spi.SPI_CS_POLARITY
|
||||
| 0 * spi.SPI_CLK_POLARITY
|
||||
| 0 * spi.SPI_CLK_PHASE
|
||||
| 0 * spi.SPI_LSB_FIRST
|
||||
| 0 * spi.SPI_HALF_DUPLEX
|
||||
)
|
||||
|
||||
|
||||
ADF5356_MIN_VCO_FREQ = int64(3.4 * GHz)
|
||||
ADF5356_MAX_VCO_FREQ = int64(6.8 * GHz)
|
||||
ADF5356_MAX_FREQ_PFD = int32(125.0 * MHz)
|
||||
ADF5356_MODULUS1 = int32(1 << 24)
|
||||
ADF5356_MAX_MODULUS2 = int32(1 << 28) # FIXME: ADF5356 has 28 bits MOD2
|
||||
ADF5356_MAX_R_CNT = int32(1023)
|
||||
|
||||
|
||||
class ADF5356:
|
||||
"""Analog Devices AD[45]35[56] family of GHz PLLs.
|
||||
|
||||
:param cpld_device: Mirny CPLD device name
|
||||
:param sw_device: Mirny RF switch device name
|
||||
:param channel: Mirny RF channel index
|
||||
:param ref_doubler: enable/disable reference clock doubler
|
||||
:param ref_divider: enable/disable reference clock divide-by-2
|
||||
:param core_device: Core device name (default: "core")
|
||||
"""
|
||||
|
||||
kernel_invariants = {"cpld", "sw", "channel", "core", "sysclk"}
|
||||
|
||||
def __init__(
|
||||
self,
|
||||
dmgr,
|
||||
cpld_device,
|
||||
sw_device,
|
||||
channel,
|
||||
ref_doubler=False,
|
||||
ref_divider=False,
|
||||
core="core",
|
||||
):
|
||||
self.cpld = dmgr.get(cpld_device)
|
||||
self.sw = dmgr.get(sw_device)
|
||||
self.channel = channel
|
||||
self.core = dmgr.get(core)
|
||||
|
||||
self.ref_doubler = ref_doubler
|
||||
self.ref_divider = ref_divider
|
||||
self.sysclk = self.cpld.refclk
|
||||
assert 10 <= self.sysclk / 1e6 <= 600
|
||||
|
||||
self._init_registers()
|
||||
|
||||
@staticmethod
|
||||
def get_rtio_channels(**kwargs):
|
||||
return []
|
||||
|
||||
@kernel
|
||||
def init(self, blind=False):
|
||||
"""
|
||||
Initialize and configure the PLL.
|
||||
|
||||
:param blind: Do not attempt to verify presence.
|
||||
"""
|
||||
if not blind:
|
||||
# MUXOUT = VDD
|
||||
self.regs[4] = ADF5356_REG4_MUXOUT_UPDATE(self.regs[4], 1)
|
||||
self.sync()
|
||||
delay(1000 * us)
|
||||
if not self.read_muxout():
|
||||
raise ValueError("MUXOUT not high")
|
||||
delay(800 * us)
|
||||
|
||||
# MUXOUT = DGND
|
||||
self.regs[4] = ADF5356_REG4_MUXOUT_UPDATE(self.regs[4], 2)
|
||||
self.sync()
|
||||
delay(1000 * us)
|
||||
if self.read_muxout():
|
||||
raise ValueError("MUXOUT not low")
|
||||
delay(800 * us)
|
||||
|
||||
# MUXOUT = digital lock-detect
|
||||
self.regs[4] = ADF5356_REG4_MUXOUT_UPDATE(self.regs[4], 6)
|
||||
else:
|
||||
self.sync()
|
||||
|
||||
@kernel
|
||||
def set_att(self, att):
|
||||
"""Set digital step attenuator in SI units.
|
||||
|
||||
This method will write the attenuator settings of the channel.
|
||||
|
||||
.. seealso:: :meth:`artiq.coredevice.mirny.Mirny.set_att`
|
||||
|
||||
:param att: Attenuation in dB.
|
||||
"""
|
||||
self.cpld.set_att(self.channel, att)
|
||||
|
||||
@kernel
|
||||
def set_att_mu(self, att):
|
||||
"""Set digital step attenuator in machine units.
|
||||
|
||||
:param att: Attenuation setting, 8 bit digital.
|
||||
"""
|
||||
self.cpld.set_att_mu(self.channel, att)
|
||||
|
||||
@kernel
|
||||
def write(self, data):
|
||||
self.cpld.write_ext(self.channel | 4, 32, data)
|
||||
|
||||
@kernel
|
||||
def read_muxout(self):
|
||||
"""
|
||||
Read the state of the MUXOUT line.
|
||||
|
||||
By default, this is configured to be the digital lock detection.
|
||||
"""
|
||||
return bool(self.cpld.read_reg(0) & (1 << (self.channel + 8)))
|
||||
|
||||
@kernel
|
||||
def set_output_power_mu(self, n):
|
||||
"""
|
||||
Set the power level at output A of the PLL chip in machine units.
|
||||
|
||||
This driver defaults to `n = 3` at init.
|
||||
|
||||
:param n: output power setting, 0, 1, 2, or 3 (see ADF5356 datasheet, fig. 44).
|
||||
"""
|
||||
if n not in [0, 1, 2, 3]:
|
||||
raise ValueError("invalid power setting")
|
||||
self.regs[6] = ADF5356_REG6_RF_OUTPUT_A_POWER_UPDATE(self.regs[6], n)
|
||||
self.sync()
|
||||
|
||||
@portable
|
||||
def output_power_mu(self):
|
||||
"""
|
||||
Return the power level at output A of the PLL chip in machine units.
|
||||
"""
|
||||
return ADF5356_REG6_RF_OUTPUT_A_POWER_GET(self.regs[6])
|
||||
|
||||
@kernel
|
||||
def enable_output(self):
|
||||
"""
|
||||
Enable output A of the PLL chip. This is the default after init.
|
||||
"""
|
||||
self.regs[6] |= ADF5356_REG6_RF_OUTPUT_A_ENABLE(1)
|
||||
self.sync()
|
||||
|
||||
@kernel
|
||||
def disable_output(self):
|
||||
"""
|
||||
Disable output A of the PLL chip.
|
||||
"""
|
||||
self.regs[6] &= ~ADF5356_REG6_RF_OUTPUT_A_ENABLE(1)
|
||||
self.sync()
|
||||
|
||||
@kernel
|
||||
def set_frequency(self, f):
|
||||
"""
|
||||
Output given frequency on output A.
|
||||
|
||||
:param f: 53.125 MHz <= f <= 6800 MHz
|
||||
"""
|
||||
freq = int64(round(f))
|
||||
|
||||
if freq > ADF5356_MAX_VCO_FREQ:
|
||||
raise ValueError("Requested too high frequency")
|
||||
|
||||
# select minimal output divider
|
||||
rf_div_sel = 0
|
||||
while freq < ADF5356_MIN_VCO_FREQ:
|
||||
freq <<= 1
|
||||
rf_div_sel += 1
|
||||
|
||||
if (1 << rf_div_sel) > 64:
|
||||
raise ValueError("Requested too low frequency")
|
||||
|
||||
# choose reference divider that maximizes PFD frequency
|
||||
self.regs[4] = ADF5356_REG4_R_COUNTER_UPDATE(
|
||||
self.regs[4], self._compute_reference_counter()
|
||||
)
|
||||
f_pfd = self.f_pfd()
|
||||
|
||||
# choose prescaler
|
||||
if freq > int64(6e9):
|
||||
self.regs[0] |= ADF5356_REG0_PRESCALER(1) # 8/9
|
||||
n_min, n_max = 75, 65535
|
||||
|
||||
# adjust reference divider to be able to match n_min constraint
|
||||
while n_min * f_pfd > freq:
|
||||
r = ADF5356_REG4_R_COUNTER_GET(self.regs[4])
|
||||
self.regs[4] = ADF5356_REG4_R_COUNTER_UPDATE(self.regs[4], r + 1)
|
||||
f_pfd = self.f_pfd()
|
||||
else:
|
||||
self.regs[0] &= ~ADF5356_REG0_PRESCALER(1) # 4/5
|
||||
n_min, n_max = 23, 32767
|
||||
|
||||
# calculate PLL parameters
|
||||
n, frac1, (frac2_msb, frac2_lsb), (mod2_msb, mod2_lsb) = calculate_pll(
|
||||
freq, f_pfd
|
||||
)
|
||||
|
||||
if not (n_min <= n <= n_max):
|
||||
raise ValueError("Invalid INT value")
|
||||
|
||||
# configure PLL
|
||||
self.regs[0] = ADF5356_REG0_INT_VALUE_UPDATE(self.regs[0], n)
|
||||
self.regs[1] = ADF5356_REG1_MAIN_FRAC_VALUE_UPDATE(self.regs[1], frac1)
|
||||
self.regs[2] = ADF5356_REG2_AUX_FRAC_LSB_VALUE_UPDATE(self.regs[2], frac2_lsb)
|
||||
self.regs[2] = ADF5356_REG2_AUX_MOD_LSB_VALUE_UPDATE(self.regs[2], mod2_lsb)
|
||||
self.regs[13] = ADF5356_REG13_AUX_FRAC_MSB_VALUE_UPDATE(
|
||||
self.regs[13], frac2_msb
|
||||
)
|
||||
self.regs[13] = ADF5356_REG13_AUX_MOD_MSB_VALUE_UPDATE(self.regs[13], mod2_msb)
|
||||
|
||||
self.regs[6] = ADF5356_REG6_RF_DIVIDER_SELECT_UPDATE(self.regs[6], rf_div_sel)
|
||||
self.regs[6] = ADF5356_REG6_CP_BLEED_CURRENT_UPDATE(
|
||||
self.regs[6], int32(floor(24 * f_pfd / (61.44 * MHz)))
|
||||
)
|
||||
self.regs[9] = ADF5356_REG9_VCO_BAND_DIVISION_UPDATE(
|
||||
self.regs[9], int32(ceil(f_pfd / 160e3))
|
||||
)
|
||||
|
||||
# commit
|
||||
self.sync()
|
||||
|
||||
@kernel
|
||||
def sync(self):
|
||||
"""
|
||||
Write all registers to the device. Attempts to lock the PLL.
|
||||
"""
|
||||
f_pfd = self.f_pfd()
|
||||
delay(200 * us) # Slack
|
||||
|
||||
if f_pfd <= 75.0 * MHz:
|
||||
for i in range(13, 0, -1):
|
||||
self.write(self.regs[i])
|
||||
delay(200 * us)
|
||||
self.write(self.regs[0] | ADF5356_REG0_AUTOCAL(1))
|
||||
else:
|
||||
# AUTOCAL AT HALF PFD FREQUENCY
|
||||
|
||||
# calculate PLL at f_pfd/2
|
||||
n, frac1, (frac2_msb, frac2_lsb), (mod2_msb, mod2_lsb) = calculate_pll(
|
||||
self.f_vco(), f_pfd >> 1
|
||||
)
|
||||
delay(200 * us) # Slack
|
||||
|
||||
self.write(
|
||||
13
|
||||
| ADF5356_REG13_AUX_FRAC_MSB_VALUE(frac2_msb)
|
||||
| ADF5356_REG13_AUX_MOD_MSB_VALUE(mod2_msb)
|
||||
)
|
||||
|
||||
for i in range(12, 4, -1):
|
||||
self.write(self.regs[i])
|
||||
|
||||
self.write(
|
||||
ADF5356_REG4_R_COUNTER_UPDATE(self.regs[4], 2 * self.ref_counter())
|
||||
)
|
||||
|
||||
self.write(self.regs[3])
|
||||
self.write(
|
||||
2
|
||||
| ADF5356_REG2_AUX_MOD_LSB_VALUE(mod2_lsb)
|
||||
| ADF5356_REG2_AUX_FRAC_LSB_VALUE(frac2_lsb)
|
||||
)
|
||||
self.write(1 | ADF5356_REG1_MAIN_FRAC_VALUE(frac1))
|
||||
|
||||
delay(200 * us)
|
||||
self.write(ADF5356_REG0_INT_VALUE(n) | ADF5356_REG0_AUTOCAL(1))
|
||||
|
||||
# RELOCK AT WANTED PFD FREQUENCY
|
||||
|
||||
for i in [4, 2, 1]:
|
||||
self.write(self.regs[i])
|
||||
|
||||
# force-disable autocal
|
||||
self.write(self.regs[0] & ~ADF5356_REG0_AUTOCAL(1))
|
||||
|
||||
@portable
|
||||
def f_pfd(self) -> TInt64:
|
||||
"""
|
||||
Return the PFD frequency for the cached set of registers.
|
||||
"""
|
||||
r = ADF5356_REG4_R_COUNTER_GET(self.regs[4])
|
||||
d = ADF5356_REG4_R_DOUBLER_GET(self.regs[4])
|
||||
t = ADF5356_REG4_R_DIVIDER_GET(self.regs[4])
|
||||
return self._compute_pfd_frequency(r, d, t)
|
||||
|
||||
@portable
|
||||
def f_vco(self) -> TInt64:
|
||||
"""
|
||||
Return the VCO frequency for the cached set of registers.
|
||||
"""
|
||||
return int64(
|
||||
self.f_pfd()
|
||||
* (
|
||||
self.pll_n()
|
||||
+ (self.pll_frac1() + self.pll_frac2() / self.pll_mod2())
|
||||
/ ADF5356_MODULUS1
|
||||
)
|
||||
)
|
||||
|
||||
@portable
|
||||
def pll_n(self) -> TInt32:
|
||||
"""
|
||||
Return the PLL integer value (INT) for the cached set of registers.
|
||||
"""
|
||||
return ADF5356_REG0_INT_VALUE_GET(self.regs[0])
|
||||
|
||||
@portable
|
||||
def pll_frac1(self) -> TInt32:
|
||||
"""
|
||||
Return the main fractional value (FRAC1) for the cached set of registers.
|
||||
"""
|
||||
return ADF5356_REG1_MAIN_FRAC_VALUE_GET(self.regs[1])
|
||||
|
||||
@portable
|
||||
def pll_frac2(self) -> TInt32:
|
||||
"""
|
||||
Return the auxiliary fractional value (FRAC2) for the cached set of registers.
|
||||
"""
|
||||
return (
|
||||
ADF5356_REG13_AUX_FRAC_MSB_VALUE_GET(self.regs[13]) << 14
|
||||
) | ADF5356_REG2_AUX_FRAC_LSB_VALUE_GET(self.regs[2])
|
||||
|
||||
@portable
|
||||
def pll_mod2(self) -> TInt32:
|
||||
"""
|
||||
Return the auxiliary modulus value (MOD2) for the cached set of registers.
|
||||
"""
|
||||
return (
|
||||
ADF5356_REG13_AUX_MOD_MSB_VALUE_GET(self.regs[13]) << 14
|
||||
) | ADF5356_REG2_AUX_MOD_LSB_VALUE_GET(self.regs[2])
|
||||
|
||||
@portable
|
||||
def ref_counter(self) -> TInt32:
|
||||
"""
|
||||
Return the reference counter value (R) for the cached set of registers.
|
||||
"""
|
||||
return ADF5356_REG4_R_COUNTER_GET(self.regs[4])
|
||||
|
||||
@portable
|
||||
def output_divider(self) -> TInt32:
|
||||
"""
|
||||
Return the value of the output A divider.
|
||||
"""
|
||||
return 1 << ADF5356_REG6_RF_DIVIDER_SELECT_GET(self.regs[6])
|
||||
|
||||
def info(self):
|
||||
"""
|
||||
Return a summary of high-level parameters as a dict.
|
||||
"""
|
||||
prescaler = ADF5356_REG0_PRESCALER_GET(self.regs[0])
|
||||
return {
|
||||
# output
|
||||
"f_outA": self.f_vco() / self.output_divider(),
|
||||
"f_outB": self.f_vco() * 2,
|
||||
"output_divider": self.output_divider(),
|
||||
# PLL parameters
|
||||
"f_vco": self.f_vco(),
|
||||
"pll_n": self.pll_n(),
|
||||
"pll_frac1": self.pll_frac1(),
|
||||
"pll_frac2": self.pll_frac2(),
|
||||
"pll_mod2": self.pll_mod2(),
|
||||
"prescaler": "4/5" if prescaler == 0 else "8/9",
|
||||
# reference / PFD
|
||||
"sysclk": self.sysclk,
|
||||
"ref_doubler": self.ref_doubler,
|
||||
"ref_divider": self.ref_divider,
|
||||
"ref_counter": self.ref_counter(),
|
||||
"f_pfd": self.f_pfd(),
|
||||
}
|
||||
|
||||
@portable
|
||||
def _init_registers(self):
|
||||
"""
|
||||
Initialize cached registers with sensible defaults.
|
||||
"""
|
||||
# fill with control bits
|
||||
self.regs = [int32(i) for i in range(ADF5356_NUM_REGS)]
|
||||
|
||||
# REG2
|
||||
# ====
|
||||
|
||||
# avoid divide-by-zero
|
||||
self.regs[2] |= ADF5356_REG2_AUX_MOD_LSB_VALUE(1)
|
||||
|
||||
# REG4
|
||||
# ====
|
||||
|
||||
# single-ended reference mode is recommended
|
||||
# for references up to 250 MHz, even if the signal is differential
|
||||
if self.sysclk <= 250 * MHz:
|
||||
self.regs[4] |= ADF5356_REG4_REF_MODE(0)
|
||||
else:
|
||||
self.regs[4] |= ADF5356_REG4_REF_MODE(1)
|
||||
|
||||
# phase detector polarity: positive
|
||||
self.regs[4] |= ADF5356_REG4_PD_POLARITY(1)
|
||||
|
||||
# charge pump current: 0.94 mA
|
||||
self.regs[4] |= ADF5356_REG4_CURRENT_SETTING(2)
|
||||
|
||||
# MUXOUT: digital lock detect
|
||||
self.regs[4] |= ADF5356_REG4_MUX_LOGIC(1) # 3v3 logic
|
||||
self.regs[4] |= ADF5356_REG4_MUXOUT(6)
|
||||
|
||||
# setup reference path
|
||||
if self.ref_doubler:
|
||||
self.regs[4] |= ADF5356_REG4_R_DOUBLER(1)
|
||||
|
||||
if self.ref_divider:
|
||||
self.regs[4] |= ADF5356_REG4_R_DIVIDER(1)
|
||||
|
||||
r = self._compute_reference_counter()
|
||||
self.regs[4] |= ADF5356_REG4_R_COUNTER(r)
|
||||
|
||||
# REG5
|
||||
# ====
|
||||
|
||||
# reserved values
|
||||
self.regs[5] = int32(0x800025)
|
||||
|
||||
# REG6
|
||||
# ====
|
||||
|
||||
# reserved values
|
||||
self.regs[6] = int32(0x14000006)
|
||||
|
||||
# enable negative bleed
|
||||
self.regs[6] |= ADF5356_REG6_NEGATIVE_BLEED(1)
|
||||
|
||||
# charge pump bleed current
|
||||
self.regs[6] |= ADF5356_REG6_CP_BLEED_CURRENT(
|
||||
int32(floor(24 * self.f_pfd() / (61.44 * MHz)))
|
||||
)
|
||||
|
||||
# direct feedback from VCO to N counter
|
||||
self.regs[6] |= ADF5356_REG6_FB_SELECT(1)
|
||||
|
||||
# mute until the PLL is locked
|
||||
self.regs[6] |= ADF5356_REG6_MUTE_TILL_LD(1)
|
||||
|
||||
# enable output A
|
||||
self.regs[6] |= ADF5356_REG6_RF_OUTPUT_A_ENABLE(1)
|
||||
|
||||
# set output A power to max power, is adjusted by extra attenuator
|
||||
self.regs[6] |= ADF5356_REG6_RF_OUTPUT_A_POWER(3) # +5 dBm
|
||||
|
||||
# REG7
|
||||
# ====
|
||||
|
||||
# reserved values
|
||||
self.regs[7] = int32(0x10000007)
|
||||
|
||||
# sync load-enable to reference
|
||||
self.regs[7] |= ADF5356_REG7_LE_SYNC(1)
|
||||
|
||||
# frac-N lock-detect precision: 12 ns
|
||||
self.regs[7] |= ADF5356_REG7_FRAC_N_LD_PRECISION(3)
|
||||
|
||||
# REG8
|
||||
# ====
|
||||
|
||||
# reserved values
|
||||
self.regs[8] = int32(0x102D0428)
|
||||
|
||||
# REG9
|
||||
# ====
|
||||
|
||||
# default timeouts (from eval software)
|
||||
self.regs[9] |= (
|
||||
ADF5356_REG9_SYNTH_LOCK_TIMEOUT(13)
|
||||
| ADF5356_REG9_AUTOCAL_TIMEOUT(31)
|
||||
| ADF5356_REG9_TIMEOUT(0x67)
|
||||
)
|
||||
|
||||
self.regs[9] |= ADF5356_REG9_VCO_BAND_DIVISION(
|
||||
int32(ceil(self.f_pfd() / 160e3))
|
||||
)
|
||||
|
||||
# REG10
|
||||
# =====
|
||||
|
||||
# reserved values
|
||||
self.regs[10] = int32(0xC0000A)
|
||||
|
||||
# ADC defaults (from eval software)
|
||||
self.regs[10] |= (
|
||||
ADF5356_REG10_ADC_ENABLE(1)
|
||||
| ADF5356_REG10_ADC_CLK_DIV(256)
|
||||
| ADF5356_REG10_ADC_CONV(1)
|
||||
)
|
||||
|
||||
# REG11
|
||||
# =====
|
||||
|
||||
# reserved values
|
||||
self.regs[11] = int32(0x61200B)
|
||||
|
||||
# REG12
|
||||
# =====
|
||||
|
||||
# reserved values
|
||||
self.regs[12] = int32(0x15FC)
|
||||
|
||||
@portable
|
||||
def _compute_pfd_frequency(self, r, d, t) -> TInt64:
|
||||
"""
|
||||
Calculate the PFD frequency from the given reference path parameters
|
||||
"""
|
||||
return int64(self.sysclk * ((1 + d) / (r * (1 + t))))
|
||||
|
||||
@portable
|
||||
def _compute_reference_counter(self) -> TInt32:
|
||||
"""
|
||||
Determine the reference counter R that maximizes the PFD frequency
|
||||
"""
|
||||
d = ADF5356_REG4_R_DOUBLER_GET(self.regs[4])
|
||||
t = ADF5356_REG4_R_DIVIDER_GET(self.regs[4])
|
||||
r = 1
|
||||
while self._compute_pfd_frequency(r, d, t) > ADF5356_MAX_FREQ_PFD:
|
||||
r += 1
|
||||
return int32(r)
|
||||
|
||||
|
||||
@portable
|
||||
def gcd(a, b):
|
||||
while b:
|
||||
a, b = b, a % b
|
||||
return a
|
||||
|
||||
|
||||
@portable
|
||||
def split_msb_lsb_28b(v):
|
||||
return int32((v >> 14) & 0x3FFF), int32(v & 0x3FFF)
|
||||
|
||||
|
||||
@portable
|
||||
def calculate_pll(f_vco: TInt64, f_pfd: TInt64):
|
||||
"""
|
||||
Calculate fractional-N PLL parameters such that
|
||||
|
||||
``f_vco`` = ``f_pfd`` * (``n`` + (``frac1`` + ``frac2``/``mod2``) / ``mod1``)
|
||||
|
||||
where
|
||||
``mod1 = 2**24`` and ``mod2 <= 2**28``
|
||||
|
||||
:param f_vco: target VCO frequency
|
||||
:param f_pfd: PFD frequency
|
||||
:return: ``(n, frac1, (frac2_msb, frac2_lsb), (mod2_msb, mod2_lsb))``
|
||||
"""
|
||||
f_pfd = int64(f_pfd)
|
||||
f_vco = int64(f_vco)
|
||||
|
||||
# integral part
|
||||
n, r = int32(f_vco // f_pfd), f_vco % f_pfd
|
||||
|
||||
# main fractional part
|
||||
r *= ADF5356_MODULUS1
|
||||
frac1, frac2 = int32(r // f_pfd), r % f_pfd
|
||||
|
||||
# auxiliary fractional part
|
||||
mod2 = f_pfd
|
||||
|
||||
while mod2 > ADF5356_MAX_MODULUS2:
|
||||
mod2 >>= 1
|
||||
frac2 >>= 1
|
||||
|
||||
gcd_div = gcd(frac2, mod2)
|
||||
mod2 //= gcd_div
|
||||
frac2 //= gcd_div
|
||||
|
||||
return n, frac1, split_msb_lsb_28b(frac2), split_msb_lsb_28b(mod2)
|
||||
|
|
@ -1,642 +0,0 @@
|
|||
# auto-generated, do not edit
|
||||
from artiq.language.core import portable
|
||||
from artiq.language.types import TInt32
|
||||
from numpy import int32
|
||||
|
||||
@portable
|
||||
def ADF5356_REG0_AUTOCAL_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 21) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG0_AUTOCAL(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 21)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG0_AUTOCAL_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 21)) | ((x & 0x1) << 21))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG0_INT_VALUE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 4) & 0xffff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG0_INT_VALUE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0xffff) << 4)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG0_INT_VALUE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0xffff << 4)) | ((x & 0xffff) << 4))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG0_PRESCALER_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 20) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG0_PRESCALER(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 20)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG0_PRESCALER_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 20)) | ((x & 0x1) << 20))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG1_MAIN_FRAC_VALUE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 4) & 0xffffff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG1_MAIN_FRAC_VALUE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0xffffff) << 4)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG1_MAIN_FRAC_VALUE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0xffffff << 4)) | ((x & 0xffffff) << 4))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG2_AUX_FRAC_LSB_VALUE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 18) & 0x3fff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG2_AUX_FRAC_LSB_VALUE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x3fff) << 18)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG2_AUX_FRAC_LSB_VALUE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x3fff << 18)) | ((x & 0x3fff) << 18))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG2_AUX_MOD_LSB_VALUE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 4) & 0x3fff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG2_AUX_MOD_LSB_VALUE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x3fff) << 4)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG2_AUX_MOD_LSB_VALUE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x3fff << 4)) | ((x & 0x3fff) << 4))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_PHASE_ADJUST_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 28) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_PHASE_ADJUST(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 28)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_PHASE_ADJUST_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 28)) | ((x & 0x1) << 28))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_PHASE_RESYNC_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 29) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_PHASE_RESYNC(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 29)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_PHASE_RESYNC_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 29)) | ((x & 0x1) << 29))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_PHASE_VALUE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 4) & 0xffffff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_PHASE_VALUE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0xffffff) << 4)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_PHASE_VALUE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0xffffff << 4)) | ((x & 0xffffff) << 4))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_SD_LOAD_RESET_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 30) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_SD_LOAD_RESET(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 30)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG3_SD_LOAD_RESET_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 30)) | ((x & 0x1) << 30))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_COUNTER_RESET_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 4) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_COUNTER_RESET(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 4)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_COUNTER_RESET_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 4)) | ((x & 0x1) << 4))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_CP_THREE_STATE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 5) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_CP_THREE_STATE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 5)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_CP_THREE_STATE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 5)) | ((x & 0x1) << 5))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_CURRENT_SETTING_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 10) & 0xf)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_CURRENT_SETTING(x: TInt32) -> TInt32:
|
||||
return int32((x & 0xf) << 10)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_CURRENT_SETTING_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0xf << 10)) | ((x & 0xf) << 10))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_DOUBLE_BUFF_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 14) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_DOUBLE_BUFF(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 14)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_DOUBLE_BUFF_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 14)) | ((x & 0x1) << 14))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_MUX_LOGIC_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 8) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_MUX_LOGIC(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 8)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_MUX_LOGIC_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 8)) | ((x & 0x1) << 8))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_MUXOUT_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 27) & 0x7)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_MUXOUT(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x7) << 27)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_MUXOUT_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x7 << 27)) | ((x & 0x7) << 27))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_PD_POLARITY_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 7) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_PD_POLARITY(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 7)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_PD_POLARITY_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 7)) | ((x & 0x1) << 7))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_POWER_DOWN_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 6) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_POWER_DOWN(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 6)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_POWER_DOWN_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 6)) | ((x & 0x1) << 6))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_R_COUNTER_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 15) & 0x3ff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_R_COUNTER(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x3ff) << 15)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_R_COUNTER_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x3ff << 15)) | ((x & 0x3ff) << 15))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_R_DIVIDER_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 25) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_R_DIVIDER(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 25)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_R_DIVIDER_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 25)) | ((x & 0x1) << 25))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_R_DOUBLER_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 26) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_R_DOUBLER(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 26)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_R_DOUBLER_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 26)) | ((x & 0x1) << 26))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_REF_MODE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 9) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_REF_MODE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 9)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG4_REF_MODE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 9)) | ((x & 0x1) << 9))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_BLEED_POLARITY_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 31) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_BLEED_POLARITY(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 31)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_BLEED_POLARITY_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 31)) | ((x & 0x1) << 31))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_CP_BLEED_CURRENT_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 13) & 0xff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_CP_BLEED_CURRENT(x: TInt32) -> TInt32:
|
||||
return int32((x & 0xff) << 13)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_CP_BLEED_CURRENT_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0xff << 13)) | ((x & 0xff) << 13))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_FB_SELECT_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 24) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_FB_SELECT(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 24)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_FB_SELECT_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 24)) | ((x & 0x1) << 24))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_GATE_BLEED_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 30) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_GATE_BLEED(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 30)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_GATE_BLEED_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 30)) | ((x & 0x1) << 30))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_MUTE_TILL_LD_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 11) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_MUTE_TILL_LD(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 11)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_MUTE_TILL_LD_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 11)) | ((x & 0x1) << 11))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_NEGATIVE_BLEED_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 29) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_NEGATIVE_BLEED(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 29)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_NEGATIVE_BLEED_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 29)) | ((x & 0x1) << 29))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_DIVIDER_SELECT_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 21) & 0x7)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_DIVIDER_SELECT(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x7) << 21)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_DIVIDER_SELECT_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x7 << 21)) | ((x & 0x7) << 21))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_OUTPUT_A_ENABLE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 6) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_OUTPUT_A_ENABLE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 6)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_OUTPUT_A_ENABLE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 6)) | ((x & 0x1) << 6))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_OUTPUT_A_POWER_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 4) & 0x3)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_OUTPUT_A_POWER(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x3) << 4)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_OUTPUT_A_POWER_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x3 << 4)) | ((x & 0x3) << 4))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_OUTPUT_B_ENABLE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 10) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_OUTPUT_B_ENABLE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 10)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG6_RF_OUTPUT_B_ENABLE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 10)) | ((x & 0x1) << 10))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_FRAC_N_LD_PRECISION_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 5) & 0x3)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_FRAC_N_LD_PRECISION(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x3) << 5)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_FRAC_N_LD_PRECISION_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x3 << 5)) | ((x & 0x3) << 5))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LD_CYCLE_COUNT_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 8) & 0x3)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LD_CYCLE_COUNT(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x3) << 8)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LD_CYCLE_COUNT_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x3 << 8)) | ((x & 0x3) << 8))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LD_MODE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 4) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LD_MODE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 4)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LD_MODE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 4)) | ((x & 0x1) << 4))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LE_SEL_SYNC_EDGE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 27) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LE_SEL_SYNC_EDGE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 27)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LE_SEL_SYNC_EDGE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 27)) | ((x & 0x1) << 27))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LE_SYNC_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 25) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LE_SYNC(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 25)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LE_SYNC_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 25)) | ((x & 0x1) << 25))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LOL_MODE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 7) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LOL_MODE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 7)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG7_LOL_MODE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 7)) | ((x & 0x1) << 7))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_AUTOCAL_TIMEOUT_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 9) & 0x1f)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_AUTOCAL_TIMEOUT(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1f) << 9)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_AUTOCAL_TIMEOUT_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1f << 9)) | ((x & 0x1f) << 9))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_SYNTH_LOCK_TIMEOUT_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 4) & 0x1f)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_SYNTH_LOCK_TIMEOUT(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1f) << 4)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_SYNTH_LOCK_TIMEOUT_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1f << 4)) | ((x & 0x1f) << 4))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_TIMEOUT_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 14) & 0x3ff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_TIMEOUT(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x3ff) << 14)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_TIMEOUT_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x3ff << 14)) | ((x & 0x3ff) << 14))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_VCO_BAND_DIVISION_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 24) & 0xff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_VCO_BAND_DIVISION(x: TInt32) -> TInt32:
|
||||
return int32((x & 0xff) << 24)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG9_VCO_BAND_DIVISION_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0xff << 24)) | ((x & 0xff) << 24))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG10_ADC_CLK_DIV_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 6) & 0xff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG10_ADC_CLK_DIV(x: TInt32) -> TInt32:
|
||||
return int32((x & 0xff) << 6)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG10_ADC_CLK_DIV_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0xff << 6)) | ((x & 0xff) << 6))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG10_ADC_CONV_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 5) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG10_ADC_CONV(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 5)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG10_ADC_CONV_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 5)) | ((x & 0x1) << 5))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG10_ADC_ENABLE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 4) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG10_ADC_ENABLE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 4)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG10_ADC_ENABLE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 4)) | ((x & 0x1) << 4))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG11_VCO_BAND_HOLD_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 24) & 0x1)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG11_VCO_BAND_HOLD(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x1) << 24)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG11_VCO_BAND_HOLD_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x1 << 24)) | ((x & 0x1) << 24))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG12_PHASE_RESYNC_CLK_VALUE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 12) & 0xfffff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG12_PHASE_RESYNC_CLK_VALUE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0xfffff) << 12)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG12_PHASE_RESYNC_CLK_VALUE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0xfffff << 12)) | ((x & 0xfffff) << 12))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG13_AUX_FRAC_MSB_VALUE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 18) & 0x3fff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG13_AUX_FRAC_MSB_VALUE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x3fff) << 18)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG13_AUX_FRAC_MSB_VALUE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x3fff << 18)) | ((x & 0x3fff) << 18))
|
||||
|
||||
|
||||
@portable
|
||||
def ADF5356_REG13_AUX_MOD_MSB_VALUE_GET(reg: TInt32) -> TInt32:
|
||||
return int32((reg >> 4) & 0x3fff)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG13_AUX_MOD_MSB_VALUE(x: TInt32) -> TInt32:
|
||||
return int32((x & 0x3fff) << 4)
|
||||
|
||||
@portable
|
||||
def ADF5356_REG13_AUX_MOD_MSB_VALUE_UPDATE(reg: TInt32, x: TInt32) -> TInt32:
|
||||
return int32((reg & ~(0x3fff << 4)) | ((x & 0x3fff) << 4))
|
||||
|
||||
ADF5356_NUM_REGS = 14
|
||||
|
|
@ -1,185 +0,0 @@
|
|||
from artiq.language.core import kernel, portable
|
||||
|
||||
from numpy import int32
|
||||
|
||||
|
||||
# almazny-specific data
|
||||
ALMAZNY_LEGACY_REG_BASE = 0x0C
|
||||
ALMAZNY_LEGACY_OE_SHIFT = 12
|
||||
|
||||
# higher SPI write divider to match almazny shift register timing
|
||||
# min SER time before SRCLK rise = 125ns
|
||||
# -> div=32 gives 125ns for data before clock rise
|
||||
# works at faster dividers too but could be less reliable
|
||||
ALMAZNY_LEGACY_SPIT_WR = 32
|
||||
|
||||
|
||||
class AlmaznyLegacy:
|
||||
"""
|
||||
Almazny (High frequency mezzanine board for Mirny)
|
||||
|
||||
This applies to Almazny hardware v1.1 and earlier.
|
||||
Use :class:`artiq.coredevice.almazny.AlmaznyChannel` for Almazny v1.2 and later.
|
||||
|
||||
:param host_mirny: Mirny device Almazny is connected to
|
||||
"""
|
||||
|
||||
def __init__(self, dmgr, host_mirny):
|
||||
self.mirny_cpld = dmgr.get(host_mirny)
|
||||
self.att_mu = [0x3f] * 4
|
||||
self.channel_sw = [0] * 4
|
||||
self.output_enable = False
|
||||
|
||||
@kernel
|
||||
def init(self):
|
||||
self.output_toggle(self.output_enable)
|
||||
|
||||
@kernel
|
||||
def att_to_mu(self, att):
|
||||
"""
|
||||
Convert an attenuator setting in dB to machine units.
|
||||
|
||||
:param att: attenuator setting in dB [0-31.5]
|
||||
:return: attenuator setting in machine units
|
||||
"""
|
||||
mu = round(att * 2.0)
|
||||
if mu > 63 or mu < 0:
|
||||
raise ValueError("Invalid Almazny attenuator settings!")
|
||||
return mu
|
||||
|
||||
@kernel
|
||||
def mu_to_att(self, att_mu):
|
||||
"""
|
||||
Convert a digital attenuator setting to dB.
|
||||
|
||||
:param att_mu: attenuator setting in machine units
|
||||
:return: attenuator setting in dB
|
||||
"""
|
||||
return att_mu / 2
|
||||
|
||||
@kernel
|
||||
def set_att(self, channel, att, rf_switch=True):
|
||||
"""
|
||||
Sets attenuators on chosen shift register (channel).
|
||||
|
||||
:param channel: index of the register [0-3]
|
||||
:param att: attenuation setting in dBm [0-31.5]
|
||||
:param rf_switch: rf switch (bool)
|
||||
"""
|
||||
self.set_att_mu(channel, self.att_to_mu(att), rf_switch)
|
||||
|
||||
@kernel
|
||||
def set_att_mu(self, channel, att_mu, rf_switch=True):
|
||||
"""
|
||||
Sets attenuators on chosen shift register (channel).
|
||||
|
||||
:param channel: index of the register [0-3]
|
||||
:param att_mu: attenuation setting in machine units [0-63]
|
||||
:param rf_switch: rf switch (bool)
|
||||
"""
|
||||
self.channel_sw[channel] = 1 if rf_switch else 0
|
||||
self.att_mu[channel] = att_mu
|
||||
self._update_register(channel)
|
||||
|
||||
@kernel
|
||||
def output_toggle(self, oe):
|
||||
"""
|
||||
Toggles output on all shift registers on or off.
|
||||
|
||||
:param oe: toggle output enable (bool)
|
||||
"""
|
||||
self.output_enable = oe
|
||||
cfg_reg = self.mirny_cpld.read_reg(1)
|
||||
en = 1 if self.output_enable else 0
|
||||
delay(100 * us)
|
||||
new_reg = (en << ALMAZNY_LEGACY_OE_SHIFT) | (cfg_reg & 0x3FF)
|
||||
self.mirny_cpld.write_reg(1, new_reg)
|
||||
delay(100 * us)
|
||||
|
||||
@kernel
|
||||
def _flip_mu_bits(self, mu):
|
||||
# in this form MSB is actually 0.5dB attenuator
|
||||
# unnatural for users, so we flip the six bits
|
||||
return (((mu & 0x01) << 5)
|
||||
| ((mu & 0x02) << 3)
|
||||
| ((mu & 0x04) << 1)
|
||||
| ((mu & 0x08) >> 1)
|
||||
| ((mu & 0x10) >> 3)
|
||||
| ((mu & 0x20) >> 5))
|
||||
|
||||
@kernel
|
||||
def _update_register(self, ch):
|
||||
self.mirny_cpld.write_ext(
|
||||
ALMAZNY_LEGACY_REG_BASE + ch,
|
||||
8,
|
||||
self._flip_mu_bits(self.att_mu[ch]) | (self.channel_sw[ch] << 6),
|
||||
ALMAZNY_LEGACY_SPIT_WR
|
||||
)
|
||||
delay(100 * us)
|
||||
|
||||
@kernel
|
||||
def _update_all_registers(self):
|
||||
for i in range(4):
|
||||
self._update_register(i)
|
||||
|
||||
|
||||
class AlmaznyChannel:
|
||||
"""
|
||||
One Almazny channel
|
||||
Almazny is a mezzanine for the Quad PLL RF source Mirny that exposes and
|
||||
controls the frequency-doubled outputs.
|
||||
This driver requires Almazny hardware revision v1.2 or later
|
||||
and Mirny CPLD gateware v0.3 or later.
|
||||
Use :class:`artiq.coredevice.almazny.AlmaznyLegacy` for Almazny hardware v1.1 and earlier.
|
||||
|
||||
:param host_mirny: Mirny CPLD device name
|
||||
:param channel: channel index (0-3)
|
||||
"""
|
||||
|
||||
def __init__(self, dmgr, host_mirny, channel):
|
||||
self.channel = channel
|
||||
self.mirny_cpld = dmgr.get(host_mirny)
|
||||
|
||||
@portable
|
||||
def to_mu(self, att, enable, led):
|
||||
"""
|
||||
Convert an attenuation in dB, RF switch state and LED state to machine
|
||||
units.
|
||||
|
||||
:param att: attenuator setting in dB (0-31.5)
|
||||
:param enable: RF switch state (bool)
|
||||
:param led: LED state (bool)
|
||||
:return: channel setting in machine units
|
||||
"""
|
||||
mu = int32(round(att * 2.))
|
||||
if mu >= 64 or mu < 0:
|
||||
raise ValueError("Attenuation out of range")
|
||||
# unfortunate hardware design: bit reverse
|
||||
mu = ((mu & 0x15) << 1) | ((mu >> 1) & 0x15)
|
||||
mu = ((mu & 0x03) << 4) | (mu & 0x0c) | ((mu >> 4) & 0x03)
|
||||
if enable:
|
||||
mu |= 1 << 6
|
||||
if led:
|
||||
mu |= 1 << 7
|
||||
return mu
|
||||
|
||||
@kernel
|
||||
def set_mu(self, mu):
|
||||
"""
|
||||
Set channel state (machine units).
|
||||
|
||||
:param mu: channel state in machine units.
|
||||
"""
|
||||
self.mirny_cpld.write_ext(
|
||||
addr=0xc + self.channel, length=8, data=mu, ext_div=32)
|
||||
|
||||
@kernel
|
||||
def set(self, att, enable, led=False):
|
||||
"""
|
||||
Set attenuation, RF switch, and LED state (SI units).
|
||||
|
||||
:param att: attenuator setting in dB (0-31.5)
|
||||
:param enable: RF switch state (bool)
|
||||
:param led: LED state (bool)
|
||||
"""
|
||||
self.set_mu(self.to_mu(att, enable, led))
|
||||
|
|
@ -2,11 +2,11 @@ from artiq.language.core import *
|
|||
from artiq.language.types import *
|
||||
|
||||
|
||||
@syscall(flags={"nounwind"})
|
||||
@syscall(flags={"nounwind", "nowrite"})
|
||||
def cache_get(key: TStr) -> TList(TInt32):
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
@syscall
|
||||
@syscall(flags={"nowrite"})
|
||||
def cache_put(key: TStr, value: TList(TInt32)) -> TNone:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,37 @@
|
|||
import sys
|
||||
import socket
|
||||
import logging
|
||||
|
||||
|
||||
logger = logging.getLogger(__name__)
|
||||
|
||||
|
||||
def set_keepalive(sock, after_idle, interval, max_fails):
|
||||
if sys.platform.startswith("linux"):
|
||||
sock.setsockopt(socket.SOL_SOCKET, socket.SO_KEEPALIVE, 1)
|
||||
sock.setsockopt(socket.IPPROTO_TCP, socket.TCP_KEEPIDLE, after_idle)
|
||||
sock.setsockopt(socket.IPPROTO_TCP, socket.TCP_KEEPINTVL, interval)
|
||||
sock.setsockopt(socket.IPPROTO_TCP, socket.TCP_KEEPCNT, max_fails)
|
||||
elif sys.platform.startswith("win") or sys.platform.startswith("cygwin"):
|
||||
# setting max_fails is not supported, typically ends up being 5 or 10
|
||||
# depending on Windows version
|
||||
sock.ioctl(socket.SIO_KEEPALIVE_VALS,
|
||||
(1, after_idle*1000, interval*1000))
|
||||
else:
|
||||
logger.warning("TCP keepalive not supported on platform '%s', ignored",
|
||||
sys.platform)
|
||||
|
||||
|
||||
def initialize_connection(host, port, ssh_transport=None):
|
||||
if ssh_transport is None:
|
||||
sock = socket.create_connection((host, port), 5.0)
|
||||
sock.settimeout(None)
|
||||
set_keepalive(sock, 3, 2, 3)
|
||||
logger.debug("connected to %s:%d", host, port)
|
||||
else:
|
||||
sock = ssh_transport.open_channel("direct-tcpip", (host, port),
|
||||
("localhost", 9999), timeout=5.0)
|
||||
ssh_transport.set_keepalive(2)
|
||||
logger.debug("connected to %s:%d via SSH transport to %s:%d",
|
||||
host, port, *ssh_transport.getpeername())
|
||||
return sock
|
||||
|
|
@ -90,28 +90,18 @@ DecodedDump = namedtuple(
|
|||
|
||||
|
||||
def decode_dump(data):
|
||||
# extract endian byte
|
||||
if data[0] == ord('E'):
|
||||
endian = '>'
|
||||
elif data[0] == ord('e'):
|
||||
endian = '<'
|
||||
else:
|
||||
raise ValueError
|
||||
data = data[1:]
|
||||
# only header is device endian
|
||||
# messages are big endian
|
||||
parts = struct.unpack(endian + "IQbbb", data[:15])
|
||||
parts = struct.unpack(">IQbbb", data[:15])
|
||||
(sent_bytes, total_byte_count,
|
||||
error_occurred, log_channel, dds_onehot_sel) = parts
|
||||
overflow_occured, log_channel, dds_onehot_sel) = parts
|
||||
|
||||
expected_len = sent_bytes + 15
|
||||
if expected_len != len(data):
|
||||
raise ValueError("analyzer dump has incorrect length "
|
||||
"(got {}, expected {})".format(
|
||||
len(data), expected_len))
|
||||
if error_occurred:
|
||||
logger.warning("error occurred within the analyzer, "
|
||||
"data may be corrupted")
|
||||
if overflow_occured:
|
||||
logger.warning("analyzer FIFO overflow occured, "
|
||||
"some messages have been lost")
|
||||
if total_byte_count > sent_bytes:
|
||||
logger.info("analyzer ring buffer has wrapped %d times",
|
||||
total_byte_count//sent_bytes)
|
||||
|
|
@ -370,8 +360,8 @@ class SPIMaster2Handler(WishboneHandler):
|
|||
def process_message(self, message):
|
||||
self.stb.set_value("1")
|
||||
self.stb.set_value("0")
|
||||
data = message.data
|
||||
if isinstance(message, OutputMessage):
|
||||
data = message.data
|
||||
address = message.address
|
||||
if address == 1:
|
||||
logger.debug("SPI config @%d data=0x%08x",
|
||||
|
|
@ -472,7 +462,7 @@ def get_ref_period(devices):
|
|||
|
||||
def get_dds_sysclk(devices):
|
||||
return get_single_device_argument(devices, "artiq.coredevice.ad9914",
|
||||
("AD9914",), "sysclk")
|
||||
("ad9914",), "sysclk")
|
||||
|
||||
|
||||
def create_channel_handlers(vcd_manager, devices, ref_period,
|
||||
|
|
@ -495,7 +485,8 @@ def create_channel_handlers(vcd_manager, devices, ref_period,
|
|||
if dds_bus_channel in channel_handlers:
|
||||
dds_handler = channel_handlers[dds_bus_channel]
|
||||
else:
|
||||
dds_handler = DDSHandler(vcd_manager, dds_onehot_sel, dds_sysclk)
|
||||
dds_handler = DDSHandler(vcd_manager, desc["class"],
|
||||
dds_onehot_sel, dds_sysclk)
|
||||
channel_handlers[dds_bus_channel] = dds_handler
|
||||
dds_handler.add_dds_channel(name, dds_channel)
|
||||
if (desc["module"] == "artiq.coredevice.spi2" and
|
||||
|
|
@ -510,13 +501,11 @@ def get_message_time(message):
|
|||
return getattr(message, "timestamp", message.rtio_counter)
|
||||
|
||||
|
||||
def decoded_dump_to_vcd(fileobj, devices, dump, uniform_interval=False):
|
||||
def decoded_dump_to_vcd(fileobj, devices, dump):
|
||||
vcd_manager = VCDManager(fileobj)
|
||||
ref_period = get_ref_period(devices)
|
||||
|
||||
if ref_period is not None:
|
||||
if not uniform_interval:
|
||||
vcd_manager.set_timescale_ps(ref_period*1e12)
|
||||
vcd_manager.set_timescale_ps(ref_period*1e12)
|
||||
else:
|
||||
logger.warning("unable to determine core device ref_period")
|
||||
ref_period = 1e-9 # guess
|
||||
|
|
@ -538,12 +527,6 @@ def decoded_dump_to_vcd(fileobj, devices, dump, uniform_interval=False):
|
|||
vcd_log_channels = get_vcd_log_channels(dump.log_channel, messages)
|
||||
channel_handlers[dump.log_channel] = LogHandler(
|
||||
vcd_manager, vcd_log_channels)
|
||||
if uniform_interval:
|
||||
# RTIO event timestamp in machine units
|
||||
timestamp = vcd_manager.get_channel("timestamp", 64)
|
||||
# RTIO time interval between this and the next timed event
|
||||
# in SI seconds
|
||||
interval = vcd_manager.get_channel("interval", 64)
|
||||
slack = vcd_manager.get_channel("rtio_slack", 64)
|
||||
|
||||
vcd_manager.set_time(0)
|
||||
|
|
@ -553,18 +536,11 @@ def decoded_dump_to_vcd(fileobj, devices, dump, uniform_interval=False):
|
|||
if start_time:
|
||||
break
|
||||
|
||||
t0 = 0
|
||||
for i, message in enumerate(messages):
|
||||
for message in messages:
|
||||
if message.channel in channel_handlers:
|
||||
t = get_message_time(message) - start_time
|
||||
if t >= 0:
|
||||
if uniform_interval:
|
||||
interval.set_value_double((t - t0)*ref_period)
|
||||
vcd_manager.set_time(i)
|
||||
timestamp.set_value("{:064b}".format(t))
|
||||
t0 = t
|
||||
else:
|
||||
vcd_manager.set_time(t)
|
||||
vcd_manager.set_time(t)
|
||||
channel_handlers[message.channel].process_message(message)
|
||||
if isinstance(message, OutputMessage):
|
||||
slack.set_value_double(
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@ import struct
|
|||
import logging
|
||||
import traceback
|
||||
import numpy
|
||||
import socket
|
||||
from enum import Enum
|
||||
from fractions import Fraction
|
||||
from collections import namedtuple
|
||||
|
||||
from artiq.coredevice import exceptions
|
||||
from artiq.coredevice.comm import initialize_connection
|
||||
from artiq import __version__ as software_version
|
||||
from sipyco.keepalive import create_connection
|
||||
|
||||
|
||||
logger = logging.getLogger(__name__)
|
||||
|
||||
|
|
@ -23,8 +23,6 @@ class Request(Enum):
|
|||
RPCReply = 7
|
||||
RPCException = 8
|
||||
|
||||
SubkernelUpload = 9
|
||||
|
||||
|
||||
class Reply(Enum):
|
||||
SystemInfo = 2
|
||||
|
|
@ -38,17 +36,16 @@ class Reply(Enum):
|
|||
|
||||
RPCRequest = 10
|
||||
|
||||
WatchdogExpired = 14
|
||||
ClockFailure = 15
|
||||
|
||||
|
||||
class UnsupportedDevice(Exception):
|
||||
pass
|
||||
|
||||
|
||||
class LoadError(Exception):
|
||||
pass
|
||||
|
||||
|
||||
class RPCReturnValueError(ValueError):
|
||||
pass
|
||||
|
||||
|
|
@ -56,105 +53,6 @@ class RPCReturnValueError(ValueError):
|
|||
RPCKeyword = namedtuple('RPCKeyword', ['name', 'value'])
|
||||
|
||||
|
||||
def _receive_fraction(kernel, embedding_map):
|
||||
numerator = kernel._read_int64()
|
||||
denominator = kernel._read_int64()
|
||||
return Fraction(numerator, denominator)
|
||||
|
||||
|
||||
def _receive_list(kernel, embedding_map):
|
||||
length = kernel._read_int32()
|
||||
tag = chr(kernel._read_int8())
|
||||
if tag == "b":
|
||||
buffer = kernel._read(length)
|
||||
return list(struct.unpack(kernel.endian + "%s?" % length, buffer))
|
||||
elif tag == "i":
|
||||
buffer = kernel._read(4 * length)
|
||||
return list(struct.unpack(kernel.endian + "%sl" % length, buffer))
|
||||
elif tag == "I":
|
||||
buffer = kernel._read(8 * length)
|
||||
return list(numpy.ndarray((length, ), kernel.endian + 'i8', buffer))
|
||||
elif tag == "f":
|
||||
buffer = kernel._read(8 * length)
|
||||
return list(struct.unpack(kernel.endian + "%sd" % length, buffer))
|
||||
else:
|
||||
fn = receivers[tag]
|
||||
elems = []
|
||||
for _ in range(length):
|
||||
# discard tag, as our device would still send the tag for each
|
||||
# non-primitive elements.
|
||||
kernel._read_int8()
|
||||
item = fn(kernel, embedding_map)
|
||||
elems.append(item)
|
||||
return elems
|
||||
|
||||
|
||||
def _receive_array(kernel, embedding_map):
|
||||
num_dims = kernel._read_int8()
|
||||
shape = tuple(kernel._read_int32() for _ in range(num_dims))
|
||||
tag = chr(kernel._read_int8())
|
||||
fn = receivers[tag]
|
||||
length = numpy.prod(shape)
|
||||
if tag == "b":
|
||||
buffer = kernel._read(length)
|
||||
elems = numpy.ndarray((length, ), '?', buffer)
|
||||
elif tag == "i":
|
||||
buffer = kernel._read(4 * length)
|
||||
elems = numpy.ndarray((length, ), kernel.endian + 'i4', buffer)
|
||||
elif tag == "I":
|
||||
buffer = kernel._read(8 * length)
|
||||
elems = numpy.ndarray((length, ), kernel.endian + 'i8', buffer)
|
||||
elif tag == "f":
|
||||
buffer = kernel._read(8 * length)
|
||||
elems = numpy.ndarray((length, ), kernel.endian + 'd', buffer)
|
||||
else:
|
||||
fn = receivers[tag]
|
||||
elems = []
|
||||
for _ in range(numpy.prod(shape)):
|
||||
# discard the tag
|
||||
kernel._read_int8()
|
||||
item = fn(kernel, embedding_map)
|
||||
elems.append(item)
|
||||
elems = numpy.array(elems)
|
||||
return elems.reshape(shape)
|
||||
|
||||
|
||||
def _receive_range(kernel, embedding_map):
|
||||
start = kernel._receive_rpc_value(embedding_map)
|
||||
stop = kernel._receive_rpc_value(embedding_map)
|
||||
step = kernel._receive_rpc_value(embedding_map)
|
||||
return range(start, stop, step)
|
||||
|
||||
|
||||
def _receive_keyword(kernel, embedding_map):
|
||||
name = kernel._read_string()
|
||||
value = kernel._receive_rpc_value(embedding_map)
|
||||
return RPCKeyword(name, value)
|
||||
|
||||
|
||||
receivers = {
|
||||
"\x00": lambda kernel, embedding_map: kernel._rpc_sentinel,
|
||||
"t": lambda kernel, embedding_map:
|
||||
tuple(kernel._receive_rpc_value(embedding_map)
|
||||
for _ in range(kernel._read_int8())),
|
||||
"n": lambda kernel, embedding_map: None,
|
||||
"b": lambda kernel, embedding_map: bool(kernel._read_int8()),
|
||||
"i": lambda kernel, embedding_map: numpy.int32(kernel._read_int32()),
|
||||
"I": lambda kernel, embedding_map: numpy.int64(kernel._read_int64()),
|
||||
"f": lambda kernel, embedding_map: kernel._read_float64(),
|
||||
"s": lambda kernel, embedding_map: kernel._read_string(),
|
||||
"B": lambda kernel, embedding_map: kernel._read_bytes(),
|
||||
"A": lambda kernel, embedding_map: kernel._read_bytes(),
|
||||
"O": lambda kernel, embedding_map:
|
||||
embedding_map.retrieve_object(kernel._read_int32()),
|
||||
"F": _receive_fraction,
|
||||
"l": _receive_list,
|
||||
"a": _receive_array,
|
||||
"r": _receive_range,
|
||||
"k": _receive_keyword
|
||||
}
|
||||
|
||||
|
||||
class CommKernelDummy:
|
||||
def __init__(self):
|
||||
pass
|
||||
|
|
@ -172,16 +70,6 @@ class CommKernelDummy:
|
|||
pass
|
||||
|
||||
|
||||
def incompatible_versions(v1, v2):
|
||||
if v1.endswith(".beta") or v2.endswith(".beta"):
|
||||
# Beta branches may introduce breaking changes. Check version strictly.
|
||||
return v1 != v2
|
||||
else:
|
||||
# On stable branches, runtime/software protocol backward compatibility is kept.
|
||||
# Runtime and software with the same major version number are compatible.
|
||||
return v1.split(".", maxsplit=1)[0] != v2.split(".", maxsplit=1)[0]
|
||||
|
||||
|
||||
class CommKernel:
|
||||
warned_of_mismatch = False
|
||||
|
||||
|
|
@ -189,31 +77,12 @@ class CommKernel:
|
|||
self._read_type = None
|
||||
self.host = host
|
||||
self.port = port
|
||||
self.read_buffer = bytearray()
|
||||
self.write_buffer = bytearray()
|
||||
|
||||
|
||||
def open(self):
|
||||
def open(self, **kwargs):
|
||||
if hasattr(self, "socket"):
|
||||
return
|
||||
self.socket = create_connection(self.host, self.port)
|
||||
self.socket = initialize_connection(self.host, self.port, **kwargs)
|
||||
self.socket.sendall(b"ARTIQ coredev\n")
|
||||
endian = self._read(1)
|
||||
if endian == b"e":
|
||||
self.endian = "<"
|
||||
elif endian == b"E":
|
||||
self.endian = ">"
|
||||
else:
|
||||
raise IOError("Incorrect reply from device: expected e/E.")
|
||||
self.unpack_int32 = struct.Struct(self.endian + "l").unpack
|
||||
self.unpack_int64 = struct.Struct(self.endian + "q").unpack
|
||||
self.unpack_float64 = struct.Struct(self.endian + "d").unpack
|
||||
|
||||
self.pack_header = struct.Struct(self.endian + "lB").pack
|
||||
self.pack_int8 = struct.Struct(self.endian + "B").pack
|
||||
self.pack_int32 = struct.Struct(self.endian + "l").pack
|
||||
self.pack_int64 = struct.Struct(self.endian + "q").pack
|
||||
self.pack_float64 = struct.Struct(self.endian + "d").pack
|
||||
|
||||
def close(self):
|
||||
if not hasattr(self, "socket"):
|
||||
|
|
@ -222,41 +91,36 @@ class CommKernel:
|
|||
del self.socket
|
||||
logger.debug("disconnected")
|
||||
|
||||
def read(self, length):
|
||||
r = bytes()
|
||||
while len(r) < length:
|
||||
rn = self.socket.recv(min(8192, length - len(r)))
|
||||
if not rn:
|
||||
raise ConnectionResetError("Connection closed")
|
||||
r += rn
|
||||
return r
|
||||
|
||||
def write(self, data):
|
||||
self.socket.sendall(data)
|
||||
|
||||
#
|
||||
# Reader interface
|
||||
#
|
||||
|
||||
def _read(self, length):
|
||||
# cache the reads to avoid frequent call to recv
|
||||
while len(self.read_buffer) < length:
|
||||
# the number is just the maximum amount
|
||||
# when there is not much data, it would return earlier
|
||||
diff = length - len(self.read_buffer)
|
||||
flag = 0
|
||||
if diff > 8192:
|
||||
flag |= socket.MSG_WAITALL
|
||||
new_buffer = self.socket.recv(8192, flag)
|
||||
if not new_buffer:
|
||||
raise ConnectionResetError("Core device connection closed unexpectedly")
|
||||
self.read_buffer += new_buffer
|
||||
result = self.read_buffer[:length]
|
||||
self.read_buffer = self.read_buffer[length:]
|
||||
return result
|
||||
|
||||
def _read_header(self):
|
||||
self.open()
|
||||
|
||||
# Wait for a synchronization sequence, 5a 5a 5a 5a.
|
||||
sync_count = 0
|
||||
while sync_count < 4:
|
||||
sync_byte = self._read(1)[0]
|
||||
(sync_byte, ) = struct.unpack("B", self.read(1))
|
||||
if sync_byte == 0x5a:
|
||||
sync_count += 1
|
||||
else:
|
||||
sync_count = 0
|
||||
|
||||
# Read message header.
|
||||
raw_type = self._read(1)[0]
|
||||
(raw_type, ) = struct.unpack("B", self.read(1))
|
||||
self._read_type = Reply(raw_type)
|
||||
|
||||
logger.debug("receiving message: type=%r",
|
||||
|
|
@ -271,26 +135,30 @@ class CommKernel:
|
|||
self._read_header()
|
||||
self._read_expect(ty)
|
||||
|
||||
def _read_chunk(self, length):
|
||||
return self.read(length)
|
||||
|
||||
def _read_int8(self):
|
||||
return self._read(1)[0]
|
||||
(value, ) = struct.unpack("B", self._read_chunk(1))
|
||||
return value
|
||||
|
||||
def _read_int32(self):
|
||||
(value, ) = self.unpack_int32(self._read(4))
|
||||
(value, ) = struct.unpack(">l", self._read_chunk(4))
|
||||
return value
|
||||
|
||||
def _read_int64(self):
|
||||
(value, ) = self.unpack_int64(self._read(8))
|
||||
(value, ) = struct.unpack(">q", self._read_chunk(8))
|
||||
return value
|
||||
|
||||
def _read_float64(self):
|
||||
(value, ) = self.unpack_float64(self._read(8))
|
||||
(value, ) = struct.unpack(">d", self._read_chunk(8))
|
||||
return value
|
||||
|
||||
def _read_bool(self):
|
||||
return True if self._read_int8() else False
|
||||
|
||||
def _read_bytes(self):
|
||||
return self._read(self._read_int32())
|
||||
return self._read_chunk(self._read_int32())
|
||||
|
||||
def _read_string(self):
|
||||
return self._read_bytes().decode("utf-8")
|
||||
|
|
@ -299,49 +167,38 @@ class CommKernel:
|
|||
# Writer interface
|
||||
#
|
||||
|
||||
def _write(self, data):
|
||||
self.write_buffer += data
|
||||
# if the buffer is already pretty large, send it
|
||||
# the block size is arbitrary, tuning it may improve performance
|
||||
if len(self.write_buffer) > 4096:
|
||||
self._flush()
|
||||
|
||||
def _flush(self):
|
||||
self.socket.sendall(self.write_buffer)
|
||||
self.write_buffer.clear()
|
||||
|
||||
def _write_header(self, ty):
|
||||
self.open()
|
||||
|
||||
logger.debug("sending message: type=%r", ty)
|
||||
|
||||
# Write synchronization sequence and header.
|
||||
self._write(self.pack_header(0x5a5a5a5a, ty.value))
|
||||
self.write(struct.pack(">lB", 0x5a5a5a5a, ty.value))
|
||||
|
||||
def _write_empty(self, ty):
|
||||
self._write_header(ty)
|
||||
|
||||
def _write_chunk(self, chunk):
|
||||
self._write(chunk)
|
||||
self.write(chunk)
|
||||
|
||||
def _write_int8(self, value):
|
||||
self._write(self.pack_int8(value))
|
||||
self.write(struct.pack("B", value))
|
||||
|
||||
def _write_int32(self, value):
|
||||
self._write(self.pack_int32(value))
|
||||
self.write(struct.pack(">l", value))
|
||||
|
||||
def _write_int64(self, value):
|
||||
self._write(self.pack_int64(value))
|
||||
self.write(struct.pack(">q", value))
|
||||
|
||||
def _write_float64(self, value):
|
||||
self._write(self.pack_float64(value))
|
||||
self.write(struct.pack(">d", value))
|
||||
|
||||
def _write_bool(self, value):
|
||||
self._write(b'\x01' if value else b'\x00')
|
||||
self.write(struct.pack("B", value))
|
||||
|
||||
def _write_bytes(self, value):
|
||||
self._write_int32(len(value))
|
||||
self._write(value)
|
||||
self.write(value)
|
||||
|
||||
def _write_string(self, value):
|
||||
self._write_bytes(value.encode("utf-8"))
|
||||
|
|
@ -350,47 +207,33 @@ class CommKernel:
|
|||
# Exported APIs
|
||||
#
|
||||
|
||||
def reset_session(self):
|
||||
self.write(struct.pack(">ll", 0x5a5a5a5a, 0))
|
||||
|
||||
def check_system_info(self):
|
||||
self._write_empty(Request.SystemInfo)
|
||||
self._flush()
|
||||
|
||||
self._read_header()
|
||||
self._read_expect(Reply.SystemInfo)
|
||||
runtime_id = self._read(4)
|
||||
if runtime_id == b"AROR":
|
||||
gateware_version = self._read_string().split(";")[0]
|
||||
if not self.warned_of_mismatch and incompatible_versions(gateware_version, software_version):
|
||||
logger.warning("Mismatch between gateware (%s) "
|
||||
"and software (%s) versions",
|
||||
gateware_version, software_version)
|
||||
CommKernel.warned_of_mismatch = True
|
||||
|
||||
finished_cleanly = self._read_bool()
|
||||
if not finished_cleanly:
|
||||
logger.warning("Previous kernel did not cleanly finish")
|
||||
elif runtime_id == b"ARZQ":
|
||||
pass
|
||||
else:
|
||||
runtime_id = self._read_chunk(4)
|
||||
if runtime_id != b"AROR":
|
||||
raise UnsupportedDevice("Unsupported runtime ID: {}"
|
||||
.format(runtime_id))
|
||||
|
||||
gateware_version = self._read_string().split(";")[0]
|
||||
if gateware_version != software_version and not self.warned_of_mismatch:
|
||||
logger.warning("Mismatch between gateware (%s) "
|
||||
"and software (%s) versions",
|
||||
gateware_version, software_version)
|
||||
CommKernel.warned_of_mismatch = True
|
||||
|
||||
finished_cleanly = self._read_bool()
|
||||
if not finished_cleanly:
|
||||
logger.warning("Previous kernel did not cleanly finish")
|
||||
|
||||
def load(self, kernel_library):
|
||||
self._write_header(Request.LoadKernel)
|
||||
self._write_bytes(kernel_library)
|
||||
self._flush()
|
||||
|
||||
self._read_header()
|
||||
if self._read_type == Reply.LoadFailed:
|
||||
raise LoadError(self._read_string())
|
||||
else:
|
||||
self._read_expect(Reply.LoadCompleted)
|
||||
|
||||
def upload_subkernel(self, kernel_library, id, destination):
|
||||
self._write_header(Request.SubkernelUpload)
|
||||
self._write_int32(id)
|
||||
self._write_int8(destination)
|
||||
self._write_bytes(kernel_library)
|
||||
self._flush()
|
||||
|
||||
self._read_header()
|
||||
if self._read_type == Reply.LoadFailed:
|
||||
|
|
@ -400,16 +243,55 @@ class CommKernel:
|
|||
|
||||
def run(self):
|
||||
self._write_empty(Request.RunKernel)
|
||||
self._flush()
|
||||
logger.debug("running kernel")
|
||||
|
||||
_rpc_sentinel = object()
|
||||
|
||||
# See rpc_proto.rs and compiler/ir.py:rpc_tag.
|
||||
# See session.c:{send,receive}_rpc_value and llvm_ir_generator.py:_rpc_tag.
|
||||
def _receive_rpc_value(self, embedding_map):
|
||||
tag = chr(self._read_int8())
|
||||
if tag in receivers:
|
||||
return receivers.get(tag)(self, embedding_map)
|
||||
if tag == "\x00":
|
||||
return self._rpc_sentinel
|
||||
elif tag == "t":
|
||||
length = self._read_int8()
|
||||
return tuple(self._receive_rpc_value(embedding_map) for _ in range(length))
|
||||
elif tag == "n":
|
||||
return None
|
||||
elif tag == "b":
|
||||
return bool(self._read_int8())
|
||||
elif tag == "i":
|
||||
return numpy.int32(self._read_int32())
|
||||
elif tag == "I":
|
||||
return numpy.int64(self._read_int64())
|
||||
elif tag == "f":
|
||||
return self._read_float64()
|
||||
elif tag == "F":
|
||||
numerator = self._read_int64()
|
||||
denominator = self._read_int64()
|
||||
return Fraction(numerator, denominator)
|
||||
elif tag == "s":
|
||||
return self._read_string()
|
||||
elif tag == "B":
|
||||
return self._read_bytes()
|
||||
elif tag == "A":
|
||||
return self._read_bytes()
|
||||
elif tag == "l":
|
||||
length = self._read_int32()
|
||||
return [self._receive_rpc_value(embedding_map) for _ in range(length)]
|
||||
elif tag == "a":
|
||||
length = self._read_int32()
|
||||
return numpy.array([self._receive_rpc_value(embedding_map) for _ in range(length)])
|
||||
elif tag == "r":
|
||||
start = self._receive_rpc_value(embedding_map)
|
||||
stop = self._receive_rpc_value(embedding_map)
|
||||
step = self._receive_rpc_value(embedding_map)
|
||||
return range(start, stop, step)
|
||||
elif tag == "k":
|
||||
name = self._read_string()
|
||||
value = self._receive_rpc_value(embedding_map)
|
||||
return RPCKeyword(name, value)
|
||||
elif tag == "O":
|
||||
return embedding_map.retrieve_object(self._read_int32())
|
||||
else:
|
||||
raise IOError("Unknown RPC value tag: {}".format(repr(tag)))
|
||||
|
||||
|
|
@ -425,7 +307,7 @@ class CommKernel:
|
|||
args.append(value)
|
||||
|
||||
def _skip_rpc_value(self, tags):
|
||||
tag = chr(tags.pop(0))
|
||||
tag = tags.pop(0)
|
||||
if tag == "t":
|
||||
length = tags.pop(0)
|
||||
for _ in range(length):
|
||||
|
|
@ -434,9 +316,6 @@ class CommKernel:
|
|||
self._skip_rpc_value(tags)
|
||||
elif tag == "r":
|
||||
self._skip_rpc_value(tags)
|
||||
elif tag == "a":
|
||||
_ndims = tags.pop(0)
|
||||
self._skip_rpc_value(tags)
|
||||
else:
|
||||
pass
|
||||
|
||||
|
|
@ -462,15 +341,15 @@ class CommKernel:
|
|||
elif tag == "b":
|
||||
check(isinstance(value, bool),
|
||||
lambda: "bool")
|
||||
self._write_bool(value)
|
||||
self._write_int8(value)
|
||||
elif tag == "i":
|
||||
check(isinstance(value, (int, numpy.int32)) and
|
||||
(-2**31 <= value < 2**31),
|
||||
(-2**31 < value < 2**31-1),
|
||||
lambda: "32-bit int")
|
||||
self._write_int32(value)
|
||||
elif tag == "I":
|
||||
check(isinstance(value, (int, numpy.int32, numpy.int64)) and
|
||||
(-2**63 <= value < 2**63),
|
||||
(-2**63 < value < 2**63-1),
|
||||
lambda: "64-bit int")
|
||||
self._write_int64(value)
|
||||
elif tag == "f":
|
||||
|
|
@ -479,8 +358,8 @@ class CommKernel:
|
|||
self._write_float64(value)
|
||||
elif tag == "F":
|
||||
check(isinstance(value, Fraction) and
|
||||
(-2**63 <= value.numerator < 2**63) and
|
||||
(-2**63 <= value.denominator < 2**63),
|
||||
(-2**63 < value.numerator < 2**63-1) and
|
||||
(-2**63 < value.denominator < 2**63-1),
|
||||
lambda: "64-bit Fraction")
|
||||
self._write_int64(value.numerator)
|
||||
self._write_int64(value.denominator)
|
||||
|
|
@ -500,58 +379,9 @@ class CommKernel:
|
|||
check(isinstance(value, list),
|
||||
lambda: "list")
|
||||
self._write_int32(len(value))
|
||||
tag_element = chr(tags[0])
|
||||
if tag_element == "b":
|
||||
self._write(bytes(value))
|
||||
elif tag_element == "i":
|
||||
try:
|
||||
self._write(struct.pack(self.endian + "%sl" % len(value), *value))
|
||||
except struct.error:
|
||||
raise RPCReturnValueError(
|
||||
"type mismatch: cannot serialize {value} as {type}".format(
|
||||
value=repr(value), type="32-bit integer list"))
|
||||
elif tag_element == "I":
|
||||
try:
|
||||
self._write(struct.pack(self.endian + "%sq" % len(value), *value))
|
||||
except struct.error:
|
||||
raise RPCReturnValueError(
|
||||
"type mismatch: cannot serialize {value} as {type}".format(
|
||||
value=repr(value), type="64-bit integer list"))
|
||||
elif tag_element == "f":
|
||||
self._write(struct.pack(self.endian + "%sd" %
|
||||
len(value), *value))
|
||||
else:
|
||||
for elt in value:
|
||||
tags_copy = bytearray(tags)
|
||||
self._send_rpc_value(tags_copy, elt, root, function)
|
||||
self._skip_rpc_value(tags)
|
||||
elif tag == "a":
|
||||
check(isinstance(value, numpy.ndarray),
|
||||
lambda: "numpy.ndarray")
|
||||
num_dims = tags.pop(0)
|
||||
check(num_dims == len(value.shape),
|
||||
lambda: "{}-dimensional numpy.ndarray".format(num_dims))
|
||||
for s in value.shape:
|
||||
self._write_int32(s)
|
||||
tag_element = chr(tags[0])
|
||||
if tag_element == "b":
|
||||
self._write(value.reshape((-1,), order="C").tobytes())
|
||||
elif tag_element == "i":
|
||||
array = value.reshape(
|
||||
(-1,), order="C").astype(self.endian + 'i4')
|
||||
self._write(array.tobytes())
|
||||
elif tag_element == "I":
|
||||
array = value.reshape(
|
||||
(-1,), order="C").astype(self.endian + 'i8')
|
||||
self._write(array.tobytes())
|
||||
elif tag_element == "f":
|
||||
array = value.reshape(
|
||||
(-1,), order="C").astype(self.endian + 'd')
|
||||
self._write(array.tobytes())
|
||||
else:
|
||||
for elt in value.reshape((-1,), order="C"):
|
||||
tags_copy = bytearray(tags)
|
||||
self._send_rpc_value(tags_copy, elt, root, function)
|
||||
for elt in value:
|
||||
tags_copy = bytearray(tags)
|
||||
self._send_rpc_value(tags_copy, elt, root, function)
|
||||
self._skip_rpc_value(tags)
|
||||
elif tag == "r":
|
||||
check(isinstance(value, range),
|
||||
|
|
@ -573,59 +403,59 @@ class CommKernel:
|
|||
return msg
|
||||
|
||||
def _serve_rpc(self, embedding_map):
|
||||
is_async = self._read_bool()
|
||||
service_id = self._read_int32()
|
||||
async = self._read_bool()
|
||||
service_id = self._read_int32()
|
||||
args, kwargs = self._receive_rpc_args(embedding_map)
|
||||
return_tags = self._read_bytes()
|
||||
return_tags = self._read_bytes()
|
||||
|
||||
if service_id == 0:
|
||||
def service(obj, attr, value): return setattr(obj, attr, value)
|
||||
if service_id is 0:
|
||||
service = lambda obj, attr, value: setattr(obj, attr, value)
|
||||
else:
|
||||
service = embedding_map.retrieve_object(service_id)
|
||||
service = embedding_map.retrieve_object(service_id)
|
||||
logger.debug("rpc service: [%d]%r%s %r %r -> %s", service_id, service,
|
||||
(" (async)" if is_async else ""), args, kwargs, return_tags)
|
||||
(" (async)" if async else ""), args, kwargs, return_tags)
|
||||
|
||||
if is_async:
|
||||
if async:
|
||||
service(*args, **kwargs)
|
||||
return
|
||||
|
||||
try:
|
||||
result = service(*args, **kwargs)
|
||||
logger.debug("rpc service: %d %r %r = %r", service_id, args, kwargs, result)
|
||||
|
||||
self._write_header(Request.RPCReply)
|
||||
self._write_bytes(return_tags)
|
||||
self._send_rpc_value(bytearray(return_tags), result, result, service)
|
||||
except RPCReturnValueError as exn:
|
||||
raise
|
||||
except Exception as exn:
|
||||
logger.debug("rpc service: %d %r %r ! %r",
|
||||
service_id, args, kwargs, exn)
|
||||
logger.debug("rpc service: %d %r %r ! %r", service_id, args, kwargs, exn)
|
||||
|
||||
self._write_header(Request.RPCException)
|
||||
|
||||
# Note: instead of sending strings, we send object ID
|
||||
# This is to avoid the need of allocatio on the device side
|
||||
# This is a special case: this only applies to exceptions
|
||||
if hasattr(exn, "artiq_core_exception"):
|
||||
exn = exn.artiq_core_exception
|
||||
self._write_int32(embedding_map.store_str(exn.name))
|
||||
self._write_int32(embedding_map.store_str(self._truncate_message(exn.message)))
|
||||
self._write_string(exn.name)
|
||||
self._write_string(self._truncate_message(exn.message))
|
||||
for index in range(3):
|
||||
self._write_int64(exn.param[index])
|
||||
|
||||
filename, line, column, function = exn.traceback[-1]
|
||||
self._write_int32(embedding_map.store_str(filename))
|
||||
self._write_string(filename)
|
||||
self._write_int32(line)
|
||||
self._write_int32(column)
|
||||
self._write_int32(embedding_map.store_str(function))
|
||||
self._write_string(function)
|
||||
else:
|
||||
exn_type = type(exn)
|
||||
if exn_type in (ZeroDivisionError, ValueError, IndexError, RuntimeError) or \
|
||||
hasattr(exn, "artiq_builtin"):
|
||||
name = "0:{}".format(exn_type.__name__)
|
||||
self._write_string("0:{}".format(exn_type.__name__))
|
||||
else:
|
||||
exn_id = embedding_map.store_object(exn_type)
|
||||
name = "{}:{}.{}".format(exn_id,
|
||||
exn_type.__module__,
|
||||
exn_type.__qualname__)
|
||||
self._write_int32(embedding_map.store_str(name))
|
||||
self._write_int32(embedding_map.store_str(self._truncate_message(str(exn))))
|
||||
self._write_string("{}:{}.{}".format(exn_id,
|
||||
exn_type.__module__,
|
||||
exn_type.__qualname__))
|
||||
self._write_string(self._truncate_message(str(exn)))
|
||||
for index in range(3):
|
||||
self._write_int64(0)
|
||||
|
||||
|
|
@ -636,93 +466,36 @@ class CommKernel:
|
|||
((filename, line, function, _), ) = tb
|
||||
else:
|
||||
assert False
|
||||
self._write_int32(embedding_map.store_str(filename))
|
||||
self._write_string(filename)
|
||||
self._write_int32(line)
|
||||
self._write_int32(-1) # column not known
|
||||
self._write_int32(embedding_map.store_str(function))
|
||||
self._flush()
|
||||
else:
|
||||
logger.debug("rpc service: %d %r %r = %r",
|
||||
service_id, args, kwargs, result)
|
||||
self._write_header(Request.RPCReply)
|
||||
self._write_bytes(return_tags)
|
||||
self._send_rpc_value(bytearray(return_tags),
|
||||
result, result, service)
|
||||
self._flush()
|
||||
self._write_int32(-1) # column not known
|
||||
self._write_string(function)
|
||||
|
||||
def _serve_exception(self, embedding_map, symbolizer, demangler):
|
||||
exception_count = self._read_int32()
|
||||
nested_exceptions = []
|
||||
name = self._read_string()
|
||||
message = self._read_string()
|
||||
params = [self._read_int64() for _ in range(3)]
|
||||
|
||||
def read_exception_string():
|
||||
# note: if length == -1, the following int32 is the object key
|
||||
length = self._read_int32()
|
||||
if length == -1:
|
||||
return embedding_map.retrieve_str(self._read_int32())
|
||||
else:
|
||||
return self._read(length).decode("utf-8")
|
||||
filename = self._read_string()
|
||||
line = self._read_int32()
|
||||
column = self._read_int32()
|
||||
function = self._read_string()
|
||||
|
||||
for _ in range(exception_count):
|
||||
name = embedding_map.retrieve_str(self._read_int32())
|
||||
message = read_exception_string()
|
||||
params = [self._read_int64() for _ in range(3)]
|
||||
backtrace = [self._read_int32() for _ in range(self._read_int32())]
|
||||
|
||||
filename = read_exception_string()
|
||||
line = self._read_int32()
|
||||
column = self._read_int32()
|
||||
function = read_exception_string()
|
||||
nested_exceptions.append([name, message, params,
|
||||
filename, line, column, function])
|
||||
|
||||
demangled_names = demangler([ex[6] for ex in nested_exceptions])
|
||||
for i in range(exception_count):
|
||||
nested_exceptions[i][6] = demangled_names[i]
|
||||
|
||||
exception_info = []
|
||||
for _ in range(exception_count):
|
||||
sp = self._read_int32()
|
||||
initial_backtrace = self._read_int32()
|
||||
current_backtrace = self._read_int32()
|
||||
exception_info.append((sp, initial_backtrace, current_backtrace))
|
||||
|
||||
backtrace = []
|
||||
stack_pointers = []
|
||||
for _ in range(self._read_int32()):
|
||||
backtrace.append(self._read_int32())
|
||||
stack_pointers.append(self._read_int32())
|
||||
|
||||
self._process_async_error()
|
||||
|
||||
traceback = list(symbolizer(backtrace))
|
||||
core_exn = exceptions.CoreException(nested_exceptions, exception_info,
|
||||
traceback, stack_pointers)
|
||||
traceback = list(reversed(symbolizer(backtrace))) + \
|
||||
[(filename, line, column, *demangler([function]), None)]
|
||||
core_exn = exceptions.CoreException(name, message, params, traceback)
|
||||
|
||||
if core_exn.id == 0:
|
||||
python_exn_type = getattr(exceptions, core_exn.name.split('.')[-1])
|
||||
else:
|
||||
python_exn_type = embedding_map.retrieve_object(core_exn.id)
|
||||
|
||||
try:
|
||||
python_exn = python_exn_type(
|
||||
nested_exceptions[-1][1].format(*nested_exceptions[0][2]))
|
||||
except Exception as ex:
|
||||
python_exn = RuntimeError(
|
||||
f"Exception type={python_exn_type}, which couldn't be "
|
||||
f"reconstructed ({ex})"
|
||||
)
|
||||
python_exn = python_exn_type(message.format(*params))
|
||||
python_exn.artiq_core_exception = core_exn
|
||||
raise python_exn
|
||||
|
||||
def _process_async_error(self):
|
||||
errors = self._read_int8()
|
||||
if errors > 0:
|
||||
map_name = lambda y, z: [f"{y}(s)"] if z else []
|
||||
errors = map_name("collision", errors & 2 ** 0) + \
|
||||
map_name("busy error", errors & 2 ** 1) + \
|
||||
map_name("sequence error", errors & 2 ** 2)
|
||||
logger.warning(f"{(', '.join(errors[:-1]) + ' and ') if len(errors) > 1 else ''}{errors[-1]} "
|
||||
f"reported during kernel execution")
|
||||
|
||||
def serve(self, embedding_map, symbolizer, demangler):
|
||||
while True:
|
||||
self._read_header()
|
||||
|
|
@ -730,9 +503,10 @@ class CommKernel:
|
|||
self._serve_rpc(embedding_map)
|
||||
elif self._read_type == Reply.KernelException:
|
||||
self._serve_exception(embedding_map, symbolizer, demangler)
|
||||
elif self._read_type == Reply.WatchdogExpired:
|
||||
raise exceptions.WatchdogExpired
|
||||
elif self._read_type == Reply.ClockFailure:
|
||||
raise exceptions.ClockFailure
|
||||
else:
|
||||
self._read_expect(Reply.KernelFinished)
|
||||
self._process_async_error()
|
||||
return
|
||||
|
|
|
|||
|
|
@ -1,8 +1,10 @@
|
|||
from enum import Enum
|
||||
import logging
|
||||
import socket
|
||||
import struct
|
||||
|
||||
from sipyco.keepalive import create_connection
|
||||
from artiq.coredevice.comm import initialize_connection
|
||||
|
||||
|
||||
logger = logging.getLogger(__name__)
|
||||
|
||||
|
|
@ -19,6 +21,11 @@ class Request(Enum):
|
|||
ConfigRemove = 14
|
||||
ConfigErase = 15
|
||||
|
||||
StartProfiler = 9
|
||||
StopProfiler = 10
|
||||
GetProfile = 11
|
||||
|
||||
Hotswap = 4
|
||||
Reboot = 5
|
||||
|
||||
DebugAllocator = 8
|
||||
|
|
@ -33,6 +40,8 @@ class Reply(Enum):
|
|||
|
||||
ConfigData = 7
|
||||
|
||||
Profile = 5
|
||||
|
||||
RebootImminent = 3
|
||||
|
||||
|
||||
|
|
@ -50,18 +59,11 @@ class CommMgmt:
|
|||
self.host = host
|
||||
self.port = port
|
||||
|
||||
def open(self):
|
||||
def open(self, **kwargs):
|
||||
if hasattr(self, "socket"):
|
||||
return
|
||||
self.socket = create_connection(self.host, self.port)
|
||||
self.socket = initialize_connection(self.host, self.port, **kwargs)
|
||||
self.socket.sendall(b"ARTIQ management\n")
|
||||
endian = self._read(1)
|
||||
if endian == b"e":
|
||||
self.endian = "<"
|
||||
elif endian == b"E":
|
||||
self.endian = ">"
|
||||
else:
|
||||
raise IOError("Incorrect reply from device: expected e/E.")
|
||||
|
||||
def close(self):
|
||||
if not hasattr(self, "socket"):
|
||||
|
|
@ -85,7 +87,7 @@ class CommMgmt:
|
|||
self._write(struct.pack("B", value))
|
||||
|
||||
def _write_int32(self, value):
|
||||
self._write(struct.pack(self.endian + "l", value))
|
||||
self._write(struct.pack(">l", value))
|
||||
|
||||
def _write_bytes(self, value):
|
||||
self._write_int32(len(value))
|
||||
|
|
@ -110,13 +112,12 @@ class CommMgmt:
|
|||
return ty
|
||||
|
||||
def _read_expect(self, ty):
|
||||
header = self._read_header()
|
||||
if header != ty:
|
||||
if self._read_header() != ty:
|
||||
raise IOError("Incorrect reply from device: {} (expected {})".
|
||||
format(header, ty))
|
||||
format(self._read_type, ty))
|
||||
|
||||
def _read_int32(self):
|
||||
(value, ) = struct.unpack(self.endian + "l", self._read(4))
|
||||
(value, ) = struct.unpack(">l", self._read(4))
|
||||
return value
|
||||
|
||||
def _read_bytes(self):
|
||||
|
|
@ -160,12 +161,7 @@ class CommMgmt:
|
|||
def config_read(self, key):
|
||||
self._write_header(Request.ConfigRead)
|
||||
self._write_string(key)
|
||||
ty = self._read_header()
|
||||
if ty == Reply.Error:
|
||||
raise IOError("Device failed to read config. The key may not exist.")
|
||||
elif ty != Reply.ConfigData:
|
||||
raise IOError("Incorrect reply from device: {} (expected {})".
|
||||
format(ty, Reply.ConfigData))
|
||||
self._read_expect(Reply.ConfigData)
|
||||
return self._read_string()
|
||||
|
||||
def config_write(self, key, value):
|
||||
|
|
@ -174,7 +170,7 @@ class CommMgmt:
|
|||
self._write_bytes(value)
|
||||
ty = self._read_header()
|
||||
if ty == Reply.Error:
|
||||
raise IOError("Device failed to write config. More information may be available in the log.")
|
||||
raise IOError("Flash storage is full")
|
||||
elif ty != Reply.Success:
|
||||
raise IOError("Incorrect reply from device: {} (expected {})".
|
||||
format(ty, Reply.Success))
|
||||
|
|
@ -188,6 +184,45 @@ class CommMgmt:
|
|||
self._write_header(Request.ConfigErase)
|
||||
self._read_expect(Reply.Success)
|
||||
|
||||
def start_profiler(self, interval, edges_size, hits_size):
|
||||
self._write_header(Request.StartProfiler)
|
||||
self._write_int32(interval)
|
||||
self._write_int32(edges_size)
|
||||
self._write_int32(hits_size)
|
||||
self._read_expect(Reply.Success)
|
||||
|
||||
def stop_profiler(self):
|
||||
self._write_header(Request.StopProfiler)
|
||||
self._read_expect(Reply.Success)
|
||||
|
||||
def stop_profiler(self):
|
||||
self._write_header(Request.StopProfiler)
|
||||
self._read_expect(Reply.Success)
|
||||
|
||||
def get_profile(self):
|
||||
self._write_header(Request.GetProfile)
|
||||
self._read_expect(Reply.Profile)
|
||||
|
||||
hits = {}
|
||||
for _ in range(self._read_int32()):
|
||||
addr = self._read_int32()
|
||||
count = self._read_int32()
|
||||
hits[addr] = count
|
||||
|
||||
edges = {}
|
||||
for _ in range(self._read_int32()):
|
||||
caller = self._read_int32()
|
||||
callee = self._read_int32()
|
||||
count = self._read_int32()
|
||||
edges[(caller, callee)] = count
|
||||
|
||||
return hits, edges
|
||||
|
||||
def hotswap(self, firmware):
|
||||
self._write_header(Request.Hotswap)
|
||||
self._write_bytes(firmware)
|
||||
self._read_expect(Reply.RebootImminent)
|
||||
|
||||
def reboot(self):
|
||||
self._write_header(Request.Reboot)
|
||||
self._read_expect(Reply.RebootImminent)
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@ import logging
|
|||
import struct
|
||||
from enum import Enum
|
||||
|
||||
from sipyco.keepalive import async_open_connection
|
||||
|
||||
__all__ = ["TTLProbe", "TTLOverride", "CommMonInj"]
|
||||
|
||||
|
|
@ -29,14 +28,7 @@ class CommMonInj:
|
|||
self.disconnect_cb = disconnect_cb
|
||||
|
||||
async def connect(self, host, port=1383):
|
||||
self._reader, self._writer = await async_open_connection(
|
||||
host,
|
||||
port,
|
||||
after_idle=1,
|
||||
interval=1,
|
||||
max_fails=3,
|
||||
)
|
||||
|
||||
self._reader, self._writer = await asyncio.open_connection(host, port)
|
||||
try:
|
||||
self._writer.write(b"ARTIQ moninj\n")
|
||||
self._receive_task = asyncio.ensure_future(self._receive_cr())
|
||||
|
|
@ -46,9 +38,6 @@ class CommMonInj:
|
|||
del self._writer
|
||||
raise
|
||||
|
||||
def wait_terminate(self):
|
||||
return self._receive_task
|
||||
|
||||
async def close(self):
|
||||
self.disconnect_cb = None
|
||||
try:
|
||||
|
|
@ -63,19 +52,19 @@ class CommMonInj:
|
|||
del self._writer
|
||||
|
||||
def monitor_probe(self, enable, channel, probe):
|
||||
packet = struct.pack("<bblb", 0, enable, channel, probe)
|
||||
packet = struct.pack(">bblb", 0, enable, channel, probe)
|
||||
self._writer.write(packet)
|
||||
|
||||
def monitor_injection(self, enable, channel, overrd):
|
||||
packet = struct.pack("<bblb", 3, enable, channel, overrd)
|
||||
packet = struct.pack(">bblb", 3, enable, channel, overrd)
|
||||
self._writer.write(packet)
|
||||
|
||||
def inject(self, channel, override, value):
|
||||
packet = struct.pack("<blbb", 1, channel, override, value)
|
||||
packet = struct.pack(">blbb", 1, channel, override, value)
|
||||
self._writer.write(packet)
|
||||
|
||||
def get_injection_status(self, channel, override):
|
||||
packet = struct.pack("<blb", 2, channel, override)
|
||||
packet = struct.pack(">blb", 2, channel, override)
|
||||
self._writer.write(packet)
|
||||
|
||||
async def _receive_cr(self):
|
||||
|
|
@ -85,19 +74,15 @@ class CommMonInj:
|
|||
if not ty:
|
||||
return
|
||||
if ty == b"\x00":
|
||||
payload = await self._reader.readexactly(13)
|
||||
channel, probe, value = struct.unpack("<lbq", payload)
|
||||
payload = await self._reader.read(9)
|
||||
channel, probe, value = struct.unpack(">lbl", payload)
|
||||
self.monitor_cb(channel, probe, value)
|
||||
elif ty == b"\x01":
|
||||
payload = await self._reader.readexactly(6)
|
||||
channel, override, value = struct.unpack("<lbb", payload)
|
||||
payload = await self._reader.read(6)
|
||||
channel, override, value = struct.unpack(">lbb", payload)
|
||||
self.injection_status_cb(channel, override, value)
|
||||
else:
|
||||
raise ValueError("Unknown packet type", ty)
|
||||
except asyncio.CancelledError:
|
||||
raise
|
||||
except:
|
||||
logger.error("Moninj connection terminating with exception", exc_info=True)
|
||||
finally:
|
||||
if self.disconnect_cb is not None:
|
||||
self.disconnect_cb()
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
import os, sys
|
||||
import numpy
|
||||
from inspect import getfullargspec
|
||||
from functools import wraps
|
||||
|
||||
from pythonparser import diagnostic
|
||||
|
||||
|
|
@ -13,7 +11,7 @@ from artiq.language.units import *
|
|||
|
||||
from artiq.compiler.module import Module
|
||||
from artiq.compiler.embedding import Stitcher
|
||||
from artiq.compiler.targets import RV32IMATarget, RV32GTarget, CortexA9Target
|
||||
from artiq.compiler.targets import OR1KTarget
|
||||
|
||||
from artiq.coredevice.comm_kernel import CommKernel, CommKernelDummy
|
||||
# Import for side effects (creating the exception classes).
|
||||
|
|
@ -45,24 +43,13 @@ class CompileError(Exception):
|
|||
def rtio_init() -> TNone:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
@syscall(flags={"nounwind", "nowrite"})
|
||||
def rtio_get_destination_status(linkno: TInt32) -> TBool:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
@syscall(flags={"nounwind", "nowrite"})
|
||||
def rtio_get_counter() -> TInt64:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
|
||||
def get_target_cls(target):
|
||||
if target == "rv32g":
|
||||
return RV32GTarget
|
||||
elif target == "rv32ima":
|
||||
return RV32IMATarget
|
||||
elif target == "cortexa9":
|
||||
return CortexA9Target
|
||||
else:
|
||||
raise ValueError("Unsupported target")
|
||||
@syscall(flags={"nounwind", "nowrite"})
|
||||
def drtio_get_link_status(linkno: TInt32) -> TBool:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
|
||||
class Core:
|
||||
|
|
@ -78,167 +65,76 @@ class Core:
|
|||
:param ref_multiplier: ratio between the RTIO fine timestamp frequency
|
||||
and the RTIO coarse timestamp frequency (e.g. SERDES multiplication
|
||||
factor).
|
||||
:param analyzer_proxy: name of the core device analyzer proxy to trigger
|
||||
(optional).
|
||||
:param analyze_at_run_end: automatically trigger the core device analyzer
|
||||
proxy after the Experiment's run stage finishes.
|
||||
"""
|
||||
|
||||
kernel_invariants = {
|
||||
"core", "ref_period", "coarse_ref_period", "ref_multiplier",
|
||||
}
|
||||
|
||||
def __init__(self, dmgr,
|
||||
host, ref_period,
|
||||
analyzer_proxy=None, analyze_at_run_end=False,
|
||||
ref_multiplier=8,
|
||||
target="rv32g", satellite_cpu_targets={}):
|
||||
def __init__(self, dmgr, host, ref_period, ref_multiplier=8):
|
||||
self.ref_period = ref_period
|
||||
self.ref_multiplier = ref_multiplier
|
||||
self.satellite_cpu_targets = satellite_cpu_targets
|
||||
self.target_cls = get_target_cls(target)
|
||||
self.coarse_ref_period = ref_period*ref_multiplier
|
||||
if host is None:
|
||||
self.comm = CommKernelDummy()
|
||||
else:
|
||||
self.comm = CommKernel(host)
|
||||
self.analyzer_proxy_name = analyzer_proxy
|
||||
self.analyze_at_run_end = analyze_at_run_end
|
||||
|
||||
self.first_run = True
|
||||
self.dmgr = dmgr
|
||||
self.core = self
|
||||
self.comm.core = self
|
||||
self.analyzer_proxy = None
|
||||
|
||||
def notify_run_end(self):
|
||||
if self.analyze_at_run_end:
|
||||
self.trigger_analyzer_proxy()
|
||||
|
||||
def close(self):
|
||||
self.comm.close()
|
||||
|
||||
def compile(self, function, args, kwargs, set_result=None,
|
||||
attribute_writeback=True, print_as_rpc=True,
|
||||
target=None, destination=0, subkernel_arg_types=[]):
|
||||
attribute_writeback=True, print_as_rpc=True):
|
||||
try:
|
||||
engine = _DiagnosticEngine(all_errors_are_fatal=True)
|
||||
|
||||
stitcher = Stitcher(engine=engine, core=self, dmgr=self.dmgr,
|
||||
print_as_rpc=print_as_rpc,
|
||||
destination=destination, subkernel_arg_types=subkernel_arg_types)
|
||||
print_as_rpc=print_as_rpc)
|
||||
stitcher.stitch_call(function, args, kwargs, set_result)
|
||||
stitcher.finalize()
|
||||
|
||||
module = Module(stitcher,
|
||||
ref_period=self.ref_period,
|
||||
attribute_writeback=attribute_writeback)
|
||||
target = target if target is not None else self.target_cls()
|
||||
target = OR1KTarget()
|
||||
|
||||
library = target.compile_and_link([module])
|
||||
stripped_library = target.strip(library)
|
||||
|
||||
return stitcher.embedding_map, stripped_library, \
|
||||
lambda addresses: target.symbolize(library, addresses), \
|
||||
lambda symbols: target.demangle(symbols), \
|
||||
module.subkernel_arg_types
|
||||
lambda symbols: target.demangle(symbols)
|
||||
except diagnostic.Error as error:
|
||||
raise CompileError(error.diagnostic) from error
|
||||
|
||||
def _run_compiled(self, kernel_library, embedding_map, symbolizer, demangler):
|
||||
if self.first_run:
|
||||
self.comm.check_system_info()
|
||||
self.first_run = False
|
||||
self.comm.load(kernel_library)
|
||||
self.comm.run()
|
||||
self.comm.serve(embedding_map, symbolizer, demangler)
|
||||
|
||||
def run(self, function, args, kwargs):
|
||||
result = None
|
||||
@rpc(flags={"async"})
|
||||
def set_result(new_result):
|
||||
nonlocal result
|
||||
result = new_result
|
||||
embedding_map, kernel_library, symbolizer, demangler, subkernel_arg_types = \
|
||||
|
||||
embedding_map, kernel_library, symbolizer, demangler = \
|
||||
self.compile(function, args, kwargs, set_result)
|
||||
self.compile_and_upload_subkernels(embedding_map, args, subkernel_arg_types)
|
||||
self._run_compiled(kernel_library, embedding_map, symbolizer, demangler)
|
||||
|
||||
if self.first_run:
|
||||
self.comm.check_system_info()
|
||||
self.first_run = False
|
||||
|
||||
self.comm.load(kernel_library)
|
||||
self.comm.run()
|
||||
self.comm.serve(embedding_map, symbolizer, demangler)
|
||||
|
||||
return result
|
||||
|
||||
def compile_subkernel(self, sid, subkernel_fn, embedding_map, args, subkernel_arg_types):
|
||||
# pass self to subkernels (if applicable)
|
||||
# assuming the first argument is self
|
||||
subkernel_args = getfullargspec(subkernel_fn.artiq_embedded.function)
|
||||
self_arg = []
|
||||
if len(subkernel_args[0]) > 0:
|
||||
if subkernel_args[0][0] == 'self':
|
||||
self_arg = args[:1]
|
||||
destination = subkernel_fn.artiq_embedded.destination
|
||||
destination_tgt = self.satellite_cpu_targets[destination]
|
||||
target = get_target_cls(destination_tgt)(subkernel_id=sid)
|
||||
object_map, kernel_library, _, _, _ = \
|
||||
self.compile(subkernel_fn, self_arg, {}, attribute_writeback=False,
|
||||
print_as_rpc=False, target=target, destination=destination,
|
||||
subkernel_arg_types=subkernel_arg_types.get(sid, []))
|
||||
if object_map.has_rpc_or_subkernel():
|
||||
raise ValueError("Subkernel must not use RPC or subkernels in other destinations")
|
||||
return destination, kernel_library
|
||||
|
||||
def compile_and_upload_subkernels(self, embedding_map, args, subkernel_arg_types):
|
||||
for sid, subkernel_fn in embedding_map.subkernels().items():
|
||||
destination, kernel_library = \
|
||||
self.compile_subkernel(sid, subkernel_fn, embedding_map,
|
||||
args, subkernel_arg_types)
|
||||
self.comm.upload_subkernel(kernel_library, sid, destination)
|
||||
|
||||
def precompile(self, function, *args, **kwargs):
|
||||
"""Precompile a kernel and return a callable that executes it on the core device
|
||||
at a later time.
|
||||
|
||||
Arguments to the kernel are set at compilation time and passed to this function,
|
||||
as additional positional and keyword arguments.
|
||||
The returned callable accepts no arguments.
|
||||
|
||||
Precompiled kernels may use RPCs and subkernels.
|
||||
|
||||
Object attributes at the beginning of a precompiled kernel execution have the
|
||||
values they had at precompilation time. If up-to-date values are required,
|
||||
use RPC to read them.
|
||||
Similarly, modified values are not written back, and explicit RPC should be used
|
||||
to modify host objects.
|
||||
Carefully review the source code of drivers calls used in precompiled kernels, as
|
||||
they may rely on host object attributes being transfered between kernel calls.
|
||||
Examples include code used to control DDS phase, and Urukul RF switch control
|
||||
via the CPLD register.
|
||||
|
||||
The return value of the callable is the return value of the kernel, if any.
|
||||
|
||||
The callable may be called several times.
|
||||
"""
|
||||
if not hasattr(function, "artiq_embedded"):
|
||||
raise ValueError("Argument is not a kernel")
|
||||
|
||||
result = None
|
||||
@rpc(flags={"async"})
|
||||
def set_result(new_result):
|
||||
nonlocal result
|
||||
result = new_result
|
||||
|
||||
embedding_map, kernel_library, symbolizer, demangler, subkernel_arg_types = \
|
||||
self.compile(function, args, kwargs, set_result, attribute_writeback=False)
|
||||
self.compile_and_upload_subkernels(embedding_map, args, subkernel_arg_types)
|
||||
|
||||
@wraps(function)
|
||||
def run_precompiled():
|
||||
nonlocal result
|
||||
self._run_compiled(kernel_library, embedding_map, symbolizer, demangler)
|
||||
return result
|
||||
|
||||
return run_precompiled
|
||||
|
||||
@portable
|
||||
def seconds_to_mu(self, seconds):
|
||||
"""Convert seconds to the corresponding number of machine units
|
||||
"""Converts seconds to the corresponding number of machine units
|
||||
(RTIO cycles).
|
||||
|
||||
:param seconds: time (in seconds) to convert.
|
||||
|
|
@ -247,7 +143,7 @@ class Core:
|
|||
|
||||
@portable
|
||||
def mu_to_seconds(self, mu):
|
||||
"""Convert machine units (RTIO cycles) to seconds.
|
||||
"""Converts machine units (RTIO cycles) to seconds.
|
||||
|
||||
:param mu: cycle count to convert.
|
||||
"""
|
||||
|
|
@ -255,34 +151,15 @@ class Core:
|
|||
|
||||
@kernel
|
||||
def get_rtio_counter_mu(self):
|
||||
"""Retrieve the current value of the hardware RTIO timeline counter.
|
||||
|
||||
As the timing of kernel code executed on the CPU is inherently
|
||||
non-deterministic, the return value is by necessity only a lower bound
|
||||
for the actual value of the hardware register at the instant when
|
||||
execution resumes in the caller.
|
||||
|
||||
For a more detailed description of these concepts, see :doc:`/rtio`.
|
||||
"""
|
||||
return rtio_get_counter()
|
||||
|
||||
@kernel
|
||||
def wait_until_mu(self, cursor_mu):
|
||||
"""Block execution until the hardware RTIO counter reaches the given
|
||||
value (see :meth:`get_rtio_counter_mu`).
|
||||
def get_drtio_link_status(self, linkno):
|
||||
"""Returns whether the specified DRTIO link is up.
|
||||
|
||||
If the hardware counter has already passed the given time, the function
|
||||
returns immediately.
|
||||
"""
|
||||
while self.get_rtio_counter_mu() < cursor_mu:
|
||||
pass
|
||||
|
||||
@kernel
|
||||
def get_rtio_destination_status(self, destination):
|
||||
"""Returns whether the specified RTIO destination is up.
|
||||
This is particularly useful in startup kernels to delay
|
||||
startup until certain DRTIO destinations are up."""
|
||||
return rtio_get_destination_status(destination)
|
||||
startup until certain DRTIO links are up."""
|
||||
return drtio_get_link_status(linkno)
|
||||
|
||||
@kernel
|
||||
def reset(self):
|
||||
|
|
@ -302,23 +179,3 @@ class Core:
|
|||
min_now = rtio_get_counter() + 125000
|
||||
if now_mu() < min_now:
|
||||
at_mu(min_now)
|
||||
|
||||
def trigger_analyzer_proxy(self):
|
||||
"""Causes the core analyzer proxy to retrieve a dump from the device,
|
||||
and distribute it to all connected clients (typically dashboards).
|
||||
|
||||
Returns only after the dump has been retrieved from the device.
|
||||
|
||||
Raises IOError if no analyzer proxy has been configured, or if the
|
||||
analyzer proxy fails. In the latter case, more details would be
|
||||
available in the proxy log.
|
||||
"""
|
||||
if self.analyzer_proxy is None:
|
||||
if self.analyzer_proxy_name is not None:
|
||||
self.analyzer_proxy = self.dmgr.get(self.analyzer_proxy_name)
|
||||
if self.analyzer_proxy is None:
|
||||
raise IOError("No analyzer proxy configured")
|
||||
else:
|
||||
success = self.analyzer_proxy.trigger()
|
||||
if not success:
|
||||
raise IOError("Analyzer proxy reported failure")
|
||||
|
|
|
|||
|
|
@ -1,641 +0,0 @@
|
|||
{
|
||||
"$id": "https://m-labs.hk/kasli_generic.schema.json",
|
||||
"$schema": "http://json-schema.org/draft-07/schema#",
|
||||
"title": "Kasli variant description",
|
||||
|
||||
"type": "object",
|
||||
"properties": {
|
||||
"_description": {
|
||||
"type": "string",
|
||||
"description": "Free-form description text"
|
||||
},
|
||||
"target": {
|
||||
"type": "string",
|
||||
"description": "Target board"
|
||||
},
|
||||
"variant": {
|
||||
"type": "string",
|
||||
"description": "Target board variant name"
|
||||
},
|
||||
"min_artiq_version": {
|
||||
"type": "string",
|
||||
"description": "Minimum required ARTIQ version",
|
||||
"default": "0"
|
||||
},
|
||||
"hw_rev": {
|
||||
"type": "string",
|
||||
"description": "Hardware revision"
|
||||
},
|
||||
"base": {
|
||||
"type": "string",
|
||||
"enum": ["use_drtio_role", "standalone", "master", "satellite"],
|
||||
"description": "Deprecated, use drtio_role instead",
|
||||
"default": "use_drtio_role"
|
||||
},
|
||||
"drtio_role": {
|
||||
"type": "string",
|
||||
"enum": ["standalone", "master", "satellite"],
|
||||
"description": "Role that this device takes in a DRTIO network; 'standalone' means no DRTIO",
|
||||
"default": "standalone"
|
||||
},
|
||||
"ext_ref_frequency": {
|
||||
"type": "number",
|
||||
"exclusiveMinimum": 0,
|
||||
"description": "External reference frequency"
|
||||
},
|
||||
"rtio_frequency": {
|
||||
"type": "number",
|
||||
"exclusiveMinimum": 0,
|
||||
"default": 125e6,
|
||||
"description": "RTIO frequency"
|
||||
},
|
||||
"core_addr": {
|
||||
"type": "string",
|
||||
"format": "ipv4",
|
||||
"description": "IPv4 address",
|
||||
"default": "192.168.1.70"
|
||||
},
|
||||
"vendor": {
|
||||
"type": "string",
|
||||
"description": "Board vendor"
|
||||
},
|
||||
"eui48": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "string",
|
||||
"pattern": "^([0-9a-f]{2}-){5}[0-9a-f]{2}$",
|
||||
"examples": ["80-1f-12-4c-22-7f"]
|
||||
},
|
||||
"description": "Ethernet MAC addresses"
|
||||
},
|
||||
"enable_sata_drtio": {
|
||||
"type": "boolean",
|
||||
"default": false
|
||||
},
|
||||
"sed_lanes": {
|
||||
"type": "number",
|
||||
"minimum": 1,
|
||||
"maximum": 32,
|
||||
"default": 8,
|
||||
"description": "Number of FIFOs in the SED, must be a power of 2"
|
||||
},
|
||||
"peripherals": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"$ref": "#/definitions/peripheral"
|
||||
}
|
||||
}
|
||||
},
|
||||
"if": {
|
||||
"properties": {
|
||||
"target": { "const": "kasli" },
|
||||
"hw_rev": {
|
||||
"not": {
|
||||
"oneOf": [
|
||||
{ "const": "v1.0" },
|
||||
{ "const": "v1.1" }
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"enable_sata_drtio": {
|
||||
"const": false
|
||||
}
|
||||
}
|
||||
},
|
||||
"required": ["target", "variant", "hw_rev", "base", "peripherals"],
|
||||
"additionalProperties": false,
|
||||
|
||||
"oneOf": [
|
||||
{
|
||||
"properties": {
|
||||
"target": {
|
||||
"type": "string",
|
||||
"const": "kasli"
|
||||
},
|
||||
"hw_rev": {
|
||||
"type": "string",
|
||||
"enum": ["v1.0", "v1.1", "v2.0"]
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"properties": {
|
||||
"target": {
|
||||
"type": "string",
|
||||
"const": "kasli_soc"
|
||||
},
|
||||
"hw_rev": {
|
||||
"type": "string",
|
||||
"enum": ["v1.0", "v1.1"]
|
||||
}
|
||||
}
|
||||
}
|
||||
],
|
||||
|
||||
"definitions": {
|
||||
"peripheral": {
|
||||
"type": "object",
|
||||
"properties": {
|
||||
"type": {
|
||||
"type": "string",
|
||||
"enum": ["dio", "dio_spi", "urukul", "novogorny", "sampler", "suservo", "zotino", "grabber", "mirny", "fastino", "phaser", "hvamp", "shuttler"]
|
||||
},
|
||||
"board": {
|
||||
"type": "string"
|
||||
},
|
||||
"hw_rev": {
|
||||
"type": "string",
|
||||
"pattern": "^v[0-9]+\\.[0-9]+"
|
||||
}
|
||||
},
|
||||
"required": ["type"],
|
||||
"allOf": [{
|
||||
"title": "DIO",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "dio"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 1
|
||||
},
|
||||
"edge_counter": {
|
||||
"type": "boolean",
|
||||
"default": false
|
||||
},
|
||||
"bank_direction_low": {
|
||||
"type": "string",
|
||||
"enum": ["input", "output", "clkgen"]
|
||||
},
|
||||
"bank_direction_high": {
|
||||
"type": "string",
|
||||
"enum": ["input", "output", "clkgen"]
|
||||
}
|
||||
},
|
||||
"required": ["ports", "bank_direction_low", "bank_direction_high"]
|
||||
}
|
||||
}, {
|
||||
"title": "DIO_SPI",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "dio_spi"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 1
|
||||
},
|
||||
"spi": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "object",
|
||||
"properties": {
|
||||
"name": {
|
||||
"type": "string",
|
||||
"default": "dio_spi"
|
||||
},
|
||||
"clk": {
|
||||
"type": "integer",
|
||||
"minimum": 0,
|
||||
"maximum": 7
|
||||
},
|
||||
"mosi": {
|
||||
"type": "integer",
|
||||
"minimum": 0,
|
||||
"maximum": 7
|
||||
},
|
||||
"miso": {
|
||||
"type": "integer",
|
||||
"minimum": 0,
|
||||
"maximum": 7
|
||||
},
|
||||
"cs": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer",
|
||||
"minimum": 0,
|
||||
"maximum": 7
|
||||
}
|
||||
}
|
||||
},
|
||||
"required": ["clk"]
|
||||
},
|
||||
"minItems": 1
|
||||
},
|
||||
"ttl": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "object",
|
||||
"properties": {
|
||||
"name": {
|
||||
"type": "string",
|
||||
"default": "ttl"
|
||||
},
|
||||
"pin": {
|
||||
"type": "integer",
|
||||
"minimum": 0,
|
||||
"maximum": 7
|
||||
},
|
||||
"direction": {
|
||||
"type": "string",
|
||||
"enum": ["input", "output"]
|
||||
},
|
||||
"edge_counter": {
|
||||
"type": "boolean",
|
||||
"default": false
|
||||
}
|
||||
},
|
||||
"required": ["pin", "direction"]
|
||||
},
|
||||
"default": []
|
||||
}
|
||||
},
|
||||
"required": ["ports", "spi"]
|
||||
}
|
||||
}, {
|
||||
"title": "Urukul",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "urukul"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 2
|
||||
},
|
||||
"synchronization": {
|
||||
"type": "boolean",
|
||||
"default": false
|
||||
},
|
||||
"refclk": {
|
||||
"type": "number",
|
||||
"minimum": 0
|
||||
},
|
||||
"clk_sel": {
|
||||
"type": "integer",
|
||||
"minimum": 0,
|
||||
"maximum": 3
|
||||
},
|
||||
"clk_div": {
|
||||
"type": "integer",
|
||||
"minimum": 0,
|
||||
"maximum": 3,
|
||||
"default": 0
|
||||
},
|
||||
"pll_n": {
|
||||
"type": "integer"
|
||||
},
|
||||
"pll_en": {
|
||||
"type": "integer",
|
||||
"minimum": 0,
|
||||
"maximum": 1,
|
||||
"default": 1
|
||||
},
|
||||
"pll_vco": {
|
||||
"type": "integer"
|
||||
},
|
||||
"dds": {
|
||||
"type": "string",
|
||||
"enum": ["ad9910", "ad9912"],
|
||||
"default": "ad9910"
|
||||
}
|
||||
},
|
||||
"required": ["ports"]
|
||||
}
|
||||
}, {
|
||||
"title": "Novogorny",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "novogorny"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 1
|
||||
}
|
||||
},
|
||||
"required": ["ports"]
|
||||
}
|
||||
}, {
|
||||
"title": "Sampler",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "sampler"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 2
|
||||
}
|
||||
},
|
||||
"required": ["ports"]
|
||||
}
|
||||
}, {
|
||||
"title": "SUServo",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "suservo"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"sampler_ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 2,
|
||||
"maxItems": 2
|
||||
},
|
||||
"sampler_hw_rev": {
|
||||
"type": "string",
|
||||
"pattern": "^v[0-9]+\\.[0-9]+",
|
||||
"default": "v2.2"
|
||||
},
|
||||
"urukul0_ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 2,
|
||||
"maxItems": 2
|
||||
},
|
||||
"urukul1_ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 2,
|
||||
"maxItems": 2
|
||||
},
|
||||
"refclk": {
|
||||
"type": "number",
|
||||
"minimum": 0
|
||||
},
|
||||
"clk_sel": {
|
||||
"type": "integer",
|
||||
"minimum": 0,
|
||||
"maximum": 3
|
||||
},
|
||||
"pll_n": {
|
||||
"type": "integer",
|
||||
"default": 32
|
||||
},
|
||||
"pll_en": {
|
||||
"type": "integer",
|
||||
"minimum": 0,
|
||||
"maximum": 1,
|
||||
"default": 1
|
||||
},
|
||||
"pll_vco": {
|
||||
"type": "integer"
|
||||
}
|
||||
},
|
||||
"required": ["sampler_ports", "urukul0_ports"]
|
||||
}
|
||||
}, {
|
||||
"title": "Zotino",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "zotino"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 1
|
||||
}
|
||||
},
|
||||
"required": ["ports"]
|
||||
}
|
||||
}, {
|
||||
"title": "Grabber",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "grabber"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 3
|
||||
}
|
||||
},
|
||||
"required": ["ports"]
|
||||
}
|
||||
}, {
|
||||
"title": "Mirny",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "mirny"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 1
|
||||
},
|
||||
"refclk": {
|
||||
"type": "number",
|
||||
"exclusiveMinimum": 0,
|
||||
"default": 100e6
|
||||
},
|
||||
"clk_sel": {
|
||||
"oneOf": [
|
||||
{
|
||||
"type": "integer",
|
||||
"minimum": 0,
|
||||
"maximum": 3
|
||||
},
|
||||
{
|
||||
"type": "string",
|
||||
"enum": ["xo", "mmcx", "sma"]
|
||||
}
|
||||
],
|
||||
"default": 0
|
||||
},
|
||||
"almazny": {
|
||||
"type": "boolean",
|
||||
"default": false
|
||||
},
|
||||
"almazny_hw_rev": {
|
||||
"type": "string",
|
||||
"pattern": "^v[0-9]+\\.[0-9]+",
|
||||
"default": "v1.2"
|
||||
}
|
||||
},
|
||||
"required": ["ports"]
|
||||
}
|
||||
}, {
|
||||
"title": "Fastino",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "fastino"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 1
|
||||
},
|
||||
"log2_width": {
|
||||
"type": "integer",
|
||||
"default": 0,
|
||||
"description": "Width of DAC channel group (logarithm base 2)"
|
||||
}
|
||||
},
|
||||
"required": ["ports"]
|
||||
}
|
||||
}, {
|
||||
"title": "Phaser",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "phaser"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 1
|
||||
},
|
||||
"mode": {
|
||||
"type": "string",
|
||||
"enum": ["base", "miqro"],
|
||||
"default": "base"
|
||||
}
|
||||
},
|
||||
"required": ["ports"]
|
||||
}
|
||||
}, {
|
||||
"title": "HVAmp",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "hvamp"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 1
|
||||
}
|
||||
},
|
||||
"required": ["ports"]
|
||||
}
|
||||
},{
|
||||
"title": "Shuttler",
|
||||
"if": {
|
||||
"properties": {
|
||||
"type": {
|
||||
"const": "shuttler"
|
||||
}
|
||||
}
|
||||
},
|
||||
"then": {
|
||||
"properties": {
|
||||
"ports": {
|
||||
"type": "array",
|
||||
"items": {
|
||||
"type": "integer"
|
||||
},
|
||||
"minItems": 1,
|
||||
"maxItems": 2
|
||||
},
|
||||
"drtio_destination": {
|
||||
"type": "integer"
|
||||
}
|
||||
},
|
||||
"required": ["ports"]
|
||||
}
|
||||
}]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,277 +0,0 @@
|
|||
class DAC34H84:
|
||||
"""DAC34H84 settings and register map.
|
||||
|
||||
For possible values, documentation, and explanation, see the DAC datasheet
|
||||
at https://www.ti.com/lit/pdf/slas751
|
||||
"""
|
||||
qmc_corr_ena = 0 # msb ab
|
||||
qmc_offset_ena = 0 # msb ab
|
||||
invsinc_ena = 0 # msb ab
|
||||
interpolation = 1 # 2x
|
||||
fifo_ena = 1
|
||||
alarm_out_ena = 1
|
||||
alarm_out_pol = 1
|
||||
clkdiv_sync_ena = 1
|
||||
|
||||
iotest_ena = 0
|
||||
cnt64_ena = 0
|
||||
oddeven_parity = 0 # even
|
||||
single_parity_ena = 1
|
||||
dual_parity_ena = 0
|
||||
rev_interface = 0
|
||||
dac_complement = 0b0000 # msb A
|
||||
alarm_fifo = 0b111 # msb 2-away
|
||||
|
||||
dacclkgone_ena = 1
|
||||
dataclkgone_ena = 1
|
||||
collisiongone_ena = 1
|
||||
sif4_ena = 1
|
||||
mixer_ena = 0
|
||||
mixer_gain = 1
|
||||
nco_ena = 0
|
||||
revbus = 0
|
||||
twos = 1
|
||||
|
||||
coarse_dac = 9 # 18.75 mA, 0-15
|
||||
sif_txenable = 0
|
||||
|
||||
mask_alarm_from_zerochk = 0
|
||||
mask_alarm_fifo_collision = 0
|
||||
mask_alarm_fifo_1away = 0
|
||||
mask_alarm_fifo_2away = 0
|
||||
mask_alarm_dacclk_gone = 0
|
||||
mask_alarm_dataclk_gone = 0
|
||||
mask_alarm_output_gone = 0
|
||||
mask_alarm_from_iotest = 0
|
||||
mask_alarm_from_pll = 0
|
||||
mask_alarm_parity = 0b0000 # msb a
|
||||
|
||||
qmc_offseta = 0 # 12b
|
||||
fifo_offset = 2 # 0-7
|
||||
qmc_offsetb = 0 # 12b
|
||||
|
||||
qmc_offsetc = 0 # 12b
|
||||
|
||||
qmc_offsetd = 0 # 12b
|
||||
|
||||
qmc_gaina = 0 # 11b
|
||||
|
||||
cmix_fs8 = 0
|
||||
cmix_fs4 = 0
|
||||
cmix_fs2 = 0
|
||||
cmix_nfs4 = 0
|
||||
qmc_gainb = 0 # 11b
|
||||
|
||||
qmc_gainc = 0 # 11b
|
||||
|
||||
output_delayab = 0b00
|
||||
output_delaycd = 0b00
|
||||
qmc_gaind = 0 # 11b
|
||||
|
||||
qmc_phaseab = 0 # 12b
|
||||
|
||||
qmc_phasecd = 0 # 12b
|
||||
|
||||
phase_offsetab = 0 # 16b
|
||||
phase_offsetcd = 0 # 16b
|
||||
phase_addab_lsb = 0 # 16b
|
||||
phase_addab_msb = 0 # 16b
|
||||
phase_addcd_lsb = 0 # 16b
|
||||
phase_addcd_msb = 0 # 16b
|
||||
|
||||
pll_reset = 0
|
||||
pll_ndivsync_ena = 1
|
||||
pll_ena = 1
|
||||
pll_cp = 0b01 # single charge pump
|
||||
pll_p = 0b100 # p=4
|
||||
|
||||
pll_m2 = 1 # x2
|
||||
pll_m = 8 # m = 8
|
||||
pll_n = 0b0001 # n = 2
|
||||
pll_vcotune = 0b01
|
||||
|
||||
pll_vco = 0x3f # 4 GHz
|
||||
bias_sleep = 0
|
||||
tsense_sleep = 0
|
||||
pll_sleep = 0
|
||||
clkrecv_sleep = 0
|
||||
dac_sleep = 0b0000 # msb a
|
||||
|
||||
extref_ena = 0
|
||||
fuse_sleep = 1
|
||||
atest = 0b00000 # atest mode
|
||||
|
||||
syncsel_qmcoffsetab = 0b1001 # sif_sync and register write
|
||||
syncsel_qmcoffsetcd = 0b1001 # sif_sync and register write
|
||||
syncsel_qmccorrab = 0b1001 # sif_sync and register write
|
||||
syncsel_qmccorrcd = 0b1001 # sif_sync and register write
|
||||
|
||||
syncsel_mixerab = 0b1001 # sif_sync and register write
|
||||
syncsel_mixercd = 0b1001 # sif_sync and register write
|
||||
syncsel_nco = 0b1000 # sif_sync
|
||||
syncsel_fifo_input = 0b10 # external lvds istr
|
||||
sif_sync = 0
|
||||
|
||||
syncsel_fifoin = 0b0010 # istr
|
||||
syncsel_fifoout = 0b0100 # ostr
|
||||
clkdiv_sync_sel = 0 # ostr
|
||||
|
||||
path_a_sel = 0
|
||||
path_b_sel = 1
|
||||
path_c_sel = 2
|
||||
path_d_sel = 3
|
||||
# swap dac pairs (CDAB) for layout
|
||||
# swap I-Q dacs for spectral inversion
|
||||
dac_a_sel = 3
|
||||
dac_b_sel = 2
|
||||
dac_c_sel = 1
|
||||
dac_d_sel = 0
|
||||
|
||||
dac_sleep_en = 0b1111 # msb a
|
||||
clkrecv_sleep_en = 1
|
||||
pll_sleep_en = 1
|
||||
lvds_data_sleep_en = 1
|
||||
lvds_control_sleep_en = 1
|
||||
temp_sense_sleep_en = 1
|
||||
bias_sleep_en = 1
|
||||
|
||||
data_dly = 2
|
||||
clk_dly = 0
|
||||
|
||||
ostrtodig_sel = 0
|
||||
ramp_ena = 0
|
||||
sifdac_ena = 0
|
||||
|
||||
grp_delaya = 0x00
|
||||
grp_delayb = 0x00
|
||||
|
||||
grp_delayc = 0x00
|
||||
grp_delayd = 0x00
|
||||
|
||||
sifdac = 0
|
||||
|
||||
def __init__(self, updates=None):
|
||||
if updates is None:
|
||||
return
|
||||
for key, value in updates.items():
|
||||
if not hasattr(self, key):
|
||||
raise KeyError("invalid setting", key)
|
||||
setattr(self, key, value)
|
||||
|
||||
def get_mmap(self):
|
||||
mmap = []
|
||||
mmap.append(
|
||||
(0x00 << 16) |
|
||||
(self.qmc_offset_ena << 14) | (self.qmc_corr_ena << 12) |
|
||||
(self.interpolation << 8) | (self.fifo_ena << 7) |
|
||||
(self.alarm_out_ena << 4) | (self.alarm_out_pol << 3) |
|
||||
(self.clkdiv_sync_ena << 2) | (self.invsinc_ena << 0))
|
||||
mmap.append(
|
||||
(0x01 << 16) |
|
||||
(self.iotest_ena << 15) | (self.cnt64_ena << 12) |
|
||||
(self.oddeven_parity << 11) | (self.single_parity_ena << 10) |
|
||||
(self.dual_parity_ena << 9) | (self.rev_interface << 8) |
|
||||
(self.dac_complement << 4) | (self.alarm_fifo << 1))
|
||||
mmap.append(
|
||||
(0x02 << 16) |
|
||||
(self.dacclkgone_ena << 14) | (self.dataclkgone_ena << 13) |
|
||||
(self.collisiongone_ena << 12) | (self.sif4_ena << 7) |
|
||||
(self.mixer_ena << 6) | (self.mixer_gain << 5) |
|
||||
(self.nco_ena << 4) | (self.revbus << 3) | (self.twos << 1))
|
||||
mmap.append((0x03 << 16) | (self.coarse_dac << 12) |
|
||||
(self.sif_txenable << 0))
|
||||
mmap.append(
|
||||
(0x07 << 16) |
|
||||
(self.mask_alarm_from_zerochk << 15) | (1 << 14) |
|
||||
(self.mask_alarm_fifo_collision << 13) |
|
||||
(self.mask_alarm_fifo_1away << 12) |
|
||||
(self.mask_alarm_fifo_2away << 11) |
|
||||
(self.mask_alarm_dacclk_gone << 10) |
|
||||
(self.mask_alarm_dataclk_gone << 9) |
|
||||
(self.mask_alarm_output_gone << 8) |
|
||||
(self.mask_alarm_from_iotest << 7) | (1 << 6) |
|
||||
(self.mask_alarm_from_pll << 5) | (self.mask_alarm_parity << 1))
|
||||
mmap.append(
|
||||
(0x08 << 16) | (self.qmc_offseta << 0))
|
||||
mmap.append(
|
||||
(0x09 << 16) | (self.fifo_offset << 13) | (self.qmc_offsetb << 0))
|
||||
mmap.append((0x0a << 16) | (self.qmc_offsetc << 0))
|
||||
mmap.append((0x0b << 16) | (self.qmc_offsetd << 0))
|
||||
mmap.append((0x0c << 16) | (self.qmc_gaina << 0))
|
||||
mmap.append(
|
||||
(0x0d << 16) |
|
||||
(self.cmix_fs8 << 15) | (self.cmix_fs4 << 14) |
|
||||
(self.cmix_fs2 << 13) | (self.cmix_nfs4 << 12) |
|
||||
(self.qmc_gainb << 0))
|
||||
mmap.append((0x0e << 16) | (self.qmc_gainc << 0))
|
||||
mmap.append(
|
||||
(0x0f << 16) |
|
||||
(self.output_delayab << 14) | (self.output_delaycd << 12) |
|
||||
(self.qmc_gaind << 0))
|
||||
mmap.append((0x10 << 16) | (self.qmc_phaseab << 0))
|
||||
mmap.append((0x11 << 16) | (self.qmc_phasecd << 0))
|
||||
mmap.append((0x12 << 16) | (self.phase_offsetab << 0))
|
||||
mmap.append((0x13 << 16) | (self.phase_offsetcd << 0))
|
||||
mmap.append((0x14 << 16) | (self.phase_addab_lsb << 0))
|
||||
mmap.append((0x15 << 16) | (self.phase_addab_msb << 0))
|
||||
mmap.append((0x16 << 16) | (self.phase_addcd_lsb << 0))
|
||||
mmap.append((0x17 << 16) | (self.phase_addcd_msb << 0))
|
||||
mmap.append(
|
||||
(0x18 << 16) |
|
||||
(0b001 << 13) | (self.pll_reset << 12) |
|
||||
(self.pll_ndivsync_ena << 11) | (self.pll_ena << 10) |
|
||||
(self.pll_cp << 6) | (self.pll_p << 3))
|
||||
mmap.append(
|
||||
(0x19 << 16) |
|
||||
(self.pll_m2 << 15) | (self.pll_m << 8) | (self.pll_n << 4) |
|
||||
(self.pll_vcotune << 2))
|
||||
mmap.append(
|
||||
(0x1a << 16) |
|
||||
(self.pll_vco << 10) | (self.bias_sleep << 7) |
|
||||
(self.tsense_sleep << 6) |
|
||||
(self.pll_sleep << 5) | (self.clkrecv_sleep << 4) |
|
||||
(self.dac_sleep << 0))
|
||||
mmap.append(
|
||||
(0x1b << 16) |
|
||||
(self.extref_ena << 15) | (self.fuse_sleep << 11) |
|
||||
(self.atest << 0))
|
||||
mmap.append(
|
||||
(0x1e << 16) |
|
||||
(self.syncsel_qmcoffsetab << 12) |
|
||||
(self.syncsel_qmcoffsetcd << 8) |
|
||||
(self.syncsel_qmccorrab << 4) |
|
||||
(self.syncsel_qmccorrcd << 0))
|
||||
mmap.append(
|
||||
(0x1f << 16) |
|
||||
(self.syncsel_mixerab << 12) | (self.syncsel_mixercd << 8) |
|
||||
(self.syncsel_nco << 4) | (self.syncsel_fifo_input << 2) |
|
||||
(self.sif_sync << 1))
|
||||
mmap.append(
|
||||
(0x20 << 16) |
|
||||
(self.syncsel_fifoin << 12) | (self.syncsel_fifoout << 8) |
|
||||
(self.clkdiv_sync_sel << 0))
|
||||
mmap.append(
|
||||
(0x22 << 16) |
|
||||
(self.path_a_sel << 14) | (self.path_b_sel << 12) |
|
||||
(self.path_c_sel << 10) | (self.path_d_sel << 8) |
|
||||
(self.dac_a_sel << 6) | (self.dac_b_sel << 4) |
|
||||
(self.dac_c_sel << 2) | (self.dac_d_sel << 0))
|
||||
mmap.append(
|
||||
(0x23 << 16) |
|
||||
(self.dac_sleep_en << 12) | (self.clkrecv_sleep_en << 11) |
|
||||
(self.pll_sleep_en << 10) | (self.lvds_data_sleep_en << 9) |
|
||||
(self.lvds_control_sleep_en << 8) |
|
||||
(self.temp_sense_sleep_en << 7) | (1 << 6) |
|
||||
(self.bias_sleep_en << 5) | (0x1f << 0))
|
||||
mmap.append(
|
||||
(0x24 << 16) | (self.data_dly << 13) | (self.clk_dly << 10))
|
||||
mmap.append(
|
||||
(0x2d << 16) |
|
||||
(self.ostrtodig_sel << 14) | (self.ramp_ena << 13) |
|
||||
(0x002 << 1) | (self.sifdac_ena << 0))
|
||||
mmap.append(
|
||||
(0x2e << 16) | (self.grp_delaya << 8) | (self.grp_delayb << 0))
|
||||
mmap.append(
|
||||
(0x2f << 16) | (self.grp_delayc << 8) | (self.grp_delayd << 0))
|
||||
mmap.append((0x30 << 16) | self.sifdac)
|
||||
return mmap
|
||||
|
|
@ -6,7 +6,7 @@ alone could achieve.
|
|||
"""
|
||||
|
||||
from artiq.language.core import syscall, kernel
|
||||
from artiq.language.types import TInt32, TInt64, TStr, TNone, TTuple, TBool
|
||||
from artiq.language.types import TInt32, TInt64, TStr, TNone, TTuple
|
||||
from artiq.coredevice.exceptions import DMAError
|
||||
|
||||
from numpy import int64
|
||||
|
|
@ -17,7 +17,7 @@ def dma_record_start(name: TStr) -> TNone:
|
|||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
@syscall
|
||||
def dma_record_stop(duration: TInt64, enable_ddma: TBool) -> TNone:
|
||||
def dma_record_stop(duration: TInt64) -> TNone:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
@syscall
|
||||
|
|
@ -25,16 +25,16 @@ def dma_erase(name: TStr) -> TNone:
|
|||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
@syscall
|
||||
def dma_retrieve(name: TStr) -> TTuple([TInt64, TInt32, TBool]):
|
||||
def dma_retrieve(name: TStr) -> TTuple([TInt64, TInt32]):
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
@syscall
|
||||
def dma_playback(timestamp: TInt64, ptr: TInt32, enable_ddma: TBool) -> TNone:
|
||||
def dma_playback(timestamp: TInt64, ptr: TInt32) -> TNone:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
|
||||
class DMARecordContextManager:
|
||||
"""Context manager returned by :meth:`CoreDMA.record()`.
|
||||
"""Context manager returned by ``CoreDMA.record()``.
|
||||
|
||||
Upon entering, starts recording a DMA trace. All RTIO operations are
|
||||
redirected to a newly created DMA buffer after this call, and ``now``
|
||||
|
|
@ -47,7 +47,6 @@ class DMARecordContextManager:
|
|||
def __init__(self):
|
||||
self.name = ""
|
||||
self.saved_now_mu = int64(0)
|
||||
self.enable_ddma = False
|
||||
|
||||
@kernel
|
||||
def __enter__(self):
|
||||
|
|
@ -57,7 +56,7 @@ class DMARecordContextManager:
|
|||
|
||||
@kernel
|
||||
def __exit__(self, type, value, traceback):
|
||||
dma_record_stop(now_mu(), self.enable_ddma) # see above
|
||||
dma_record_stop(now_mu()) # see above
|
||||
at_mu(self.saved_now_mu)
|
||||
|
||||
|
||||
|
|
@ -75,20 +74,12 @@ class CoreDMA:
|
|||
self.epoch = 0
|
||||
|
||||
@kernel
|
||||
def record(self, name, enable_ddma=False):
|
||||
def record(self, name):
|
||||
"""Returns a context manager that will record a DMA trace called ``name``.
|
||||
Any previously recorded trace with the same name is overwritten.
|
||||
The trace will persist across kernel switches.
|
||||
|
||||
In DRTIO context, distributed DMA can be toggled with ``enable_ddma``.
|
||||
Enabling it allows running DMA on satellites, rather than sending all
|
||||
events from the master.
|
||||
|
||||
Keeping it disabled it may improve performance in some scenarios,
|
||||
e.g. when there are many small satellite buffers."""
|
||||
The trace will persist across kernel switches."""
|
||||
self.epoch += 1
|
||||
self.recorder.name = name
|
||||
self.recorder.enable_ddma = enable_ddma
|
||||
return self.recorder
|
||||
|
||||
@kernel
|
||||
|
|
@ -101,24 +92,24 @@ class CoreDMA:
|
|||
def playback(self, name):
|
||||
"""Replays a previously recorded DMA trace. This function blocks until
|
||||
the entire trace is submitted to the RTIO FIFOs."""
|
||||
(advance_mu, ptr, uses_ddma) = dma_retrieve(name)
|
||||
dma_playback(now_mu(), ptr, uses_ddma)
|
||||
(advance_mu, ptr) = dma_retrieve(name)
|
||||
dma_playback(now_mu(), ptr)
|
||||
delay_mu(advance_mu)
|
||||
|
||||
@kernel
|
||||
def get_handle(self, name):
|
||||
"""Returns a handle to a previously recorded DMA trace. The returned handle
|
||||
is only valid until the next call to :meth:`record` or :meth:`erase`."""
|
||||
(advance_mu, ptr, uses_ddma) = dma_retrieve(name)
|
||||
return (self.epoch, advance_mu, ptr, uses_ddma)
|
||||
(advance_mu, ptr) = dma_retrieve(name)
|
||||
return (self.epoch, advance_mu, ptr)
|
||||
|
||||
@kernel
|
||||
def playback_handle(self, handle):
|
||||
"""Replays a handle obtained with :meth:`get_handle`. Using this function
|
||||
is much faster than :meth:`playback` for replaying a set of traces repeatedly,
|
||||
but incurs the overhead of managing the handles onto the programmer."""
|
||||
(epoch, advance_mu, ptr, uses_ddma) = handle
|
||||
(epoch, advance_mu, ptr) = handle
|
||||
if self.epoch != epoch:
|
||||
raise DMAError("Invalid handle")
|
||||
dma_playback(now_mu(), ptr, uses_ddma)
|
||||
dma_playback(now_mu(), ptr)
|
||||
delay_mu(advance_mu)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,17 @@
|
|||
"""
|
||||
DRTIO debugging functions.
|
||||
|
||||
Those syscalls are intended for ARTIQ developers only.
|
||||
"""
|
||||
|
||||
from artiq.language.core import syscall
|
||||
from artiq.language.types import TTuple, TInt32, TInt64, TNone
|
||||
|
||||
|
||||
@syscall(flags={"nounwind", "nowrite"})
|
||||
def drtio_get_packet_counts(linkno: TInt32) -> TTuple([TInt32, TInt32]):
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
@syscall(flags={"nounwind", "nowrite"})
|
||||
def drtio_get_fifo_space_req_count(linkno: TInt32) -> TInt32:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
|
@ -1,240 +0,0 @@
|
|||
"""Driver for RTIO-enabled TTL edge counter.
|
||||
|
||||
Like for the TTL input PHYs, sensitivity can be configured over RTIO
|
||||
(``gate_rising()``, etc.). In contrast to the former, however, the count is
|
||||
accumulated in gateware, and only a single input event is generated at the end
|
||||
of each gate period::
|
||||
|
||||
with parallel:
|
||||
doppler_cool()
|
||||
self.pmt_counter.gate_rising(1 * ms)
|
||||
|
||||
with parallel:
|
||||
readout()
|
||||
self.pmt_counter.gate_rising(100 * us)
|
||||
|
||||
print("Doppler cooling counts:", self.pmt_counter.fetch_count())
|
||||
print("Readout counts:", self.pmt_counter.fetch_count())
|
||||
|
||||
For applications where the timestamps of the individual input events are not
|
||||
required, this has two advantages over ``TTLInOut.count()`` beyond raw
|
||||
throughput. First, it is easy to count events during multiple separate periods
|
||||
without blocking to read back counts in between, as illustrated in the above
|
||||
example. Secondly, as each count total only takes up a single input event, it
|
||||
is much easier to acquire counts on several channels in parallel without
|
||||
risking input FIFO overflows::
|
||||
|
||||
# Using the TTLInOut driver, pmt_1 input events are only processed
|
||||
# after pmt_0 is done counting. To avoid RTIOOverflows, a round-robin
|
||||
# scheme would have to be implemented manually.
|
||||
|
||||
with parallel:
|
||||
self.pmt_0.gate_rising(10 * ms)
|
||||
self.pmt_1.gate_rising(10 * ms)
|
||||
|
||||
counts_0 = self.pmt_0.count(now_mu()) # blocks
|
||||
counts_1 = self.pmt_1.count(now_mu())
|
||||
|
||||
#
|
||||
|
||||
# Using gateware counters, only a single input event each is
|
||||
# generated, greatly reducing the load on the input FIFOs:
|
||||
|
||||
with parallel:
|
||||
self.pmt_0_counter.gate_rising(10 * ms)
|
||||
self.pmt_1_counter.gate_rising(10 * ms)
|
||||
|
||||
counts_0 = self.pmt_0_counter.fetch_count() # blocks
|
||||
counts_1 = self.pmt_1_counter.fetch_count()
|
||||
|
||||
See :mod:`artiq.gateware.rtio.phy.edge_counter` and
|
||||
:meth:`artiq.gateware.eem.DIO.add_std` for the gateware components.
|
||||
"""
|
||||
|
||||
from artiq.language.core import *
|
||||
from artiq.language.types import *
|
||||
from artiq.coredevice.rtio import (rtio_output, rtio_input_data,
|
||||
rtio_input_timestamped_data)
|
||||
from numpy import int32, int64
|
||||
|
||||
CONFIG_COUNT_RISING = 0b0001
|
||||
CONFIG_COUNT_FALLING = 0b0010
|
||||
CONFIG_SEND_COUNT_EVENT = 0b0100
|
||||
CONFIG_RESET_TO_ZERO = 0b1000
|
||||
|
||||
|
||||
class CounterOverflow(Exception):
|
||||
"""Raised when an edge counter value is read which indicates that the
|
||||
counter might have overflowed."""
|
||||
pass
|
||||
|
||||
|
||||
class EdgeCounter:
|
||||
"""RTIO TTL edge counter driver driver.
|
||||
|
||||
Like for regular TTL inputs, timeline periods where the counter is
|
||||
sensitive to a chosen set of input transitions can be specified. Unlike the
|
||||
former, however, the specified edges do not create individual input events;
|
||||
rather, the total count can be requested as a single input event from the
|
||||
core (typically at the end of the gate window).
|
||||
|
||||
:param channel: The RTIO channel of the gateware phy.
|
||||
:param gateware_width: The width of the gateware counter register, in
|
||||
bits. This is only used for overflow handling; to change the size,
|
||||
the gateware needs to be rebuilt.
|
||||
"""
|
||||
|
||||
kernel_invariants = {"core", "channel", "counter_max"}
|
||||
|
||||
def __init__(self, dmgr, channel, gateware_width=31, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.channel = channel
|
||||
self.counter_max = (1 << (gateware_width - 1)) - 1
|
||||
|
||||
@staticmethod
|
||||
def get_rtio_channels(channel, **kwargs):
|
||||
return [(channel, None)]
|
||||
|
||||
@kernel
|
||||
def gate_rising(self, duration):
|
||||
"""Count rising edges for the given duration and request the total at
|
||||
the end.
|
||||
|
||||
The counter is reset at the beginning of the gate period. Use
|
||||
:meth:`set_config` directly for more detailed control.
|
||||
|
||||
:param duration: The duration for which the gate is to stay open.
|
||||
|
||||
:return: The timestamp at the end of the gate period, in machine units.
|
||||
"""
|
||||
return self.gate_rising_mu(self.core.seconds_to_mu(duration))
|
||||
|
||||
@kernel
|
||||
def gate_falling(self, duration):
|
||||
"""Count falling edges for the given duration and request the total at
|
||||
the end.
|
||||
|
||||
The counter is reset at the beginning of the gate period. Use
|
||||
:meth:`set_config` directly for more detailed control.
|
||||
|
||||
:param duration: The duration for which the gate is to stay open.
|
||||
|
||||
:return: The timestamp at the end of the gate period, in machine units.
|
||||
"""
|
||||
return self.gate_falling_mu(self.core.seconds_to_mu(duration))
|
||||
|
||||
@kernel
|
||||
def gate_both(self, duration):
|
||||
"""Count both rising and falling edges for the given duration, and
|
||||
request the total at the end.
|
||||
|
||||
The counter is reset at the beginning of the gate period. Use
|
||||
:meth:`set_config` directly for more detailed control.
|
||||
|
||||
:param duration: The duration for which the gate is to stay open.
|
||||
|
||||
:return: The timestamp at the end of the gate period, in machine units.
|
||||
"""
|
||||
return self.gate_both_mu(self.core.seconds_to_mu(duration))
|
||||
|
||||
@kernel
|
||||
def gate_rising_mu(self, duration_mu):
|
||||
"""See :meth:`gate_rising`."""
|
||||
return self._gate_mu(
|
||||
duration_mu, count_rising=True, count_falling=False)
|
||||
|
||||
@kernel
|
||||
def gate_falling_mu(self, duration_mu):
|
||||
"""See :meth:`gate_falling`."""
|
||||
return self._gate_mu(
|
||||
duration_mu, count_rising=False, count_falling=True)
|
||||
|
||||
@kernel
|
||||
def gate_both_mu(self, duration_mu):
|
||||
"""See :meth:`gate_both_mu`."""
|
||||
return self._gate_mu(
|
||||
duration_mu, count_rising=True, count_falling=True)
|
||||
|
||||
@kernel
|
||||
def _gate_mu(self, duration_mu, count_rising, count_falling):
|
||||
self.set_config(
|
||||
count_rising=count_rising,
|
||||
count_falling=count_falling,
|
||||
send_count_event=False,
|
||||
reset_to_zero=True)
|
||||
delay_mu(duration_mu)
|
||||
self.set_config(
|
||||
count_rising=False,
|
||||
count_falling=False,
|
||||
send_count_event=True,
|
||||
reset_to_zero=False)
|
||||
return now_mu()
|
||||
|
||||
@kernel
|
||||
def set_config(self, count_rising: TBool, count_falling: TBool,
|
||||
send_count_event: TBool, reset_to_zero: TBool):
|
||||
"""Emit an RTIO event at the current timeline position to set the
|
||||
gateware configuration.
|
||||
|
||||
For most use cases, the `gate_*` wrappers will be more convenient.
|
||||
|
||||
:param count_rising: Whether to count rising signal edges.
|
||||
:param count_falling: Whether to count falling signal edges.
|
||||
:param send_count_event: If `True`, an input event with the current
|
||||
counter value is generated on the next clock cycle (once).
|
||||
:param reset_to_zero: If `True`, the counter value is reset to zero on
|
||||
the next clock cycle (once).
|
||||
"""
|
||||
config = int32(0)
|
||||
if count_rising:
|
||||
config |= CONFIG_COUNT_RISING
|
||||
if count_falling:
|
||||
config |= CONFIG_COUNT_FALLING
|
||||
if send_count_event:
|
||||
config |= CONFIG_SEND_COUNT_EVENT
|
||||
if reset_to_zero:
|
||||
config |= CONFIG_RESET_TO_ZERO
|
||||
rtio_output(self.channel << 8, config)
|
||||
|
||||
@kernel
|
||||
def fetch_count(self) -> TInt32:
|
||||
"""Wait for and return count total from previously requested input
|
||||
event.
|
||||
|
||||
It is valid to trigger multiple gate periods without immediately
|
||||
reading back the count total; the results will be returned in order on
|
||||
subsequent fetch calls.
|
||||
|
||||
This function blocks until a result becomes available.
|
||||
"""
|
||||
count = rtio_input_data(self.channel)
|
||||
if count == self.counter_max:
|
||||
raise CounterOverflow(
|
||||
"Input edge counter overflow on RTIO channel {0}",
|
||||
int64(self.channel))
|
||||
return count
|
||||
|
||||
@kernel
|
||||
def fetch_timestamped_count(
|
||||
self, timeout_mu=int64(-1)) -> TTuple([TInt64, TInt32]):
|
||||
"""Wait for and return the timestamp and count total of a previously
|
||||
requested input event.
|
||||
|
||||
It is valid to trigger multiple gate periods without immediately
|
||||
reading back the count total; the results will be returned in order on
|
||||
subsequent fetch calls.
|
||||
|
||||
This function blocks until a result becomes available or the given
|
||||
timeout elapses.
|
||||
|
||||
:return: A tuple of timestamp (-1 if timeout elapsed) and counter
|
||||
value. (The timestamp is that of the requested input event –
|
||||
typically the gate closing time – and not that of any input edges.)
|
||||
"""
|
||||
timestamp, count = rtio_input_timestamped_data(timeout_mu,
|
||||
self.channel)
|
||||
if count == self.counter_max:
|
||||
raise CounterOverflow(
|
||||
"Input edge counter overflow on RTIO channel {0}",
|
||||
int64(self.channel))
|
||||
return timestamp, count
|
||||
|
|
@ -11,99 +11,54 @@ ZeroDivisionError = builtins.ZeroDivisionError
|
|||
ValueError = builtins.ValueError
|
||||
IndexError = builtins.IndexError
|
||||
RuntimeError = builtins.RuntimeError
|
||||
AssertionError = builtins.AssertionError
|
||||
|
||||
|
||||
class CoreException:
|
||||
"""Information about an exception raised or passed through the core device."""
|
||||
def __init__(self, exceptions, exception_info, traceback, stack_pointers):
|
||||
self.exceptions = exceptions
|
||||
self.exception_info = exception_info
|
||||
self.traceback = list(traceback)
|
||||
self.stack_pointers = stack_pointers
|
||||
|
||||
first_exception = exceptions[0]
|
||||
name = first_exception[0]
|
||||
def __init__(self, name, message, params, traceback):
|
||||
if ':' in name:
|
||||
exn_id, self.name = name.split(':', 2)
|
||||
self.id = int(exn_id)
|
||||
else:
|
||||
self.id, self.name = 0, name
|
||||
self.message = first_exception[1]
|
||||
self.params = first_exception[2]
|
||||
|
||||
def append_backtrace(self, record, inlined=False):
|
||||
filename, line, column, function, address = record
|
||||
stub_globals = {"__name__": filename, "__loader__": source_loader}
|
||||
source_line = linecache.getline(filename, line, stub_globals)
|
||||
indentation = re.search(r"^\s*", source_line).end()
|
||||
|
||||
if address is None:
|
||||
formatted_address = ""
|
||||
elif inlined:
|
||||
formatted_address = " (inlined)"
|
||||
else:
|
||||
formatted_address = " (RA=+0x{:x})".format(address)
|
||||
|
||||
filename = filename.replace(artiq_dir, "<artiq>")
|
||||
lines = []
|
||||
if column == -1:
|
||||
lines.append(" {}".format(source_line.strip() if source_line else "<unknown>"))
|
||||
lines.append(" File \"{file}\", line {line}, in {function}{address}".
|
||||
format(file=filename, line=line, function=function,
|
||||
address=formatted_address))
|
||||
else:
|
||||
lines.append(" {}^".format(" " * (column - indentation)))
|
||||
lines.append(" {}".format(source_line.strip() if source_line else "<unknown>"))
|
||||
lines.append(" File \"{file}\", line {line}, column {column},"
|
||||
" in {function}{address}".
|
||||
format(file=filename, line=line, column=column + 1,
|
||||
function=function, address=formatted_address))
|
||||
return lines
|
||||
|
||||
def single_traceback(self, exception_index):
|
||||
# note that we insert in reversed order
|
||||
lines = []
|
||||
last_sp = 0
|
||||
start_backtrace_index = self.exception_info[exception_index][1]
|
||||
zipped = list(zip(self.traceback[start_backtrace_index:],
|
||||
self.stack_pointers[start_backtrace_index:]))
|
||||
exception = self.exceptions[exception_index]
|
||||
name = exception[0]
|
||||
message = exception[1]
|
||||
params = exception[2]
|
||||
if ':' in name:
|
||||
exn_id, name = name.split(':', 2)
|
||||
exn_id = int(exn_id)
|
||||
else:
|
||||
exn_id = 0
|
||||
lines.append("{}({}): {}".format(name, exn_id, message.format(*params)))
|
||||
zipped.append(((exception[3], exception[4], exception[5], exception[6],
|
||||
None, []), None))
|
||||
|
||||
for ((filename, line, column, function, address, inlined), sp) in zipped:
|
||||
# backtrace of nested exceptions may be discontinuous
|
||||
# but the stack pointer must increase monotonically
|
||||
if sp is not None and sp <= last_sp:
|
||||
continue
|
||||
last_sp = sp
|
||||
|
||||
for record in reversed(inlined):
|
||||
lines += self.append_backtrace(record, True)
|
||||
lines += self.append_backtrace((filename, line, column, function,
|
||||
address))
|
||||
|
||||
lines.append("Traceback (most recent call first):")
|
||||
|
||||
return "\n".join(reversed(lines))
|
||||
self.message, self.params = message, params
|
||||
self.traceback = list(traceback)
|
||||
|
||||
def __str__(self):
|
||||
tracebacks = [self.single_traceback(i) for i in range(len(self.exceptions))]
|
||||
traceback_str = ('\n\nDuring handling of the above exception, ' +
|
||||
'another exception occurred:\n\n').join(tracebacks)
|
||||
return 'Core Device Traceback:\n' +\
|
||||
traceback_str +\
|
||||
'\n\nEnd of Core Device Traceback\n'
|
||||
lines = []
|
||||
lines.append("Core Device Traceback (most recent call last):")
|
||||
last_address = 0
|
||||
for (filename, line, column, function, address) in self.traceback:
|
||||
stub_globals = {"__name__": filename, "__loader__": source_loader}
|
||||
source_line = linecache.getline(filename, line, stub_globals)
|
||||
indentation = re.search(r"^\s*", source_line).end()
|
||||
|
||||
if address is None:
|
||||
formatted_address = ""
|
||||
elif address == last_address:
|
||||
formatted_address = " (inlined)"
|
||||
else:
|
||||
formatted_address = " (RA=+0x{:x})".format(address)
|
||||
last_address = address
|
||||
|
||||
filename = filename.replace(artiq_dir, "<artiq>")
|
||||
if column == -1:
|
||||
lines.append(" File \"{file}\", line {line}, in {function}{address}".
|
||||
format(file=filename, line=line, function=function,
|
||||
address=formatted_address))
|
||||
lines.append(" {}".format(source_line.strip() if source_line else "<unknown>"))
|
||||
else:
|
||||
lines.append(" File \"{file}\", line {line}, column {column},"
|
||||
" in {function}{address}".
|
||||
format(file=filename, line=line, column=column + 1,
|
||||
function=function, address=formatted_address))
|
||||
lines.append(" {}".format(source_line.strip() if source_line else "<unknown>"))
|
||||
lines.append(" {}^".format(" " * (column - indentation)))
|
||||
|
||||
lines.append("{}({}): {}".format(self.name, self.id,
|
||||
self.message.format(*self.params)))
|
||||
return "\n".join(lines)
|
||||
|
||||
|
||||
class InternalError(Exception):
|
||||
|
|
@ -136,7 +91,7 @@ class RTIOOverflow(Exception):
|
|||
artiq_builtin = True
|
||||
|
||||
|
||||
class RTIODestinationUnreachable(Exception):
|
||||
class RTIOLinkError(Exception):
|
||||
"""Raised with a RTIO operation could not be completed due to a DRTIO link
|
||||
being down.
|
||||
"""
|
||||
|
|
@ -148,11 +103,8 @@ class DMAError(Exception):
|
|||
artiq_builtin = True
|
||||
|
||||
|
||||
class SubkernelError(Exception):
|
||||
"""Raised when an operation regarding a subkernel is invalid
|
||||
or cannot be completed.
|
||||
"""
|
||||
artiq_builtin = True
|
||||
class WatchdogExpired(Exception):
|
||||
"""Raised when a watchdog expires."""
|
||||
|
||||
|
||||
class ClockFailure(Exception):
|
||||
|
|
|
|||
|
|
@ -1,304 +0,0 @@
|
|||
"""RTIO driver for the Fastino 32channel, 16 bit, 2.5 MS/s per channel,
|
||||
streaming DAC.
|
||||
"""
|
||||
from numpy import int32, int64
|
||||
|
||||
from artiq.language.core import kernel, portable, delay, delay_mu
|
||||
from artiq.coredevice.rtio import (rtio_output, rtio_output_wide,
|
||||
rtio_input_data)
|
||||
from artiq.language.units import ns
|
||||
from artiq.language.types import TInt32, TList
|
||||
|
||||
|
||||
class Fastino:
|
||||
"""Fastino 32-channel, 16-bit, 2.5 MS/s per channel streaming DAC
|
||||
|
||||
The RTIO PHY supports staging DAC data before transmitting them by writing
|
||||
to the DAC RTIO addresses, if a channel is not "held" by setting its bit
|
||||
using :meth:`set_hold`, the next frame will contain the update. For the
|
||||
DACs held, the update is triggered explicitly by setting the corresponding
|
||||
bit using :meth:`set_update`. Update is self-clearing. This enables atomic
|
||||
DAC updates synchronized to a frame edge.
|
||||
|
||||
The `log2_width=0` RTIO layout uses one DAC channel per RTIO address and a
|
||||
dense RTIO address space. The RTIO words are narrow (32 bit) and
|
||||
few-channel updates are efficient. There is the least amount of DAC state
|
||||
tracking in kernels, at the cost of more DMA and RTIO data.
|
||||
The setting here and in the RTIO PHY (gateware) must match.
|
||||
|
||||
Other `log2_width` (up to `log2_width=5`) settings pack multiple
|
||||
(in powers of two) DAC channels into one group and into one RTIO write.
|
||||
The RTIO data width increases accordingly. The `log2_width`
|
||||
LSBs of the RTIO address for a DAC channel write must be zero and the
|
||||
address space is sparse. For `log2_width=5` the RTIO data is 512 bit wide.
|
||||
|
||||
If `log2_width` is zero, the :meth:`set_dac`/:meth:`set_dac_mu` interface
|
||||
must be used. If non-zero, the :meth:`set_group`/:meth:`set_group_mu`
|
||||
interface must be used.
|
||||
|
||||
:param channel: RTIO channel number
|
||||
:param core_device: Core device name (default: "core")
|
||||
:param log2_width: Width of DAC channel group (logarithm base 2).
|
||||
Value must match the corresponding value in the RTIO PHY (gateware).
|
||||
"""
|
||||
kernel_invariants = {"core", "channel", "width", "t_frame"}
|
||||
|
||||
def __init__(self, dmgr, channel, core_device="core", log2_width=0):
|
||||
self.channel = channel << 8
|
||||
self.core = dmgr.get(core_device)
|
||||
self.width = 1 << log2_width
|
||||
# frame duration in mu (14 words each 7 clock cycles each 4 ns)
|
||||
# self.core.seconds_to_mu(14*7*4*ns) # unfortunately this may round wrong
|
||||
assert self.core.ref_period == 1*ns
|
||||
self.t_frame = int64(14*7*4)
|
||||
|
||||
@staticmethod
|
||||
def get_rtio_channels(channel, **kwargs):
|
||||
return [(channel, None)]
|
||||
|
||||
@kernel
|
||||
def init(self):
|
||||
"""Initialize the device.
|
||||
|
||||
* disables RESET, DAC_CLR, enables AFE_PWR
|
||||
* clears error counters, enables error counting
|
||||
* turns LEDs off
|
||||
* clears `hold` and `continuous` on all channels
|
||||
* clear and resets interpolators to unit rate change on all
|
||||
channels
|
||||
|
||||
It does not change set channel voltages and does not reset the PLLs or clock
|
||||
domains.
|
||||
|
||||
Note: On Fastino gateware before v0.2 this may lead to 0 voltage being emitted
|
||||
transiently.
|
||||
"""
|
||||
self.set_cfg(reset=0, afe_power_down=0, dac_clr=0, clr_err=1)
|
||||
delay_mu(self.t_frame)
|
||||
self.set_cfg(reset=0, afe_power_down=0, dac_clr=0, clr_err=0)
|
||||
delay_mu(self.t_frame)
|
||||
self.set_continuous(0)
|
||||
delay_mu(self.t_frame)
|
||||
self.stage_cic(1)
|
||||
delay_mu(self.t_frame)
|
||||
self.apply_cic(0xffffffff)
|
||||
delay_mu(self.t_frame)
|
||||
self.set_leds(0)
|
||||
delay_mu(self.t_frame)
|
||||
self.set_hold(0)
|
||||
delay_mu(self.t_frame)
|
||||
|
||||
@kernel
|
||||
def write(self, addr, data):
|
||||
"""Write data to a Fastino register.
|
||||
|
||||
:param addr: Address to write to.
|
||||
:param data: Data to write.
|
||||
"""
|
||||
rtio_output(self.channel | addr, data)
|
||||
|
||||
@kernel
|
||||
def read(self, addr):
|
||||
"""Read from Fastino register.
|
||||
|
||||
TODO: untested
|
||||
|
||||
:param addr: Address to read from.
|
||||
:return: The data read.
|
||||
"""
|
||||
raise NotImplementedError
|
||||
# rtio_output(self.channel | addr | 0x80)
|
||||
# return rtio_input_data(self.channel >> 8)
|
||||
|
||||
@kernel
|
||||
def set_dac_mu(self, dac, data):
|
||||
"""Write DAC data in machine units.
|
||||
|
||||
:param dac: DAC channel to write to (0-31).
|
||||
:param data: DAC word to write, 16 bit unsigned integer, in machine
|
||||
units.
|
||||
"""
|
||||
self.write(dac, data)
|
||||
|
||||
@kernel
|
||||
def set_group_mu(self, dac: TInt32, data: TList(TInt32)):
|
||||
"""Write a group of DAC channels in machine units.
|
||||
|
||||
:param dac: First channel in DAC channel group (0-31). The `log2_width`
|
||||
LSBs must be zero.
|
||||
:param data: List of DAC data pairs (2x16 bit unsigned) to write,
|
||||
in machine units. Data exceeding group size is ignored.
|
||||
If the list length is less than group size, the remaining
|
||||
DAC channels within the group are cleared to 0 (machine units).
|
||||
"""
|
||||
if dac & (self.width - 1):
|
||||
raise ValueError("Group index LSBs must be zero")
|
||||
rtio_output_wide(self.channel | dac, data)
|
||||
|
||||
@portable
|
||||
def voltage_to_mu(self, voltage):
|
||||
"""Convert SI Volts to DAC machine units.
|
||||
|
||||
:param voltage: Voltage in SI Volts.
|
||||
:return: DAC data word in machine units, 16 bit integer.
|
||||
"""
|
||||
data = int32(round((0x8000/10.)*voltage)) + int32(0x8000)
|
||||
if data < 0 or data > 0xffff:
|
||||
raise ValueError("DAC voltage out of bounds")
|
||||
return data
|
||||
|
||||
@portable
|
||||
def voltage_group_to_mu(self, voltage, data):
|
||||
"""Convert SI Volts to packed DAC channel group machine units.
|
||||
|
||||
:param voltage: List of SI Volt voltages.
|
||||
:param data: List of DAC channel data pairs to write to.
|
||||
Half the length of `voltage`.
|
||||
"""
|
||||
for i in range(len(voltage)):
|
||||
v = self.voltage_to_mu(voltage[i])
|
||||
if i & 1:
|
||||
v = data[i // 2] | (v << 16)
|
||||
data[i // 2] = int32(v)
|
||||
|
||||
@kernel
|
||||
def set_dac(self, dac, voltage):
|
||||
"""Set DAC data to given voltage.
|
||||
|
||||
:param dac: DAC channel (0-31).
|
||||
:param voltage: Desired output voltage.
|
||||
"""
|
||||
self.write(dac, self.voltage_to_mu(voltage))
|
||||
|
||||
@kernel
|
||||
def set_group(self, dac, voltage):
|
||||
"""Set DAC group data to given voltage.
|
||||
|
||||
:param dac: DAC channel (0-31).
|
||||
:param voltage: Desired output voltage.
|
||||
"""
|
||||
data = [int32(0)] * (len(voltage) // 2)
|
||||
self.voltage_group_to_mu(voltage, data)
|
||||
self.set_group_mu(dac, data)
|
||||
|
||||
@kernel
|
||||
def update(self, update):
|
||||
"""Schedule channels for update.
|
||||
|
||||
:param update: Bit mask of channels to update (32 bit).
|
||||
"""
|
||||
self.write(0x20, update)
|
||||
|
||||
@kernel
|
||||
def set_hold(self, hold):
|
||||
"""Set channels to manual update.
|
||||
|
||||
:param hold: Bit mask of channels to hold (32 bit).
|
||||
"""
|
||||
self.write(0x21, hold)
|
||||
|
||||
@kernel
|
||||
def set_cfg(self, reset=0, afe_power_down=0, dac_clr=0, clr_err=0):
|
||||
"""Set configuration bits.
|
||||
|
||||
:param reset: Reset SPI PLL and SPI clock domain.
|
||||
:param afe_power_down: Disable AFE power.
|
||||
:param dac_clr: Assert all 32 DAC_CLR signals setting all DACs to
|
||||
mid-scale (0 V).
|
||||
:param clr_err: Clear error counters and PLL reset indicator.
|
||||
This clears the sticky red error LED. Must be cleared to enable
|
||||
error counting.
|
||||
"""
|
||||
self.write(0x22, (reset << 0) | (afe_power_down << 1) |
|
||||
(dac_clr << 2) | (clr_err << 3))
|
||||
|
||||
@kernel
|
||||
def set_leds(self, leds):
|
||||
"""Set the green user-defined LEDs
|
||||
|
||||
:param leds: LED status, 8 bit integer each bit corresponding to one
|
||||
green LED.
|
||||
"""
|
||||
self.write(0x23, leds)
|
||||
|
||||
@kernel
|
||||
def set_continuous(self, channel_mask):
|
||||
"""Enable continuous DAC updates on channels regardless of new data
|
||||
being submitted.
|
||||
"""
|
||||
self.write(0x25, channel_mask)
|
||||
|
||||
@kernel
|
||||
def stage_cic_mu(self, rate_mantissa, rate_exponent, gain_exponent):
|
||||
"""Stage machine unit CIC interpolator configuration.
|
||||
"""
|
||||
if rate_mantissa < 0 or rate_mantissa >= 1 << 6:
|
||||
raise ValueError("rate_mantissa out of bounds")
|
||||
if rate_exponent < 0 or rate_exponent >= 1 << 4:
|
||||
raise ValueError("rate_exponent out of bounds")
|
||||
if gain_exponent < 0 or gain_exponent >= 1 << 6:
|
||||
raise ValueError("gain_exponent out of bounds")
|
||||
config = rate_mantissa | (rate_exponent << 6) | (gain_exponent << 10)
|
||||
self.write(0x26, config)
|
||||
|
||||
@kernel
|
||||
def stage_cic(self, rate) -> TInt32:
|
||||
"""Compute and stage interpolator configuration.
|
||||
|
||||
This method approximates the desired interpolation rate using a 10 bit
|
||||
floating point representation (6 bit mantissa, 4 bit exponent) and
|
||||
then determines an optimal interpolation gain compensation exponent
|
||||
to avoid clipping. Gains for rates that are powers of two are accurately
|
||||
compensated. Other rates lead to overall less than unity gain (but more
|
||||
than 0.5 gain).
|
||||
|
||||
The overall gain including gain compensation is
|
||||
`actual_rate**order/2**ceil(log2(actual_rate**order))`
|
||||
where `order = 3`.
|
||||
|
||||
Returns the actual interpolation rate.
|
||||
"""
|
||||
if rate <= 0 or rate > 1 << 16:
|
||||
raise ValueError("rate out of bounds")
|
||||
rate_mantissa = rate
|
||||
rate_exponent = 0
|
||||
while rate_mantissa > 1 << 6:
|
||||
rate_exponent += 1
|
||||
rate_mantissa >>= 1
|
||||
order = 3
|
||||
gain = 1
|
||||
for i in range(order):
|
||||
gain *= rate_mantissa
|
||||
gain_exponent = 0
|
||||
while gain > 1 << gain_exponent:
|
||||
gain_exponent += 1
|
||||
gain_exponent += order*rate_exponent
|
||||
assert gain_exponent <= order*16
|
||||
self.stage_cic_mu(rate_mantissa - 1, rate_exponent, gain_exponent)
|
||||
return rate_mantissa << rate_exponent
|
||||
|
||||
@kernel
|
||||
def apply_cic(self, channel_mask):
|
||||
"""Apply the staged interpolator configuration on the specified channels.
|
||||
|
||||
Each Fastino channel starting with gateware v0.2 includes a fourth order
|
||||
(cubic) CIC interpolator with variable rate change and variable output
|
||||
gain compensation (see :meth:`stage_cic`).
|
||||
|
||||
Fastino gateware before v0.2 does not include the interpolators and the
|
||||
methods affecting the CICs should not be used.
|
||||
|
||||
Channels using non-unity interpolation rate should have
|
||||
continous DAC updates enabled (see :meth:`set_continuous`) unless
|
||||
their output is supposed to be constant.
|
||||
|
||||
This method resets and settles the affected interpolators. There will be
|
||||
no output updates for the next `order = 3` input samples.
|
||||
Affected channels will only accept one input sample per input sample
|
||||
period. This method synchronizes the input sample period to the current
|
||||
frame on the affected channels.
|
||||
|
||||
If application of new interpolator settings results in a change of the
|
||||
overall gain, there will be a corresponding output step.
|
||||
"""
|
||||
self.write(0x27, channel_mask)
|
||||
|
|
@ -23,11 +23,7 @@ class Grabber:
|
|||
count_width = min(31, 2*res_width + 16 - count_shift)
|
||||
# This value is inserted by the gateware to mark the start of a series of
|
||||
# ROI engine outputs for one video frame.
|
||||
self.sentinel = int32(int64(2**count_width))
|
||||
|
||||
@staticmethod
|
||||
def get_rtio_channels(channel_base, **kwargs):
|
||||
return [(channel_base, "ROI coordinates"), (channel_base + 1, "ROI mask")]
|
||||
self.sentinel = int32(2**count_width)
|
||||
|
||||
@kernel
|
||||
def setup_roi(self, n, x0, y0, x1, y1):
|
||||
|
|
@ -44,13 +40,13 @@ class Grabber:
|
|||
Advances the timeline by 4 coarse RTIO cycles.
|
||||
"""
|
||||
c = int64(self.core.ref_multiplier)
|
||||
rtio_output((self.channel_base << 8) | (4*n+0), x0)
|
||||
rtio_output(now_mu(), self.channel_base, 4*n+0, x0)
|
||||
delay_mu(c)
|
||||
rtio_output((self.channel_base << 8) | (4*n+1), y0)
|
||||
rtio_output(now_mu(), self.channel_base, 4*n+1, y0)
|
||||
delay_mu(c)
|
||||
rtio_output((self.channel_base << 8) | (4*n+2), x1)
|
||||
rtio_output(now_mu(), self.channel_base, 4*n+2, x1)
|
||||
delay_mu(c)
|
||||
rtio_output((self.channel_base << 8) | (4*n+3), y1)
|
||||
rtio_output(now_mu(), self.channel_base, 4*n+3, y1)
|
||||
delay_mu(c)
|
||||
|
||||
@kernel
|
||||
|
|
@ -71,7 +67,7 @@ class Grabber:
|
|||
|
||||
:param mask: bitmask enabling or disabling each ROI engine.
|
||||
"""
|
||||
rtio_output((self.channel_base + 1) << 8, mask)
|
||||
rtio_output(now_mu(), self.channel_base+1, 0, mask)
|
||||
|
||||
@kernel
|
||||
def gate_roi_pulse(self, mask, dt):
|
||||
|
|
|
|||
|
|
@ -33,11 +33,6 @@ def i2c_read(busno: TInt32, ack: TBool) -> TInt32:
|
|||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
|
||||
@syscall(flags={"nounwind", "nowrite"})
|
||||
def i2c_switch_select(busno: TInt32, address: TInt32, mask: TInt32) -> TNone:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
|
||||
@kernel
|
||||
def i2c_poll(busno, busaddr):
|
||||
"""Poll I2C device at address.
|
||||
|
|
@ -142,10 +137,8 @@ def i2c_read_many(busno, busaddr, addr, data):
|
|||
i2c_stop(busno)
|
||||
|
||||
|
||||
class I2CSwitch:
|
||||
"""Driver for the I2C bus switch.
|
||||
|
||||
PCA954X (or other) type detection is done by the CPU during I2C init.
|
||||
class PCA9548:
|
||||
"""Driver for the PCA9548 I2C bus switch.
|
||||
|
||||
I2C transactions not real-time, and are performed by the CPU without
|
||||
involving RTIO.
|
||||
|
|
@ -158,19 +151,25 @@ class I2CSwitch:
|
|||
self.busno = busno
|
||||
self.address = address
|
||||
|
||||
@kernel
|
||||
def select(self, mask):
|
||||
"""Enable/disable channels.
|
||||
|
||||
:param mask: Bit mask of enabled channels
|
||||
"""
|
||||
i2c_write_byte(self.busno, self.address, mask)
|
||||
|
||||
@kernel
|
||||
def set(self, channel):
|
||||
"""Enable one channel.
|
||||
|
||||
:param channel: channel number (0-7)
|
||||
"""
|
||||
i2c_switch_select(self.busno, self.address >> 1, 1 << channel)
|
||||
self.select(1 << channel)
|
||||
|
||||
@kernel
|
||||
def unset(self):
|
||||
"""Disable output of the I2C switch.
|
||||
"""
|
||||
i2c_switch_select(self.busno, self.address >> 1, 0)
|
||||
def readback(self):
|
||||
return i2c_read_byte(self.busno, self.address)
|
||||
|
||||
|
||||
class TCA6424A:
|
||||
|
|
@ -208,46 +207,3 @@ class TCA6424A:
|
|||
|
||||
self._write24(0x8c, 0) # set all directions to output
|
||||
self._write24(0x84, outputs_le) # set levels
|
||||
|
||||
class PCF8574A:
|
||||
"""Driver for the PCF8574 I2C remote 8-bit I/O expander.
|
||||
|
||||
I2C transactions not real-time, and are performed by the CPU without
|
||||
involving RTIO.
|
||||
"""
|
||||
def __init__(self, dmgr, busno=0, address=0x7c, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.busno = busno
|
||||
self.address = address
|
||||
|
||||
@kernel
|
||||
def set(self, data):
|
||||
"""Drive data on the quasi-bidirectional pins.
|
||||
|
||||
:param data: Pin data. High bits are weakly driven high
|
||||
(and thus inputs), low bits are strongly driven low.
|
||||
"""
|
||||
i2c_start(self.busno)
|
||||
try:
|
||||
if not i2c_write(self.busno, self.address):
|
||||
raise I2CError("PCF8574A failed to ack address")
|
||||
if not i2c_write(self.busno, data):
|
||||
raise I2CError("PCF8574A failed to ack data")
|
||||
finally:
|
||||
i2c_stop(self.busno)
|
||||
|
||||
@kernel
|
||||
def get(self):
|
||||
"""Retrieve quasi-bidirectional pin input data.
|
||||
|
||||
:return: Pin data
|
||||
"""
|
||||
i2c_start(self.busno)
|
||||
ret = 0
|
||||
try:
|
||||
if not i2c_write(self.busno, self.address | 1):
|
||||
raise I2CError("PCF8574A failed to ack address")
|
||||
ret = i2c_read(self.busno, False)
|
||||
finally:
|
||||
i2c_stop(self.busno)
|
||||
return ret
|
||||
|
|
|
|||
|
|
@ -1,38 +0,0 @@
|
|||
from os import path
|
||||
import json
|
||||
from jsonschema import Draft7Validator, validators
|
||||
|
||||
def extend_with_default(validator_class):
|
||||
validate_properties = validator_class.VALIDATORS["properties"]
|
||||
|
||||
def set_defaults(validator, properties, instance, schema):
|
||||
for property, subschema in properties.items():
|
||||
if "default" in subschema:
|
||||
instance.setdefault(property, subschema["default"])
|
||||
|
||||
for error in validate_properties(
|
||||
validator, properties, instance, schema,
|
||||
):
|
||||
yield error
|
||||
|
||||
return validators.extend(
|
||||
validator_class, {"properties" : set_defaults},
|
||||
)
|
||||
|
||||
schema_path = path.join(path.dirname(__file__), "coredevice_generic.schema.json")
|
||||
with open(schema_path, "r") as f:
|
||||
schema = json.load(f)
|
||||
|
||||
validator = extend_with_default(Draft7Validator)(schema)
|
||||
|
||||
def load(description_path):
|
||||
with open(description_path, "r") as f:
|
||||
result = json.load(f)
|
||||
|
||||
global validator
|
||||
validator.validate(result)
|
||||
|
||||
if result["base"] != "use_drtio_role":
|
||||
result["drtio_role"] = result["base"]
|
||||
|
||||
return result
|
||||
|
|
@ -1,77 +0,0 @@
|
|||
from numpy import int32
|
||||
|
||||
from artiq.experiment import *
|
||||
from artiq.coredevice.i2c import i2c_write_many, i2c_read_many, i2c_poll
|
||||
|
||||
|
||||
port_mapping = {
|
||||
"EEM0": 7,
|
||||
"EEM1": 5,
|
||||
"EEM2": 4,
|
||||
"EEM3": 3,
|
||||
"EEM4": 2,
|
||||
"EEM5": 1,
|
||||
"EEM6": 0,
|
||||
"EEM7": 6,
|
||||
"EEM8": 12,
|
||||
"EEM9": 13,
|
||||
"EEM10": 15,
|
||||
"EEM11": 14,
|
||||
"SFP0": 8,
|
||||
"SFP1": 9,
|
||||
"SFP2": 10,
|
||||
"LOC0": 11,
|
||||
}
|
||||
|
||||
|
||||
class KasliEEPROM:
|
||||
def __init__(self, dmgr, port, busno=0,
|
||||
core_device="core", sw0_device="i2c_switch0", sw1_device="i2c_switch1"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.sw0 = dmgr.get(sw0_device)
|
||||
self.sw1 = dmgr.get(sw1_device)
|
||||
self.busno = busno
|
||||
self.port = port_mapping[port]
|
||||
self.address = 0xa0 # i2c 8 bit
|
||||
|
||||
@kernel
|
||||
def select(self):
|
||||
mask = 1 << self.port
|
||||
if self.port < 8:
|
||||
self.sw0.set(self.port)
|
||||
self.sw1.unset()
|
||||
else:
|
||||
self.sw0.unset()
|
||||
self.sw1.set(self.port - 8)
|
||||
|
||||
@kernel
|
||||
def deselect(self):
|
||||
self.sw0.unset()
|
||||
self.sw1.unset()
|
||||
|
||||
@kernel
|
||||
def write_i32(self, addr, value):
|
||||
self.select()
|
||||
try:
|
||||
data = [0]*4
|
||||
for i in range(4):
|
||||
data[i] = (value >> 24) & 0xff
|
||||
value <<= 8
|
||||
i2c_write_many(self.busno, self.address, addr, data)
|
||||
i2c_poll(self.busno, self.address)
|
||||
finally:
|
||||
self.deselect()
|
||||
|
||||
@kernel
|
||||
def read_i32(self, addr):
|
||||
self.select()
|
||||
try:
|
||||
data = [0]*4
|
||||
i2c_read_many(self.busno, self.address, addr, data)
|
||||
value = int32(0)
|
||||
for i in range(4):
|
||||
value <<= 8
|
||||
value |= data[i]
|
||||
finally:
|
||||
self.deselect()
|
||||
return value
|
||||
|
|
@ -1,169 +0,0 @@
|
|||
"""RTIO driver for Mirny (4 channel GHz PLLs)
|
||||
"""
|
||||
|
||||
from artiq.language.core import kernel, delay, portable
|
||||
from artiq.language.units import us
|
||||
|
||||
from numpy import int32
|
||||
|
||||
from artiq.coredevice import spi2 as spi
|
||||
|
||||
|
||||
SPI_CONFIG = (
|
||||
0 * spi.SPI_OFFLINE
|
||||
| 0 * spi.SPI_END
|
||||
| 0 * spi.SPI_INPUT
|
||||
| 1 * spi.SPI_CS_POLARITY
|
||||
| 0 * spi.SPI_CLK_POLARITY
|
||||
| 0 * spi.SPI_CLK_PHASE
|
||||
| 0 * spi.SPI_LSB_FIRST
|
||||
| 0 * spi.SPI_HALF_DUPLEX
|
||||
)
|
||||
|
||||
# SPI clock write and read dividers
|
||||
SPIT_WR = 4
|
||||
SPIT_RD = 16
|
||||
|
||||
SPI_CS = 1
|
||||
|
||||
WE = 1 << 24
|
||||
|
||||
# supported CPLD code version
|
||||
PROTO_REV_MATCH = 0x0
|
||||
|
||||
|
||||
class Mirny:
|
||||
"""
|
||||
Mirny PLL-based RF generator.
|
||||
|
||||
:param spi_device: SPI bus device
|
||||
:param refclk: Reference clock (SMA, MMCX or on-board 100 MHz oscillator)
|
||||
frequency in Hz
|
||||
:param clk_sel: Reference clock selection.
|
||||
Valid options are: "XO" - onboard crystal oscillator;
|
||||
"SMA" - front-panel SMA connector; "MMCX" - internal MMCX connector.
|
||||
Passing an integer writes it as ``clk_sel`` in the CPLD's register 1.
|
||||
The effect depends on the hardware revision.
|
||||
:param core_device: Core device name (default: "core")
|
||||
"""
|
||||
|
||||
kernel_invariants = {"bus", "core", "refclk", "clk_sel_hw_rev"}
|
||||
|
||||
def __init__(self, dmgr, spi_device, refclk=100e6, clk_sel="XO", core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.bus = dmgr.get(spi_device)
|
||||
|
||||
# reference clock frequency
|
||||
self.refclk = refclk
|
||||
if not (10 <= self.refclk / 1e6 <= 600):
|
||||
raise ValueError("Invalid refclk")
|
||||
|
||||
# reference clock selection
|
||||
try:
|
||||
self.clk_sel_hw_rev = {
|
||||
# clk source: [reserved, reserved, v1.1, v1.0]
|
||||
"xo": [-1, -1, 0, 0],
|
||||
"mmcx": [-1, -1, 3, 2],
|
||||
"sma": [-1, -1, 2, 3],
|
||||
}[clk_sel.lower()]
|
||||
except AttributeError: # not a string, fallback to int
|
||||
if clk_sel & 0x3 != clk_sel:
|
||||
raise ValueError("Invalid clk_sel") from None
|
||||
self.clk_sel_hw_rev = [clk_sel] * 4
|
||||
except KeyError:
|
||||
raise ValueError("Invalid clk_sel") from None
|
||||
|
||||
self.clk_sel = -1
|
||||
|
||||
# board hardware revision
|
||||
self.hw_rev = 0 # v1.0: 3, v1.1: 2
|
||||
|
||||
# TODO: support clk_div on v1.0 boards
|
||||
|
||||
@kernel
|
||||
def read_reg(self, addr):
|
||||
"""Read a register"""
|
||||
self.bus.set_config_mu(
|
||||
SPI_CONFIG | spi.SPI_INPUT | spi.SPI_END, 24, SPIT_RD, SPI_CS
|
||||
)
|
||||
self.bus.write((addr << 25))
|
||||
return self.bus.read() & int32(0xFFFF)
|
||||
|
||||
@kernel
|
||||
def write_reg(self, addr, data):
|
||||
"""Write a register"""
|
||||
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 24, SPIT_WR, SPI_CS)
|
||||
self.bus.write((addr << 25) | WE | ((data & 0xFFFF) << 8))
|
||||
|
||||
@kernel
|
||||
def init(self, blind=False):
|
||||
"""
|
||||
Initialize and detect Mirny.
|
||||
|
||||
Select the clock source based the board's hardware revision.
|
||||
Raise ValueError if the board's hardware revision is not supported.
|
||||
|
||||
:param blind: Verify presence and protocol compatibility. Raise ValueError on failure.
|
||||
"""
|
||||
reg0 = self.read_reg(0)
|
||||
self.hw_rev = reg0 & 0x3
|
||||
|
||||
if not blind:
|
||||
if (reg0 >> 2) & 0x3 != PROTO_REV_MATCH:
|
||||
raise ValueError("Mirny PROTO_REV mismatch")
|
||||
delay(100 * us) # slack
|
||||
|
||||
# select clock source
|
||||
self.clk_sel = self.clk_sel_hw_rev[self.hw_rev]
|
||||
|
||||
if self.clk_sel < 0:
|
||||
raise ValueError("Hardware revision not supported")
|
||||
|
||||
self.write_reg(1, (self.clk_sel << 4))
|
||||
delay(1000 * us)
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def att_to_mu(self, att):
|
||||
"""Convert an attenuation setting in dB to machine units.
|
||||
|
||||
:param att: Attenuation setting in dB.
|
||||
:return: Digital attenuation setting.
|
||||
"""
|
||||
code = int32(255) - int32(round(att * 8))
|
||||
if code < 0 or code > 255:
|
||||
raise ValueError("Invalid Mirny attenuation!")
|
||||
return code
|
||||
|
||||
@kernel
|
||||
def set_att_mu(self, channel, att):
|
||||
"""Set digital step attenuator in machine units.
|
||||
|
||||
:param att: Attenuation setting, 8 bit digital.
|
||||
"""
|
||||
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 16, SPIT_WR, SPI_CS)
|
||||
self.bus.write(((channel | 8) << 25) | (att << 16))
|
||||
|
||||
@kernel
|
||||
def set_att(self, channel, att):
|
||||
"""Set digital step attenuator in SI units.
|
||||
|
||||
This method will write the attenuator settings of the selected channel.
|
||||
|
||||
.. seealso:: :meth:`set_att_mu`
|
||||
|
||||
:param channel: Attenuator channel (0-3).
|
||||
:param att: Attenuation setting in dB. Higher value is more
|
||||
attenuation. Minimum attenuation is 0*dB, maximum attenuation is
|
||||
31.5*dB.
|
||||
"""
|
||||
self.set_att_mu(channel, self.att_to_mu(att))
|
||||
|
||||
@kernel
|
||||
def write_ext(self, addr, length, data, ext_div=SPIT_WR):
|
||||
"""Perform SPI write to a prefixed address"""
|
||||
self.bus.set_config_mu(SPI_CONFIG, 8, SPIT_WR, SPI_CS)
|
||||
self.bus.write(addr << 25)
|
||||
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, length, ext_div, SPI_CS)
|
||||
if length < 32:
|
||||
data <<= 32 - length
|
||||
self.bus.write(data)
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
from artiq.experiment import kernel
|
||||
from artiq.coredevice.i2c import (
|
||||
i2c_start, i2c_write, i2c_read, i2c_stop, I2CError)
|
||||
|
||||
|
||||
class PCF8574A:
|
||||
"""Driver for the PCF8574 I2C remote 8-bit I/O expander.
|
||||
|
||||
I2C transactions not real-time, and are performed by the CPU without
|
||||
involving RTIO.
|
||||
"""
|
||||
def __init__(self, dmgr, busno=0, address=0x7c, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.busno = busno
|
||||
self.address = address
|
||||
|
||||
@kernel
|
||||
def set(self, data):
|
||||
"""Drive data on the quasi-bidirectional pins.
|
||||
|
||||
:param data: Pin data. High bits are weakly driven high
|
||||
(and thus inputs), low bits are strongly driven low.
|
||||
"""
|
||||
i2c_start(self.busno)
|
||||
try:
|
||||
if not i2c_write(self.busno, self.address):
|
||||
raise I2CError("PCF8574A failed to ack address")
|
||||
if not i2c_write(self.busno, data):
|
||||
raise I2CError("PCF8574A failed to ack data")
|
||||
finally:
|
||||
i2c_stop(self.busno)
|
||||
|
||||
@kernel
|
||||
def get(self):
|
||||
"""Retrieve quasi-bidirectional pin input data.
|
||||
|
||||
:return: Pin data
|
||||
"""
|
||||
i2c_start(self.busno)
|
||||
ret = 0
|
||||
try:
|
||||
if not i2c_write(self.busno, self.address | 1):
|
||||
raise I2CError("PCF8574A failed to ack address")
|
||||
ret = i2c_read(self.busno, False)
|
||||
finally:
|
||||
i2c_stop(self.busno)
|
||||
return ret
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
from .spr import mtspr, mfspr
|
||||
from artiq.language.core import kernel
|
||||
|
||||
|
||||
_MAX_SPRS_PER_GRP_BITS = 11
|
||||
_SPRGROUP_PC = 7 << _MAX_SPRS_PER_GRP_BITS
|
||||
_SPR_PCMR_CP = 0x00000001 # Counter present
|
||||
_SPR_PCMR_CISM = 0x00000004 # Count in supervisor mode
|
||||
_SPR_PCMR_CIUM = 0x00000008 # Count in user mode
|
||||
_SPR_PCMR_LA = 0x00000010 # Load access event
|
||||
_SPR_PCMR_SA = 0x00000020 # Store access event
|
||||
_SPR_PCMR_IF = 0x00000040 # Instruction fetch event
|
||||
_SPR_PCMR_DCM = 0x00000080 # Data cache miss event
|
||||
_SPR_PCMR_ICM = 0x00000100 # Insn cache miss event
|
||||
_SPR_PCMR_IFS = 0x00000200 # Insn fetch stall event
|
||||
_SPR_PCMR_LSUS = 0x00000400 # LSU stall event
|
||||
_SPR_PCMR_BS = 0x00000800 # Branch stall event
|
||||
_SPR_PCMR_DTLBM = 0x00001000 # DTLB miss event
|
||||
_SPR_PCMR_ITLBM = 0x00002000 # ITLB miss event
|
||||
_SPR_PCMR_DDS = 0x00004000 # Data dependency stall event
|
||||
_SPR_PCMR_WPE = 0x03ff8000 # Watchpoint events
|
||||
|
||||
|
||||
@kernel(flags={"nowrite", "nounwind"})
|
||||
def _PCCR(n):
|
||||
return _SPRGROUP_PC + n
|
||||
|
||||
|
||||
@kernel(flags={"nowrite", "nounwind"})
|
||||
def _PCMR(n):
|
||||
return _SPRGROUP_PC + 8 + n
|
||||
|
||||
|
||||
class CorePCU:
|
||||
"""Core device performance counter unit (PCU) access"""
|
||||
def __init__(self, dmgr, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
|
||||
@kernel
|
||||
def start(self):
|
||||
"""
|
||||
Configure and clear the kernel CPU performance counters.
|
||||
|
||||
The eight counters are configured to count the following events:
|
||||
* Load or store
|
||||
* Instruction fetch
|
||||
* Data cache miss
|
||||
* Instruction cache miss
|
||||
* Instruction fetch stall
|
||||
* Load-store-unit stall
|
||||
* Branch stall
|
||||
* Data dependency stall
|
||||
"""
|
||||
for i in range(8):
|
||||
if not mfspr(_PCMR(i)) & _SPR_PCMR_CP:
|
||||
raise ValueError("counter not present")
|
||||
mtspr(_PCMR(i), 0)
|
||||
mtspr(_PCCR(i), 0)
|
||||
mtspr(_PCMR(0), _SPR_PCMR_CISM | _SPR_PCMR_LA | _SPR_PCMR_SA)
|
||||
mtspr(_PCMR(1), _SPR_PCMR_CISM | _SPR_PCMR_IF)
|
||||
mtspr(_PCMR(2), _SPR_PCMR_CISM | _SPR_PCMR_DCM)
|
||||
mtspr(_PCMR(3), _SPR_PCMR_CISM | _SPR_PCMR_ICM)
|
||||
mtspr(_PCMR(4), _SPR_PCMR_CISM | _SPR_PCMR_IFS)
|
||||
mtspr(_PCMR(5), _SPR_PCMR_CISM | _SPR_PCMR_LSUS)
|
||||
mtspr(_PCMR(6), _SPR_PCMR_CISM | _SPR_PCMR_BS)
|
||||
mtspr(_PCMR(7), _SPR_PCMR_CISM | _SPR_PCMR_DDS)
|
||||
|
||||
@kernel
|
||||
def get(self, r):
|
||||
"""
|
||||
Read the performance counters and store the counts in the
|
||||
array provided.
|
||||
|
||||
:param list[int] r: array to store the counter values
|
||||
"""
|
||||
for i in range(8):
|
||||
r[i] = mfspr(_PCCR(i))
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,92 @@
|
|||
from collections import defaultdict
|
||||
import subprocess
|
||||
|
||||
|
||||
class Symbolizer:
|
||||
def __init__(self, binary, triple, demangle=True):
|
||||
cmdline = [
|
||||
triple + "-addr2line", "--exe=" + binary,
|
||||
"--addresses", "--functions", "--inlines"
|
||||
]
|
||||
if demangle:
|
||||
cmdline.append("--demangle=rust")
|
||||
self._addr2line = subprocess.Popen(cmdline, stdin=subprocess.PIPE, stdout=subprocess.PIPE,
|
||||
universal_newlines=True)
|
||||
|
||||
def symbolize(self, addr):
|
||||
self._addr2line.stdin.write("0x{:08x}\n0\n".format(addr))
|
||||
self._addr2line.stdin.flush()
|
||||
self._addr2line.stdout.readline() # 0x[addr]
|
||||
|
||||
result = []
|
||||
while True:
|
||||
function = self._addr2line.stdout.readline().rstrip()
|
||||
|
||||
# check for end marker
|
||||
if function == "0x00000000": # 0x00000000
|
||||
self._addr2line.stdout.readline() # ??
|
||||
self._addr2line.stdout.readline() # ??:0
|
||||
return result
|
||||
|
||||
file, line = self._addr2line.stdout.readline().rstrip().split(":")
|
||||
|
||||
result.append((function, file, line, addr))
|
||||
|
||||
|
||||
class CallgrindWriter:
|
||||
def __init__(self, output, binary, triple, compression=True, demangle=True):
|
||||
self._output = output
|
||||
self._binary = binary
|
||||
self._current = defaultdict(lambda: None)
|
||||
self._ids = defaultdict(lambda: {})
|
||||
self._compression = compression
|
||||
self._symbolizer = Symbolizer(binary, triple, demangle=demangle)
|
||||
|
||||
def _write(self, fmt, *args, **kwargs):
|
||||
self._output.write(fmt.format(*args, **kwargs))
|
||||
self._output.write("\n")
|
||||
|
||||
def _spec(self, spec, value):
|
||||
if self._current[spec] == value:
|
||||
return
|
||||
self._current[spec] = value
|
||||
|
||||
if not self._compression or value == "??":
|
||||
self._write("{}={}", spec, value)
|
||||
return
|
||||
|
||||
spec_ids = self._ids[spec]
|
||||
if value in spec_ids:
|
||||
self._write("{}=({})", spec, spec_ids[value])
|
||||
else:
|
||||
spec_ids[value] = len(spec_ids) + 1
|
||||
self._write("{}=({}) {}", spec, spec_ids[value], value)
|
||||
|
||||
def header(self):
|
||||
self._write("# callgrind format")
|
||||
self._write("version: 1")
|
||||
self._write("creator: ARTIQ")
|
||||
self._write("positions: instr line")
|
||||
self._write("events: Hits")
|
||||
self._write("")
|
||||
self._spec("ob", self._binary)
|
||||
self._spec("cob", self._binary)
|
||||
|
||||
def hit(self, addr, count):
|
||||
for function, file, line, addr in self._symbolizer.symbolize(addr):
|
||||
self._spec("fl", file)
|
||||
self._spec("fn", function)
|
||||
self._write("0x{:08x} {} {}", addr, line, count)
|
||||
|
||||
def edge(self, caller, callee, count):
|
||||
edges = self._symbolizer.symbolize(callee) + self._symbolizer.symbolize(caller)
|
||||
for (callee, caller) in zip(edges, edges[1:]):
|
||||
function, file, line, addr = callee
|
||||
self._spec("cfl", file)
|
||||
self._spec("cfn", function)
|
||||
self._write("calls={} 0x{:08x} {}", count, addr, line)
|
||||
|
||||
function, file, line, addr = caller
|
||||
self._spec("fl", file)
|
||||
self._spec("fn", function)
|
||||
self._write("0x{:08x} {} {}", addr, line, count)
|
||||
|
|
@ -1,14 +1,16 @@
|
|||
from artiq.language.core import syscall
|
||||
from artiq.language.types import TInt32, TInt64, TList, TNone, TTuple
|
||||
from artiq.language.types import TInt64, TInt32, TNone, TList
|
||||
|
||||
|
||||
@syscall(flags={"nowrite"})
|
||||
def rtio_output(target: TInt32, data: TInt32) -> TNone:
|
||||
def rtio_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
|
||||
) -> TNone:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
|
||||
@syscall(flags={"nowrite"})
|
||||
def rtio_output_wide(target: TInt32, data: TList(TInt32)) -> TNone:
|
||||
def rtio_output_wide(time_mu: TInt64, channel: TInt32, addr: TInt32,
|
||||
data: TList(TInt32)) -> TNone:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
|
||||
|
|
@ -20,12 +22,3 @@ def rtio_input_timestamp(timeout_mu: TInt64, channel: TInt32) -> TInt64:
|
|||
@syscall(flags={"nowrite"})
|
||||
def rtio_input_data(channel: TInt32) -> TInt32:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
|
||||
@syscall(flags={"nowrite"})
|
||||
def rtio_input_timestamped_data(timeout_mu: TInt64,
|
||||
channel: TInt32) -> TTuple([TInt64, TInt32]):
|
||||
"""Wait for an input event up to timeout_mu on the given channel, and
|
||||
return a tuple of timestamp and attached data, or (-1, 0) if the timeout is
|
||||
reached."""
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
|
|
|||
|
|
@ -15,26 +15,24 @@ SPI_CS_PGIA = 1 # separate SPI bus, CS used as RCLK
|
|||
|
||||
|
||||
@portable
|
||||
def adc_mu_to_volt(data, gain=0, corrected_fs=True):
|
||||
def adc_mu_to_volt(data, gain=0):
|
||||
"""Convert ADC data in machine units to Volts.
|
||||
|
||||
:param data: 16 bit signed ADC word
|
||||
:param gain: PGIA gain setting (0: 1, ..., 3: 1000)
|
||||
:param corrected_fs: use corrected ADC FS reference.
|
||||
Should be True for Samplers' revisions after v2.1. False for v2.1 and earlier.
|
||||
:return: Voltage in Volts
|
||||
"""
|
||||
if gain == 0:
|
||||
volt_per_lsb = 20.48 / (1 << 16) if corrected_fs else 20. / (1 << 16)
|
||||
volt_per_lsb = 20./(1 << 16)
|
||||
elif gain == 1:
|
||||
volt_per_lsb = 2.048 / (1 << 16) if corrected_fs else 2. / (1 << 16)
|
||||
volt_per_lsb = 2./(1 << 16)
|
||||
elif gain == 2:
|
||||
volt_per_lsb = .2048 / (1 << 16) if corrected_fs else .2 / (1 << 16)
|
||||
volt_per_lsb = .2/(1 << 16)
|
||||
elif gain == 3:
|
||||
volt_per_lsb = 0.02048 / (1 << 16) if corrected_fs else .02 / (1 << 16)
|
||||
volt_per_lsb = .02/(1 << 16)
|
||||
else:
|
||||
raise ValueError("invalid gain")
|
||||
return data * volt_per_lsb
|
||||
return data*volt_per_lsb
|
||||
|
||||
|
||||
class Sampler:
|
||||
|
|
@ -50,13 +48,12 @@ class Sampler:
|
|||
:param gains: Initial value for PGIA gains shift register
|
||||
(default: 0x0000). Knowledge of this state is not transferred
|
||||
between experiments.
|
||||
:param hw_rev: Sampler's hardware revision string (default 'v2.2')
|
||||
:param core_device: Core device name
|
||||
"""
|
||||
kernel_invariants = {"bus_adc", "bus_pgia", "core", "cnv", "div", "corrected_fs"}
|
||||
kernel_invariants = {"bus_adc", "bus_pgia", "core", "cnv", "div"}
|
||||
|
||||
def __init__(self, dmgr, spi_adc_device, spi_pgia_device, cnv_device,
|
||||
div=8, gains=0x0000, hw_rev="v2.2", core_device="core"):
|
||||
div=8, gains=0x0000, core_device="core"):
|
||||
self.bus_adc = dmgr.get(spi_adc_device)
|
||||
self.bus_adc.update_xfer_duration_mu(div, 32)
|
||||
self.bus_pgia = dmgr.get(spi_pgia_device)
|
||||
|
|
@ -65,11 +62,6 @@ class Sampler:
|
|||
self.cnv = dmgr.get(cnv_device)
|
||||
self.div = div
|
||||
self.gains = gains
|
||||
self.corrected_fs = self.use_corrected_fs(hw_rev)
|
||||
|
||||
@staticmethod
|
||||
def use_corrected_fs(hw_rev):
|
||||
return hw_rev != "v2.1"
|
||||
|
||||
@kernel
|
||||
def init(self):
|
||||
|
|
@ -152,4 +144,4 @@ class Sampler:
|
|||
for i in range(n):
|
||||
channel = i + 8 - len(data)
|
||||
gain = (self.gains >> (channel*2)) & 0b11
|
||||
data[i] = adc_mu_to_volt(adc_data[i], gain, self.corrected_fs)
|
||||
data[i] = adc_mu_to_volt(adc_data[i], gain)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,372 @@
|
|||
"""
|
||||
Driver for the Smart Arbitrary Waveform Generator (SAWG) on RTIO.
|
||||
|
||||
The SAWG is an "improved DDS" built in gateware and interfacing to
|
||||
high-speed DACs.
|
||||
|
||||
Output event replacement is supported except on the configuration channel.
|
||||
"""
|
||||
|
||||
|
||||
from artiq.language.types import TInt32, TFloat
|
||||
from numpy import int32, int64
|
||||
from artiq.language.core import kernel, now_mu
|
||||
from artiq.coredevice.spline import Spline
|
||||
from artiq.coredevice.rtio import rtio_output
|
||||
|
||||
|
||||
# sawg.Config addresses
|
||||
_SAWG_DIV = 0
|
||||
_SAWG_CLR = 1
|
||||
_SAWG_IQ_EN = 2
|
||||
# _SAWF_PAD = 3 # reserved
|
||||
_SAWG_OUT_MIN = 4
|
||||
_SAWG_OUT_MAX = 5
|
||||
_SAWG_DUC_MIN = 6
|
||||
_SAWG_DUC_MAX = 7
|
||||
|
||||
|
||||
class Config:
|
||||
"""SAWG configuration.
|
||||
|
||||
Exposes the configurable quantities of a single SAWG channel.
|
||||
|
||||
Access to the configuration registers for a SAWG channel can not
|
||||
be concurrent. There must be at least :attr:`_rtio_interval` machine
|
||||
units of delay between accesses. Replacement is not supported and will be
|
||||
lead to an ``RTIOCollision`` as this is likely a programming error.
|
||||
All methods therefore advance the timeline by the duration of one
|
||||
configuration register transfer.
|
||||
|
||||
:param channel: RTIO channel number of the channel.
|
||||
:param core: Core device.
|
||||
"""
|
||||
kernel_invariants = {"channel", "core", "_out_scale", "_duc_scale",
|
||||
"_rtio_interval"}
|
||||
|
||||
def __init__(self, channel, core, cordic_gain=1.):
|
||||
self.channel = channel
|
||||
self.core = core
|
||||
# normalized DAC output
|
||||
self._out_scale = (1 << 15) - 1.
|
||||
# normalized DAC output including DUC cordic gain
|
||||
self._duc_scale = self._out_scale/cordic_gain
|
||||
# configuration channel access interval
|
||||
self._rtio_interval = int64(3*self.core.ref_multiplier)
|
||||
|
||||
@kernel
|
||||
def set_div(self, div: TInt32, n: TInt32=0):
|
||||
"""Set the spline evolution divider and current counter value.
|
||||
|
||||
The divider and the spline evolution are synchronized across all
|
||||
spline channels within a SAWG channel. The DDS/DUC phase accumulators
|
||||
always evolves at full speed.
|
||||
|
||||
.. note:: The spline evolution divider has not been tested extensively
|
||||
and is currently considered a technological preview only.
|
||||
|
||||
:param div: Spline evolution divider, such that
|
||||
``t_sawg_spline/t_rtio_coarse = div + 1``. Default: ``0``.
|
||||
:param n: Current value of the counter. Default: ``0``.
|
||||
"""
|
||||
rtio_output(now_mu(), self.channel, _SAWG_DIV, div | (n << 16))
|
||||
delay_mu(self._rtio_interval)
|
||||
|
||||
@kernel
|
||||
def set_clr(self, clr0: TInt32, clr1: TInt32, clr2: TInt32):
|
||||
"""Set the accumulator clear mode for the three phase accumulators.
|
||||
|
||||
When the ``clr`` bit for a given DDS/DUC phase accumulator is
|
||||
set, that phase accumulator will be cleared with every phase offset
|
||||
RTIO command and the output phase of the DDS/DUC will be
|
||||
exactly the phase RTIO value ("absolute phase update mode").
|
||||
|
||||
.. math::
|
||||
q^\prime(t) = p^\prime + (t - t^\prime) f^\prime
|
||||
|
||||
In turn, when the bit is cleared, the phase RTIO channels
|
||||
determine a phase offset to the current (carrier-) value of the
|
||||
DDS/DUC phase accumulator. This "relative phase update mode" is
|
||||
sometimes also called “continuous phase mode”.
|
||||
|
||||
.. math::
|
||||
q^\prime(t) = q(t^\prime) + (p^\prime - p) +
|
||||
(t - t^\prime) f^\prime
|
||||
|
||||
Where:
|
||||
|
||||
* :math:`q`, :math:`q^\prime`: old/new phase accumulator
|
||||
* :math:`p`, :math:`p^\prime`: old/new phase offset
|
||||
* :math:`f^\prime`: new frequency
|
||||
* :math:`t^\prime`: timestamp of setting new :math:`p`, :math:`f`
|
||||
* :math:`t`: running time
|
||||
|
||||
:param clr0: Auto-clear phase accumulator of the ``phase0``/
|
||||
``frequency0`` DUC. Default: ``True``
|
||||
:param clr1: Auto-clear phase accumulator of the ``phase1``/
|
||||
``frequency1`` DDS. Default: ``True``
|
||||
:param clr2: Auto-clear phase accumulator of the ``phase2``/
|
||||
``frequency2`` DDS. Default: ``True``
|
||||
"""
|
||||
rtio_output(now_mu(), self.channel, _SAWG_CLR, clr0 |
|
||||
(clr1 << 1) | (clr2 << 2))
|
||||
delay_mu(self._rtio_interval)
|
||||
|
||||
@kernel
|
||||
def set_iq_en(self, i_enable: TInt32, q_enable: TInt32):
|
||||
"""Enable I/Q data on this DAC channel.
|
||||
|
||||
Every pair of SAWG channels forms a buddy pair.
|
||||
The ``iq_en`` configuration controls which DDS data is emitted to the
|
||||
DACs.
|
||||
|
||||
Refer to the documentation of :class:`SAWG` for a mathematical
|
||||
description of ``i_enable`` and ``q_enable``.
|
||||
|
||||
.. note:: Quadrature data from the buddy channel is currently
|
||||
a technological preview only. The data is ignored in the SAWG
|
||||
gateware and not added to the DAC output.
|
||||
This is equivalent to the ``q_enable`` switch always being ``0``.
|
||||
|
||||
:param i_enable: Controls adding the in-phase
|
||||
DUC-DDS data of *this* SAWG channel to *this* DAC channel.
|
||||
Default: ``1``.
|
||||
:param q_enable: controls adding the quadrature
|
||||
DUC-DDS data of this SAWG's *buddy* channel to *this* DAC
|
||||
channel. Default: ``0``.
|
||||
"""
|
||||
rtio_output(now_mu(), self.channel, _SAWG_IQ_EN, i_enable |
|
||||
(q_enable << 1))
|
||||
delay_mu(self._rtio_interval)
|
||||
|
||||
@kernel
|
||||
def set_duc_max_mu(self, limit: TInt32):
|
||||
"""Set the digital up-converter (DUC) I and Q data summing junctions
|
||||
upper limit. In machine units.
|
||||
|
||||
The default limits are chosen to reach maximum and minimum DAC output
|
||||
amplitude.
|
||||
|
||||
For a description of the limiter functions in normalized units see:
|
||||
|
||||
.. seealso:: :meth:`set_duc_max`
|
||||
"""
|
||||
rtio_output(now_mu(), self.channel, _SAWG_DUC_MAX, limit)
|
||||
delay_mu(self._rtio_interval)
|
||||
|
||||
@kernel
|
||||
def set_duc_min_mu(self, limit: TInt32):
|
||||
""".. seealso:: :meth:`set_duc_max_mu`"""
|
||||
rtio_output(now_mu(), self.channel, _SAWG_DUC_MIN, limit)
|
||||
delay_mu(self._rtio_interval)
|
||||
|
||||
@kernel
|
||||
def set_out_max_mu(self, limit: TInt32):
|
||||
""".. seealso:: :meth:`set_duc_max_mu`"""
|
||||
rtio_output(now_mu(), self.channel, _SAWG_OUT_MAX, limit)
|
||||
delay_mu(self._rtio_interval)
|
||||
|
||||
@kernel
|
||||
def set_out_min_mu(self, limit: TInt32):
|
||||
""".. seealso:: :meth:`set_duc_max_mu`"""
|
||||
rtio_output(now_mu(), self.channel, _SAWG_OUT_MIN, limit)
|
||||
delay_mu(self._rtio_interval)
|
||||
|
||||
@kernel
|
||||
def set_duc_max(self, limit: TFloat):
|
||||
"""Set the digital up-converter (DUC) I and Q data summing junctions
|
||||
upper limit.
|
||||
|
||||
Each of the three summing junctions has a saturating adder with
|
||||
configurable upper and lower limits. The three summing junctions are:
|
||||
|
||||
* At the in-phase input to the ``phase0``/``frequency0`` fast DUC,
|
||||
after the anti-aliasing FIR filter.
|
||||
* At the quadrature input to the ``phase0``/``frequency0``
|
||||
fast DUC, after the anti-aliasing FIR filter. The in-phase and
|
||||
quadrature data paths both use the same limits.
|
||||
* Before the DAC, where the following three data streams
|
||||
are added together:
|
||||
|
||||
* the output of the ``offset`` spline,
|
||||
* (optionally, depending on ``i_enable``) the in-phase output
|
||||
of the ``phase0``/``frequency0`` fast DUC, and
|
||||
* (optionally, depending on ``q_enable``) the quadrature
|
||||
output of the ``phase0``/``frequency0`` fast DUC of the
|
||||
buddy channel.
|
||||
|
||||
Refer to the documentation of :class:`SAWG` for a mathematical
|
||||
description of the summing junctions.
|
||||
|
||||
:param limit: Limit value ``[-1, 1]``. The output of the limiter will
|
||||
never exceed this limit. The default limits are the full range
|
||||
``[-1, 1]``.
|
||||
|
||||
.. seealso::
|
||||
* :meth:`set_duc_max`: Upper limit of the in-phase and quadrature
|
||||
inputs to the DUC.
|
||||
* :meth:`set_duc_min`: Lower limit of the in-phase and quadrature
|
||||
inputs to the DUC.
|
||||
* :meth:`set_out_max`: Upper limit of the DAC output.
|
||||
* :meth:`set_out_min`: Lower limit of the DAC output.
|
||||
"""
|
||||
self.set_duc_max_mu(int32(round(limit*self._duc_scale)))
|
||||
|
||||
@kernel
|
||||
def set_duc_min(self, limit: TFloat):
|
||||
""".. seealso:: :meth:`set_duc_max`"""
|
||||
self.set_duc_min_mu(int32(round(limit*self._duc_scale)))
|
||||
|
||||
@kernel
|
||||
def set_out_max(self, limit: TFloat):
|
||||
""".. seealso:: :meth:`set_duc_max`"""
|
||||
self.set_out_max_mu(int32(round(limit*self._out_scale)))
|
||||
|
||||
@kernel
|
||||
def set_out_min(self, limit: TFloat):
|
||||
""".. seealso:: :meth:`set_duc_max`"""
|
||||
self.set_out_min_mu(int32(round(limit*self._out_scale)))
|
||||
|
||||
|
||||
class SAWG:
|
||||
"""Smart arbitrary waveform generator channel.
|
||||
The channel is parametrized as: ::
|
||||
|
||||
oscillators = exp(2j*pi*(frequency0*t + phase0))*(
|
||||
amplitude1*exp(2j*pi*(frequency1*t + phase1)) +
|
||||
amplitude2*exp(2j*pi*(frequency2*t + phase2)))
|
||||
|
||||
output = (offset +
|
||||
i_enable*Re(oscillators) +
|
||||
q_enable*Im(buddy_oscillators))
|
||||
|
||||
This parametrization can be viewed as two complex (quadrature) oscillators
|
||||
(``frequency1``/``phase1`` and ``frequency2``/``phase2``) that are
|
||||
executing and sampling at the coarse RTIO frequency. They can represent
|
||||
frequencies within the first Nyquist zone from ``-f_rtio_coarse/2`` to
|
||||
``f_rtio_coarse/2``.
|
||||
|
||||
.. note:: The coarse RTIO frequency ``f_rtio_coarse`` is the inverse of
|
||||
``ref_period*multiplier``. Both are arguments of the ``Core`` device,
|
||||
specified in the device database ``device_db.py``.
|
||||
|
||||
The sum of their outputs is then interpolated by a factor of
|
||||
:attr:`parallelism` (2, 4, 8 depending on the bitstream) using a
|
||||
finite-impulse-response (FIR) anti-aliasing filter (more accurately
|
||||
a half-band filter).
|
||||
|
||||
The filter is followed by a configurable saturating limiter.
|
||||
|
||||
After the limiter, the data is shifted in frequency using a complex
|
||||
digital up-converter (DUC, ``frequency0``/``phase0``) running at
|
||||
:attr:`parallelism` times the coarse RTIO frequency. The first Nyquist
|
||||
zone of the DUC extends from ``-f_rtio_coarse*parallelism/2`` to
|
||||
``f_rtio_coarse*parallelism/2``. Other Nyquist zones are usable depending
|
||||
on the interpolation/modulation options configured in the DAC.
|
||||
|
||||
The real/in-phase data after digital up-conversion can be offset using
|
||||
another spline interpolator ``offset``.
|
||||
|
||||
The ``i_enable``/``q_enable`` switches enable emission of quadrature
|
||||
signals for later analog quadrature mixing distinguishing upper and lower
|
||||
sidebands and thus doubling the bandwidth. They can also be used to emit
|
||||
four-tone signals.
|
||||
|
||||
.. note:: Quadrature data from the buddy channel is currently
|
||||
ignored in the SAWG gateware and not added to the DAC output.
|
||||
This is equivalent to the ``q_enable`` switch always being ``0``.
|
||||
|
||||
The configuration channel and the nine
|
||||
:class:`artiq.coredevice.spline.Spline` interpolators are accessible as
|
||||
attributes:
|
||||
|
||||
* :attr:`config`: :class:`Config`
|
||||
* :attr:`offset`, :attr:`amplitude1`, :attr:`amplitude2`: in units
|
||||
of full scale
|
||||
* :attr:`phase0`, :attr:`phase1`, :attr:`phase2`: in units of turns
|
||||
* :attr:`frequency0`, :attr:`frequency1`, :attr:`frequency2`: in units
|
||||
of Hz
|
||||
|
||||
.. note:: The latencies (pipeline depths) of the nine data channels (i.e.
|
||||
all except :attr:`config`) are matched. Equivalent channels (e.g.
|
||||
:attr:`phase1` and :attr:`phase2`) are exactly matched. Channels of
|
||||
different type or functionality (e.g. :attr:`offset` vs
|
||||
:attr:`amplitude1`, DDS vs DUC, :attr:`phase0` vs :attr:`phase1`) are
|
||||
only matched to within one coarse RTIO cycle.
|
||||
|
||||
:param channel_base: RTIO channel number of the first channel (amplitude).
|
||||
The configuration channel and frequency/phase/amplitude channels are
|
||||
then assumed to be successive channels.
|
||||
:param parallelism: Number of output samples per coarse RTIO clock cycle.
|
||||
:param core_device: Name of the core device that this SAWG is on.
|
||||
"""
|
||||
kernel_invariants = {"channel_base", "core", "parallelism",
|
||||
"amplitude1", "frequency1", "phase1",
|
||||
"amplitude2", "frequency2", "phase2",
|
||||
"frequency0", "phase0", "offset"}
|
||||
|
||||
def __init__(self, dmgr, channel_base, parallelism, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.channel_base = channel_base
|
||||
self.parallelism = parallelism
|
||||
width = 16
|
||||
time_width = 16
|
||||
cordic_gain = 1.646760258057163 # Cordic(width=16, guard=None).gain
|
||||
head_room = 1.001
|
||||
self.config = Config(channel_base, self.core, cordic_gain)
|
||||
self.offset = Spline(width, time_width, channel_base + 1,
|
||||
self.core, 2.*head_room)
|
||||
self.amplitude1 = Spline(width, time_width, channel_base + 2,
|
||||
self.core, 2*head_room*cordic_gain**2)
|
||||
self.frequency1 = Spline(3*width, time_width, channel_base + 3,
|
||||
self.core, 1/self.core.coarse_ref_period)
|
||||
self.phase1 = Spline(width, time_width, channel_base + 4,
|
||||
self.core, 1.)
|
||||
self.amplitude2 = Spline(width, time_width, channel_base + 5,
|
||||
self.core, 2*head_room*cordic_gain**2)
|
||||
self.frequency2 = Spline(3*width, time_width, channel_base + 6,
|
||||
self.core, 1/self.core.coarse_ref_period)
|
||||
self.phase2 = Spline(width, time_width, channel_base + 7,
|
||||
self.core, 1.)
|
||||
self.frequency0 = Spline(2*width, time_width, channel_base + 8,
|
||||
self.core,
|
||||
parallelism/self.core.coarse_ref_period)
|
||||
self.phase0 = Spline(width, time_width, channel_base + 9,
|
||||
self.core, 1.)
|
||||
|
||||
@kernel
|
||||
def reset(self):
|
||||
"""Re-establish initial conditions.
|
||||
|
||||
This clears all spline interpolators, accumulators and configuration
|
||||
settings.
|
||||
|
||||
This method advances the timeline by the time required to perform all
|
||||
7 writes to the configuration channel, plus 9 coarse RTIO cycles.
|
||||
"""
|
||||
self.config.set_div(0, 0)
|
||||
self.config.set_clr(1, 1, 1)
|
||||
self.config.set_iq_en(1, 0)
|
||||
self.config.set_duc_min(-1.)
|
||||
self.config.set_duc_max(1.)
|
||||
self.config.set_out_min(-1.)
|
||||
self.config.set_out_max(1.)
|
||||
self.frequency0.set_mu(0)
|
||||
coarse_cycle = int64(self.core.ref_multiplier)
|
||||
delay_mu(coarse_cycle)
|
||||
self.frequency1.set_mu(0)
|
||||
delay_mu(coarse_cycle)
|
||||
self.frequency2.set_mu(0)
|
||||
delay_mu(coarse_cycle)
|
||||
self.phase0.set_mu(0)
|
||||
delay_mu(coarse_cycle)
|
||||
self.phase1.set_mu(0)
|
||||
delay_mu(coarse_cycle)
|
||||
self.phase2.set_mu(0)
|
||||
delay_mu(coarse_cycle)
|
||||
self.amplitude1.set_mu(0)
|
||||
delay_mu(coarse_cycle)
|
||||
self.amplitude2.set_mu(0)
|
||||
delay_mu(coarse_cycle)
|
||||
self.offset.set_mu(0)
|
||||
delay_mu(coarse_cycle)
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
from artiq.language.core import kernel, delay
|
||||
from artiq.language.units import us
|
||||
|
||||
|
||||
class ShiftReg:
|
||||
"""Driver for shift registers/latch combos connected to TTLs"""
|
||||
kernel_invariants = {"dt", "n"}
|
||||
|
||||
def __init__(self, dmgr, clk, ser, latch, n=32, dt=10*us):
|
||||
self.core = dmgr.get("core")
|
||||
self.clk = dmgr.get(clk)
|
||||
self.ser = dmgr.get(ser)
|
||||
self.latch = dmgr.get(latch)
|
||||
self.n = n
|
||||
self.dt = dt
|
||||
|
||||
@kernel
|
||||
def set(self, data):
|
||||
"""Sets the values of the latch outputs. This does not
|
||||
advance the timeline and the waveform is generated before
|
||||
`now`."""
|
||||
delay(-2*(self.n + 1)*self.dt)
|
||||
for i in range(self.n):
|
||||
if (data >> (self.n-i-1)) & 1 == 0:
|
||||
self.ser.off()
|
||||
else:
|
||||
self.ser.on()
|
||||
self.clk.off()
|
||||
delay(self.dt)
|
||||
self.clk.on()
|
||||
delay(self.dt)
|
||||
self.clk.off()
|
||||
self.latch.on()
|
||||
delay(self.dt)
|
||||
self.latch.off()
|
||||
delay(self.dt)
|
||||
|
|
@ -1,623 +0,0 @@
|
|||
from artiq.language.core import *
|
||||
from artiq.language.types import *
|
||||
from artiq.coredevice.rtio import rtio_output, rtio_input_data
|
||||
from artiq.coredevice import spi2 as spi
|
||||
from artiq.language.units import us
|
||||
|
||||
|
||||
@portable
|
||||
def shuttler_volt_to_mu(volt):
|
||||
"""Return the equivalent DAC code. Valid input range is from -10 to
|
||||
10 - LSB.
|
||||
"""
|
||||
return round((1 << 16) * (volt / 20.0)) & 0xffff
|
||||
|
||||
|
||||
class Config:
|
||||
"""Shuttler configuration registers interface.
|
||||
|
||||
The configuration registers control waveform phase auto-clear, and pre-DAC
|
||||
gain & offset values for calibration with ADC on the Shuttler AFE card.
|
||||
|
||||
To find the calibrated DAC code, the Shuttler Core first multiplies the
|
||||
output data with pre-DAC gain, then adds the offset.
|
||||
|
||||
.. note::
|
||||
The DAC code is capped at 0x7fff and 0x8000.
|
||||
|
||||
:param channel: RTIO channel number of this interface.
|
||||
:param core_device: Core device name.
|
||||
"""
|
||||
kernel_invariants = {
|
||||
"core", "channel", "target_base", "target_read",
|
||||
"target_gain", "target_offset", "target_clr"
|
||||
}
|
||||
|
||||
def __init__(self, dmgr, channel, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.channel = channel
|
||||
self.target_base = channel << 8
|
||||
self.target_read = 1 << 6
|
||||
self.target_gain = 0 * (1 << 4)
|
||||
self.target_offset = 1 * (1 << 4)
|
||||
self.target_clr = 1 * (1 << 5)
|
||||
|
||||
@kernel
|
||||
def set_clr(self, clr):
|
||||
"""Set/Unset waveform phase clear bits.
|
||||
|
||||
Each bit corresponds to a Shuttler waveform generator core. Setting a
|
||||
clear bit forces the Shuttler Core to clear the phase accumulator on
|
||||
waveform trigger (See :class:`Trigger` for the trigger method).
|
||||
Otherwise, the phase accumulator increments from its original value.
|
||||
|
||||
:param clr: Waveform phase clear bits. The MSB corresponds to Channel
|
||||
15, LSB corresponds to Channel 0.
|
||||
"""
|
||||
rtio_output(self.target_base | self.target_clr, clr)
|
||||
|
||||
@kernel
|
||||
def set_gain(self, channel, gain):
|
||||
"""Set the 16-bits pre-DAC gain register of a Shuttler Core channel.
|
||||
|
||||
The `gain` parameter represents the decimal portion of the gain
|
||||
factor. The MSB represents 0.5 and the sign bit. Hence, the valid
|
||||
total gain value (1 +/- 0.gain) ranges from 0.5 to 1.5 - LSB.
|
||||
|
||||
:param channel: Shuttler Core channel to be configured.
|
||||
:param gain: Shuttler Core channel gain.
|
||||
"""
|
||||
rtio_output(self.target_base | self.target_gain | channel, gain)
|
||||
|
||||
@kernel
|
||||
def get_gain(self, channel):
|
||||
"""Return the pre-DAC gain value of a Shuttler Core channel.
|
||||
|
||||
:param channel: The Shuttler Core channel.
|
||||
:return: Pre-DAC gain value. See :meth:`set_gain`.
|
||||
"""
|
||||
rtio_output(self.target_base | self.target_gain |
|
||||
self.target_read | channel, 0)
|
||||
return rtio_input_data(self.channel)
|
||||
|
||||
@kernel
|
||||
def set_offset(self, channel, offset):
|
||||
"""Set the 16-bits pre-DAC offset register of a Shuttler Core channel.
|
||||
|
||||
.. seealso::
|
||||
:meth:`shuttler_volt_to_mu`
|
||||
|
||||
:param channel: Shuttler Core channel to be configured.
|
||||
:param offset: Shuttler Core channel offset.
|
||||
"""
|
||||
rtio_output(self.target_base | self.target_offset | channel, offset)
|
||||
|
||||
@kernel
|
||||
def get_offset(self, channel):
|
||||
"""Return the pre-DAC offset value of a Shuttler Core channel.
|
||||
|
||||
:param channel: The Shuttler Core channel.
|
||||
:return: Pre-DAC offset value. See :meth:`set_offset`.
|
||||
"""
|
||||
rtio_output(self.target_base | self.target_offset |
|
||||
self.target_read | channel, 0)
|
||||
return rtio_input_data(self.channel)
|
||||
|
||||
|
||||
class DCBias:
|
||||
"""Shuttler Core cubic DC-bias spline.
|
||||
|
||||
A Shuttler channel can generate a waveform `w(t)` that is the sum of a
|
||||
cubic spline `a(t)` and a sinusoid modulated in amplitude by a cubic
|
||||
spline `b(t)` and in phase/frequency by a quadratic spline `c(t)`, where
|
||||
|
||||
.. math::
|
||||
w(t) = a(t) + b(t) * cos(c(t))
|
||||
|
||||
And `t` corresponds to time in seconds.
|
||||
This class controls the cubic spline `a(t)`, in which
|
||||
|
||||
.. math::
|
||||
a(t) = p_0 + p_1t + \\frac{p_2t^2}{2} + \\frac{p_3t^3}{6}
|
||||
|
||||
And `a(t)` is in Volt.
|
||||
|
||||
:param channel: RTIO channel number of this DC-bias spline interface.
|
||||
:param core_device: Core device name.
|
||||
"""
|
||||
kernel_invariants = {"core", "channel", "target_o"}
|
||||
|
||||
def __init__(self, dmgr, channel, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.channel = channel
|
||||
self.target_o = channel << 8
|
||||
|
||||
@kernel
|
||||
def set_waveform(self, a0: TInt32, a1: TInt32, a2: TInt64, a3: TInt64):
|
||||
"""Set the DC-bias spline waveform.
|
||||
|
||||
Given `a(t)` as defined in :class:`DCBias`, the coefficients should be
|
||||
configured by the following formulae.
|
||||
|
||||
.. math::
|
||||
T &= 8*10^{-9}
|
||||
|
||||
a_0 &= p_0
|
||||
|
||||
a_1 &= p_1T + \\frac{p_2T^2}{2} + \\frac{p_3T^3}{6}
|
||||
|
||||
a_2 &= p_2T^2 + p_3T^3
|
||||
|
||||
a_3 &= p_3T^3
|
||||
|
||||
:math:`a_0`, :math:`a_1`, :math:`a_2` and :math:`a_3` are 16, 32, 48
|
||||
and 48 bits in width respectively. See :meth:`shuttler_volt_to_mu` for
|
||||
machine unit conversion.
|
||||
|
||||
Note: The waveform is not updated to the Shuttler Core until
|
||||
triggered. See :class:`Trigger` for the update triggering mechanism.
|
||||
|
||||
:param a0: The :math:`a_0` coefficient in machine unit.
|
||||
:param a1: The :math:`a_1` coefficient in machine unit.
|
||||
:param a2: The :math:`a_2` coefficient in machine unit.
|
||||
:param a3: The :math:`a_3` coefficient in machine unit.
|
||||
"""
|
||||
coef_words = [
|
||||
a0,
|
||||
a1,
|
||||
a1 >> 16,
|
||||
a2 & 0xFFFF,
|
||||
(a2 >> 16) & 0xFFFF,
|
||||
(a2 >> 32) & 0xFFFF,
|
||||
a3 & 0xFFFF,
|
||||
(a3 >> 16) & 0xFFFF,
|
||||
(a3 >> 32) & 0xFFFF,
|
||||
]
|
||||
|
||||
for i in range(len(coef_words)):
|
||||
rtio_output(self.target_o | i, coef_words[i])
|
||||
delay_mu(int64(self.core.ref_multiplier))
|
||||
|
||||
|
||||
class DDS:
|
||||
"""Shuttler Core DDS spline.
|
||||
|
||||
A Shuttler channel can generate a waveform `w(t)` that is the sum of a
|
||||
cubic spline `a(t)` and a sinusoid modulated in amplitude by a cubic
|
||||
spline `b(t)` and in phase/frequency by a quadratic spline `c(t)`, where
|
||||
|
||||
.. math::
|
||||
w(t) = a(t) + b(t) * cos(c(t))
|
||||
|
||||
And `t` corresponds to time in seconds.
|
||||
This class controls the cubic spline `b(t)` and quadratic spline `c(t)`,
|
||||
in which
|
||||
|
||||
.. math::
|
||||
b(t) &= g * (q_0 + q_1t + \\frac{q_2t^2}{2} + \\frac{q_3t^3}{6})
|
||||
|
||||
c(t) &= r_0 + r_1t + \\frac{r_2t^2}{2}
|
||||
|
||||
And `b(t)` is in Volt, `c(t)` is in number of turns. Note that `b(t)`
|
||||
contributes to a constant gain of :math:`g=1.64676`.
|
||||
|
||||
:param channel: RTIO channel number of this DC-bias spline interface.
|
||||
:param core_device: Core device name.
|
||||
"""
|
||||
kernel_invariants = {"core", "channel", "target_o"}
|
||||
|
||||
def __init__(self, dmgr, channel, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.channel = channel
|
||||
self.target_o = channel << 8
|
||||
|
||||
@kernel
|
||||
def set_waveform(self, b0: TInt32, b1: TInt32, b2: TInt64, b3: TInt64,
|
||||
c0: TInt32, c1: TInt32, c2: TInt32):
|
||||
"""Set the DDS spline waveform.
|
||||
|
||||
Given `b(t)` and `c(t)` as defined in :class:`DDS`, the coefficients
|
||||
should be configured by the following formulae.
|
||||
|
||||
.. math::
|
||||
T &= 8*10^{-9}
|
||||
|
||||
b_0 &= q_0
|
||||
|
||||
b_1 &= q_1T + \\frac{q_2T^2}{2} + \\frac{q_3T^3}{6}
|
||||
|
||||
b_2 &= q_2T^2 + q_3T^3
|
||||
|
||||
b_3 &= q_3T^3
|
||||
|
||||
c_0 &= r_0
|
||||
|
||||
c_1 &= r_1T + \\frac{r_2T^2}{2}
|
||||
|
||||
c_2 &= r_2T^2
|
||||
|
||||
:math:`b_0`, :math:`b_1`, :math:`b_2` and :math:`b_3` are 16, 32, 48
|
||||
and 48 bits in width respectively. See :meth:`shuttler_volt_to_mu` for
|
||||
machine unit conversion. :math:`c_0`, :math:`c_1` and :math:`c_2` are
|
||||
16, 32 and 32 bits in width respectively.
|
||||
|
||||
Note: The waveform is not updated to the Shuttler Core until
|
||||
triggered. See :class:`Trigger` for the update triggering mechanism.
|
||||
|
||||
:param b0: The :math:`b_0` coefficient in machine unit.
|
||||
:param b1: The :math:`b_1` coefficient in machine unit.
|
||||
:param b2: The :math:`b_2` coefficient in machine unit.
|
||||
:param b3: The :math:`b_3` coefficient in machine unit.
|
||||
:param c0: The :math:`c_0` coefficient in machine unit.
|
||||
:param c1: The :math:`c_1` coefficient in machine unit.
|
||||
:param c2: The :math:`c_2` coefficient in machine unit.
|
||||
"""
|
||||
coef_words = [
|
||||
b0,
|
||||
b1,
|
||||
b1 >> 16,
|
||||
b2 & 0xFFFF,
|
||||
(b2 >> 16) & 0xFFFF,
|
||||
(b2 >> 32) & 0xFFFF,
|
||||
b3 & 0xFFFF,
|
||||
(b3 >> 16) & 0xFFFF,
|
||||
(b3 >> 32) & 0xFFFF,
|
||||
c0,
|
||||
c1,
|
||||
c1 >> 16,
|
||||
c2,
|
||||
c2 >> 16,
|
||||
]
|
||||
|
||||
for i in range(len(coef_words)):
|
||||
rtio_output(self.target_o | i, coef_words[i])
|
||||
delay_mu(int64(self.core.ref_multiplier))
|
||||
|
||||
|
||||
class Trigger:
|
||||
"""Shuttler Core spline coefficients update trigger.
|
||||
|
||||
:param channel: RTIO channel number of the trigger interface.
|
||||
:param core_device: Core device name.
|
||||
"""
|
||||
kernel_invariants = {"core", "channel", "target_o"}
|
||||
|
||||
def __init__(self, dmgr, channel, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.channel = channel
|
||||
self.target_o = channel << 8
|
||||
|
||||
@kernel
|
||||
def trigger(self, trig_out):
|
||||
"""Triggers coefficient update of (a) Shuttler Core channel(s).
|
||||
|
||||
Each bit corresponds to a Shuttler waveform generator core. Setting
|
||||
`trig_out` bits commits the pending coefficient update (from
|
||||
`set_waveform` in :class:`DCBias` and :class:`DDS`) to the Shuttler Core
|
||||
synchronously.
|
||||
|
||||
:param trig_out: Coefficient update trigger bits. The MSB corresponds
|
||||
to Channel 15, LSB corresponds to Channel 0.
|
||||
"""
|
||||
rtio_output(self.target_o, trig_out)
|
||||
|
||||
|
||||
RELAY_SPI_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
|
||||
0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
|
||||
0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
|
||||
0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
|
||||
|
||||
ADC_SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_END |
|
||||
0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
|
||||
1*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
|
||||
0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
|
||||
|
||||
# SPI clock write and read dividers
|
||||
# CS should assert at least 9.5 ns after clk pulse
|
||||
SPIT_RELAY_WR = 4
|
||||
# 25 ns high/low pulse hold (limiting for write)
|
||||
SPIT_ADC_WR = 4
|
||||
SPIT_ADC_RD = 16
|
||||
|
||||
# SPI CS line
|
||||
CS_RELAY = 1 << 0
|
||||
CS_LED = 1 << 1
|
||||
CS_ADC = 1 << 0
|
||||
|
||||
# Referenced AD4115 registers
|
||||
_AD4115_REG_STATUS = 0x00
|
||||
_AD4115_REG_ADCMODE = 0x01
|
||||
_AD4115_REG_DATA = 0x04
|
||||
_AD4115_REG_ID = 0x07
|
||||
_AD4115_REG_CH0 = 0x10
|
||||
_AD4115_REG_SETUPCON0 = 0x20
|
||||
|
||||
|
||||
class Relay:
|
||||
"""Shuttler AFE relay switches.
|
||||
|
||||
It controls the AFE relay switches and the LEDs. Switch on the relay to
|
||||
enable AFE output; And off to disable the output. The LEDs indicates the
|
||||
relay status.
|
||||
|
||||
.. note::
|
||||
The relay does not disable ADC measurements. Voltage of any channels
|
||||
can still be read by the ADC even after switching off the relays.
|
||||
|
||||
:param spi_device: SPI bus device name.
|
||||
:param core_device: Core device name.
|
||||
"""
|
||||
kernel_invariant = {"core", "bus"}
|
||||
|
||||
def __init__(self, dmgr, spi_device, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.bus = dmgr.get(spi_device)
|
||||
|
||||
@kernel
|
||||
def init(self):
|
||||
"""Initialize SPI device.
|
||||
|
||||
Configures the SPI bus to 16-bits, write-only, simultaneous relay
|
||||
switches and LED control.
|
||||
"""
|
||||
self.bus.set_config_mu(
|
||||
RELAY_SPI_CONFIG, 16, SPIT_RELAY_WR, CS_RELAY | CS_LED)
|
||||
|
||||
@kernel
|
||||
def enable(self, en: TInt32):
|
||||
"""Enable/Disable relay switches of corresponding channels.
|
||||
|
||||
Each bit corresponds to the relay switch of a channel. Asserting a bit
|
||||
turns on the corresponding relay switch; Deasserting the same bit
|
||||
turns off the switch instead.
|
||||
|
||||
:param en: Switch enable bits. The MSB corresponds to Channel 15, LSB
|
||||
corresponds to Channel 0.
|
||||
"""
|
||||
self.bus.write(en << 16)
|
||||
|
||||
|
||||
class ADC:
|
||||
"""Shuttler AFE ADC (AD4115) driver.
|
||||
|
||||
:param spi_device: SPI bus device name.
|
||||
:param core_device: Core device name.
|
||||
"""
|
||||
kernel_invariant = {"core", "bus"}
|
||||
|
||||
def __init__(self, dmgr, spi_device, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.bus = dmgr.get(spi_device)
|
||||
|
||||
@kernel
|
||||
def read_id(self) -> TInt32:
|
||||
"""Read the product ID of the ADC.
|
||||
|
||||
The expected return value is 0x38DX, the 4 LSbs are don't cares.
|
||||
|
||||
:return: The read-back product ID.
|
||||
"""
|
||||
return self.read16(_AD4115_REG_ID)
|
||||
|
||||
@kernel
|
||||
def reset(self):
|
||||
"""AD4115 reset procedure.
|
||||
|
||||
This performs a write operation of 96 serial clock cycles with DIN
|
||||
held at high. It resets the entire device, including the register
|
||||
contents.
|
||||
|
||||
.. note::
|
||||
The datasheet only requires 64 cycles, but reasserting `CS_n` right
|
||||
after the transfer appears to interrupt the start-up sequence.
|
||||
"""
|
||||
self.bus.set_config_mu(ADC_SPI_CONFIG, 32, SPIT_ADC_WR, CS_ADC)
|
||||
self.bus.write(0xffffffff)
|
||||
self.bus.write(0xffffffff)
|
||||
self.bus.set_config_mu(
|
||||
ADC_SPI_CONFIG | spi.SPI_END, 32, SPIT_ADC_WR, CS_ADC)
|
||||
self.bus.write(0xffffffff)
|
||||
|
||||
@kernel
|
||||
def read8(self, addr: TInt32) -> TInt32:
|
||||
"""Read from 8 bit register.
|
||||
|
||||
:param addr: Register address.
|
||||
:return: Read-back register content.
|
||||
"""
|
||||
self.bus.set_config_mu(
|
||||
ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
|
||||
16, SPIT_ADC_RD, CS_ADC)
|
||||
self.bus.write((addr | 0x40) << 24)
|
||||
return self.bus.read() & 0xff
|
||||
|
||||
@kernel
|
||||
def read16(self, addr: TInt32) -> TInt32:
|
||||
"""Read from 16 bit register.
|
||||
|
||||
:param addr: Register address.
|
||||
:return: Read-back register content.
|
||||
"""
|
||||
self.bus.set_config_mu(
|
||||
ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
|
||||
24, SPIT_ADC_RD, CS_ADC)
|
||||
self.bus.write((addr | 0x40) << 24)
|
||||
return self.bus.read() & 0xffff
|
||||
|
||||
@kernel
|
||||
def read24(self, addr: TInt32) -> TInt32:
|
||||
"""Read from 24 bit register.
|
||||
|
||||
:param addr: Register address.
|
||||
:return: Read-back register content.
|
||||
"""
|
||||
self.bus.set_config_mu(
|
||||
ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
|
||||
32, SPIT_ADC_RD, CS_ADC)
|
||||
self.bus.write((addr | 0x40) << 24)
|
||||
return self.bus.read() & 0xffffff
|
||||
|
||||
@kernel
|
||||
def write8(self, addr: TInt32, data: TInt32):
|
||||
"""Write to 8 bit register.
|
||||
|
||||
:param addr: Register address.
|
||||
:param data: Data to be written.
|
||||
"""
|
||||
self.bus.set_config_mu(
|
||||
ADC_SPI_CONFIG | spi.SPI_END, 16, SPIT_ADC_WR, CS_ADC)
|
||||
self.bus.write(addr << 24 | (data & 0xff) << 16)
|
||||
|
||||
@kernel
|
||||
def write16(self, addr: TInt32, data: TInt32):
|
||||
"""Write to 16 bit register.
|
||||
|
||||
:param addr: Register address.
|
||||
:param data: Data to be written.
|
||||
"""
|
||||
self.bus.set_config_mu(
|
||||
ADC_SPI_CONFIG | spi.SPI_END, 24, SPIT_ADC_WR, CS_ADC)
|
||||
self.bus.write(addr << 24 | (data & 0xffff) << 8)
|
||||
|
||||
@kernel
|
||||
def write24(self, addr: TInt32, data: TInt32):
|
||||
"""Write to 24 bit register.
|
||||
|
||||
:param addr: Register address.
|
||||
:param data: Data to be written.
|
||||
"""
|
||||
self.bus.set_config_mu(
|
||||
ADC_SPI_CONFIG | spi.SPI_END, 32, SPIT_ADC_WR, CS_ADC)
|
||||
self.bus.write(addr << 24 | (data & 0xffffff))
|
||||
|
||||
@kernel
|
||||
def read_ch(self, channel: TInt32) -> TFloat:
|
||||
"""Sample a Shuttler channel on the AFE.
|
||||
|
||||
It performs a single conversion using profile 0 and setup 0, on the
|
||||
selected channel. The sample is then recovered and converted to volt.
|
||||
|
||||
:param channel: Shuttler channel to be sampled.
|
||||
:return: Voltage sample in volt.
|
||||
"""
|
||||
# Always configure Profile 0 for single conversion
|
||||
self.write16(_AD4115_REG_CH0, 0x8000 | ((channel * 2 + 1) << 4))
|
||||
self.write16(_AD4115_REG_SETUPCON0, 0x1300)
|
||||
self.single_conversion()
|
||||
|
||||
delay(100*us)
|
||||
adc_code = self.read24(_AD4115_REG_DATA)
|
||||
return ((adc_code / (1 << 23)) - 1) * 2.5 / 0.1
|
||||
|
||||
@kernel
|
||||
def single_conversion(self):
|
||||
"""Place the ADC in single conversion mode.
|
||||
|
||||
The ADC returns to standby mode after the conversion is complete.
|
||||
"""
|
||||
self.write16(_AD4115_REG_ADCMODE, 0x8010)
|
||||
|
||||
@kernel
|
||||
def standby(self):
|
||||
"""Place the ADC in standby mode and disables power down the clock.
|
||||
|
||||
The ADC can be returned to single conversion mode by calling
|
||||
:meth:`single_conversion`.
|
||||
"""
|
||||
# Selecting internal XO (0b00) also disables clock during standby
|
||||
self.write16(_AD4115_REG_ADCMODE, 0x8020)
|
||||
|
||||
@kernel
|
||||
def power_down(self):
|
||||
"""Place the ADC in power-down mode.
|
||||
|
||||
The ADC must be reset before returning to other modes.
|
||||
|
||||
.. note::
|
||||
The AD4115 datasheet suggests placing the ADC in standby mode
|
||||
before power-down. This is to prevent accidental entry into the
|
||||
power-down mode.
|
||||
|
||||
.. seealso::
|
||||
:meth:`standby`
|
||||
|
||||
:meth:`power_up`
|
||||
|
||||
"""
|
||||
self.write16(_AD4115_REG_ADCMODE, 0x8030)
|
||||
|
||||
@kernel
|
||||
def power_up(self):
|
||||
"""Exit the ADC power-down mode.
|
||||
|
||||
The ADC should be in power-down mode before calling this method.
|
||||
|
||||
.. seealso::
|
||||
:meth:`power_down`
|
||||
"""
|
||||
self.reset()
|
||||
# Although the datasheet claims 500 us reset wait time, only waiting
|
||||
# for ~500 us can result in DOUT pin stuck in high
|
||||
delay(2500*us)
|
||||
|
||||
@kernel
|
||||
def calibrate(self, volts, trigger, config, samples=[-5.0, 0.0, 5.0]):
|
||||
"""Calibrate the Shuttler waveform generator using the ADC on the AFE.
|
||||
|
||||
It finds the average slope rate and average offset by samples, and
|
||||
compensate by writing the pre-DAC gain and offset registers in the
|
||||
configuration registers.
|
||||
|
||||
.. note::
|
||||
If the pre-calibration slope rate < 1, the calibration procedure
|
||||
will introduce a pre-DAC gain compensation. However, this may
|
||||
saturate the pre-DAC voltage code. (See :class:`Config` notes).
|
||||
Shuttler cannot cover the entire +/- 10 V range in this case.
|
||||
|
||||
.. seealso::
|
||||
:meth:`Config.set_gain`
|
||||
|
||||
:meth:`Config.set_offset`
|
||||
|
||||
:param volts: A list of all 16 cubic DC-bias spline.
|
||||
(See :class:`DCBias`)
|
||||
:param trigger: The Shuttler spline coefficient update trigger.
|
||||
:param config: The Shuttler Core configuration registers.
|
||||
:param samples: A list of sample voltages for calibration. There must
|
||||
be at least 2 samples to perform slope rate calculation.
|
||||
"""
|
||||
assert len(volts) == 16
|
||||
assert len(samples) > 1
|
||||
|
||||
measurements = [0.0] * len(samples)
|
||||
|
||||
for ch in range(16):
|
||||
# Find the average slope rate and offset
|
||||
for i in range(len(samples)):
|
||||
self.core.break_realtime()
|
||||
volts[ch].set_waveform(
|
||||
shuttler_volt_to_mu(samples[i]), 0, 0, 0)
|
||||
trigger.trigger(1 << ch)
|
||||
measurements[i] = self.read_ch(ch)
|
||||
|
||||
# Find the average output slope
|
||||
slope_sum = 0.0
|
||||
for i in range(len(samples) - 1):
|
||||
slope_sum += (measurements[i+1] - measurements[i])/(samples[i+1] - samples[i])
|
||||
slope_avg = slope_sum / (len(samples) - 1)
|
||||
|
||||
gain_code = int32(1 / slope_avg * (2 ** 16)) & 0xffff
|
||||
|
||||
# Scale the measurements by 1/slope, find average offset
|
||||
offset_sum = 0.0
|
||||
for i in range(len(samples)):
|
||||
offset_sum += (measurements[i] / slope_avg) - samples[i]
|
||||
offset_avg = offset_sum / len(samples)
|
||||
|
||||
offset_code = shuttler_volt_to_mu(-offset_avg)
|
||||
|
||||
self.core.break_realtime()
|
||||
config.set_gain(ch, gain_code)
|
||||
|
||||
delay_mu(int64(self.core.ref_multiplier))
|
||||
config.set_offset(ch, offset_code)
|
||||
|
|
@ -7,7 +7,7 @@ Output event replacement is not supported and issuing commands at the same
|
|||
time is an error.
|
||||
"""
|
||||
|
||||
from artiq.language.core import syscall, kernel, portable, delay_mu
|
||||
from artiq.language.core import syscall, kernel, portable, now_mu, delay_mu
|
||||
from artiq.language.types import TInt32, TNone
|
||||
from artiq.coredevice.rtio import rtio_output, rtio_input_data
|
||||
|
||||
|
|
@ -72,10 +72,6 @@ class SPIMaster:
|
|||
self.channel = channel
|
||||
self.update_xfer_duration_mu(div, length)
|
||||
|
||||
@staticmethod
|
||||
def get_rtio_channels(channel, **kwargs):
|
||||
return [(channel, None)]
|
||||
|
||||
@portable
|
||||
def frequency_to_div(self, f):
|
||||
"""Convert a SPI clock frequency to the closest SPI clock divider."""
|
||||
|
|
@ -170,7 +166,7 @@ class SPIMaster:
|
|||
raise ValueError("Invalid SPI transfer length")
|
||||
if div > 257 or div < 2:
|
||||
raise ValueError("Invalid SPI clock divider")
|
||||
rtio_output((self.channel << 8) | SPI_CONFIG_ADDR, flags |
|
||||
rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
|
||||
((length - 1) << 8) | ((div - 2) << 16) | (cs << 24))
|
||||
self.update_xfer_duration_mu(div, length)
|
||||
delay_mu(self.ref_period_mu)
|
||||
|
|
@ -188,13 +184,7 @@ class SPIMaster:
|
|||
experiments and are known.
|
||||
|
||||
This method is portable and can also be called from e.g.
|
||||
:meth:`__init__`.
|
||||
|
||||
.. warning:: If this method is called while recording a DMA
|
||||
sequence, the playback of the sequence will not update the
|
||||
driver state.
|
||||
When required, update the driver state manually (by calling
|
||||
this method) after playing back a DMA sequence.
|
||||
``__init__``.
|
||||
|
||||
:param div: SPI clock divider (see: :meth:`set_config_mu`)
|
||||
:param length: SPI transfer length (see: :meth:`set_config_mu`)
|
||||
|
|
@ -226,7 +216,7 @@ class SPIMaster:
|
|||
|
||||
:param data: SPI output data to be written.
|
||||
"""
|
||||
rtio_output((self.channel << 8) | SPI_DATA_ADDR, data)
|
||||
rtio_output(now_mu(), self.channel, SPI_DATA_ADDR, data)
|
||||
delay_mu(self.xfer_duration_mu)
|
||||
|
||||
@kernel
|
||||
|
|
@ -277,8 +267,9 @@ class NRTSPIMaster:
|
|||
def set_config_mu(self, flags=0, length=8, div=6, cs=1):
|
||||
"""Set the ``config`` register.
|
||||
|
||||
In many cases, the SPI configuration is already set by the firmware
|
||||
and you do not need to call this method.
|
||||
Note that the non-realtime SPI cores are usually clocked by the system
|
||||
clock and not the RTIO clock. In many cases, the SPI configuration is
|
||||
already set by the firmware and you do not need to call this method.
|
||||
"""
|
||||
spi_set_config(self.busno, flags, length, div, cs)
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,228 @@
|
|||
from numpy import int32, int64
|
||||
from artiq.language.core import kernel, now_mu, portable, delay
|
||||
from artiq.coredevice.rtio import rtio_output, rtio_output_wide
|
||||
from artiq.language.types import TInt32, TInt64, TFloat
|
||||
|
||||
|
||||
class Spline:
|
||||
r"""Spline interpolating RTIO channel.
|
||||
|
||||
One knot of a polynomial basis spline (B-spline) :math:`u(t)`
|
||||
is defined by the coefficients :math:`u_n` up to order :math:`n = k`.
|
||||
If the coefficients are evaluated starting at time :math:`t_0`,
|
||||
the output :math:`u(t)` for :math:`t > t_0, t_0` is:
|
||||
|
||||
.. math::
|
||||
u(t) &= \sum_{n=0}^k \frac{u_n}{n!} (t - t_0)^n \\
|
||||
&= u_0 + u_1 (t - t_0) + \frac{u_2}{2} (t - t_0)^2 + \dots
|
||||
|
||||
This class contains multiple methods to convert spline knot data from SI
|
||||
to machine units and multiple methods that set the current spline
|
||||
coefficient data. None of these advance the timeline. The :meth:`smooth`
|
||||
method is the only method that advances the timeline.
|
||||
|
||||
:param width: Width in bits of the quantity that this spline controls
|
||||
:param time_width: Width in bits of the time counter of this spline
|
||||
:param channel: RTIO channel number
|
||||
:param core_device: Core device that this spline is attached to
|
||||
:param scale: Scale for conversion between machine units and physical
|
||||
units; to be given as the "full scale physical value".
|
||||
"""
|
||||
|
||||
kernel_invariants = {"channel", "core", "scale", "width",
|
||||
"time_width", "time_scale"}
|
||||
|
||||
def __init__(self, width, time_width, channel, core_device, scale=1.):
|
||||
self.core = core_device
|
||||
self.channel = channel
|
||||
self.width = width
|
||||
self.scale = float((int64(1) << width) / scale)
|
||||
self.time_width = time_width
|
||||
self.time_scale = float((1 << time_width) *
|
||||
core_device.coarse_ref_period)
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def to_mu(self, value: TFloat) -> TInt32:
|
||||
"""Convert floating point ``value`` from physical units to 32 bit
|
||||
integer machine units."""
|
||||
return int32(round(value*self.scale))
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def from_mu(self, value: TInt32) -> TFloat:
|
||||
"""Convert 32 bit integer ``value`` from machine units to floating
|
||||
point physical units."""
|
||||
return value/self.scale
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def to_mu64(self, value: TFloat) -> TInt64:
|
||||
"""Convert floating point ``value`` from physical units to 64 bit
|
||||
integer machine units."""
|
||||
return int64(round(value*self.scale))
|
||||
|
||||
@kernel
|
||||
def set_mu(self, value: TInt32):
|
||||
"""Set spline value (machine units).
|
||||
|
||||
:param value: Spline value in integer machine units.
|
||||
"""
|
||||
rtio_output(now_mu(), self.channel, 0, value)
|
||||
|
||||
@kernel(flags={"fast-math"})
|
||||
def set(self, value: TFloat):
|
||||
"""Set spline value.
|
||||
|
||||
:param value: Spline value relative to full-scale.
|
||||
"""
|
||||
if self.width > 32:
|
||||
l = [int32(0)] * 2
|
||||
self.pack_coeff_mu([self.to_mu64(value)], l)
|
||||
rtio_output_wide(now_mu(), self.channel, 0, l)
|
||||
else:
|
||||
rtio_output(now_mu(), self.channel, 0, self.to_mu(value))
|
||||
|
||||
@kernel
|
||||
def set_coeff_mu(self, value): # TList(TInt32)
|
||||
"""Set spline raw values.
|
||||
|
||||
:param value: Spline packed raw values.
|
||||
"""
|
||||
rtio_output_wide(now_mu(), self.channel, 0, value)
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def pack_coeff_mu(self, coeff, packed): # TList(TInt64), TList(TInt32)
|
||||
"""Pack coefficients into RTIO data
|
||||
|
||||
:param coeff: TList(TInt64) list of machine units spline coefficients.
|
||||
Lowest (zeroth) order first. The coefficient list is zero-extended
|
||||
by the RTIO gateware.
|
||||
:param packed: TList(TInt32) list for packed RTIO data. Must be
|
||||
pre-allocated. Length in bits is
|
||||
``n*width + (n - 1)*n//2*time_width``
|
||||
"""
|
||||
pos = 0
|
||||
for i in range(len(coeff)):
|
||||
wi = self.width + i*self.time_width
|
||||
ci = coeff[i]
|
||||
while wi != 0:
|
||||
j = pos//32
|
||||
used = pos - 32*j
|
||||
avail = 32 - used
|
||||
if avail > wi:
|
||||
avail = wi
|
||||
cij = int32(ci)
|
||||
if avail != 32:
|
||||
cij &= (1 << avail) - 1
|
||||
packed[j] |= cij << used
|
||||
ci >>= avail
|
||||
wi -= avail
|
||||
pos += avail
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def coeff_to_mu(self, coeff, coeff64): # TList(TFloat), TList(TInt64)
|
||||
"""Convert a floating point list of coefficients into a 64 bit
|
||||
integer (preallocated).
|
||||
|
||||
:param coeff: TList(TFloat) list of coefficients in physical units.
|
||||
:param coeff64: TList(TInt64) preallocated list of coefficients in
|
||||
machine units.
|
||||
"""
|
||||
for i in range(len(coeff)):
|
||||
vi = coeff[i] * self.scale
|
||||
for j in range(i):
|
||||
vi *= self.time_scale
|
||||
ci = int64(round(vi))
|
||||
coeff64[i] = ci
|
||||
# artiq.wavesynth.coefficients.discrete_compensate:
|
||||
if i == 2:
|
||||
coeff64[1] += ci >> self.time_width + 1
|
||||
elif i == 3:
|
||||
coeff64[2] += ci >> self.time_width
|
||||
coeff64[1] += ci // 6 >> 2*self.time_width
|
||||
|
||||
def coeff_as_packed_mu(self, coeff64):
|
||||
"""Pack 64 bit integer machine units coefficients into 32 bit integer
|
||||
RTIO data list.
|
||||
|
||||
This is a host-only method that can be used to generate packed
|
||||
spline coefficient data to be frozen into kernels at compile time.
|
||||
"""
|
||||
n = len(coeff64)
|
||||
width = n*self.width + (n - 1)*n//2*self.time_width
|
||||
packed = [int32(0)] * ((width + 31)//32)
|
||||
self.pack_coeff_mu(coeff64, packed)
|
||||
return packed
|
||||
|
||||
def coeff_as_packed(self, coeff):
|
||||
"""Convert floating point spline coefficients into 32 bit integer
|
||||
packed data.
|
||||
|
||||
This is a host-only method that can be used to generate packed
|
||||
spline coefficient data to be frozen into kernels at compile time.
|
||||
"""
|
||||
coeff64 = [int64(0)] * len(coeff)
|
||||
self.coeff_to_mu(coeff, coeff64)
|
||||
return self.coeff_as_packed_mu(coeff64)
|
||||
|
||||
@kernel(flags={"fast-math"})
|
||||
def set_coeff(self, coeff): # TList(TFloat)
|
||||
"""Set spline coefficients.
|
||||
|
||||
Missing coefficients (high order) are zero-extended byt the RTIO
|
||||
gateware.
|
||||
|
||||
If more coefficients are supplied than the gateware supports the extra
|
||||
coefficients are ignored.
|
||||
|
||||
:param value: List of floating point spline coefficients,
|
||||
lowest order (constant) coefficient first. Units are the
|
||||
unit of this spline's value times increasing powers of 1/s.
|
||||
"""
|
||||
n = len(coeff)
|
||||
coeff64 = [int64(0)] * n
|
||||
self.coeff_to_mu(coeff, coeff64)
|
||||
width = n*self.width + (n - 1)*n//2*self.time_width
|
||||
packed = [int32(0)] * ((width + 31)//32)
|
||||
self.pack_coeff_mu(coeff64, packed)
|
||||
self.set_coeff_mu(packed)
|
||||
|
||||
@kernel(flags={"fast-math"})
|
||||
def smooth(self, start: TFloat, stop: TFloat, duration: TFloat,
|
||||
order: TInt32):
|
||||
"""Initiate an interpolated value change.
|
||||
|
||||
For zeroth order (step) interpolation, the step is at
|
||||
``start + duration/2``.
|
||||
|
||||
First order interpolation corresponds to a linear value ramp from
|
||||
``start`` to ``stop`` over ``duration``.
|
||||
|
||||
The third order interpolation is constrained to have zero first
|
||||
order derivative at both `start` and `stop`.
|
||||
|
||||
For first order and third order interpolation (linear and cubic)
|
||||
the interpolator needs to be stopped explicitly at the stop time
|
||||
(e.g. by setting spline coefficient data or starting a new
|
||||
:meth:`smooth` interpolation).
|
||||
|
||||
This method advances the timeline by ``duration``.
|
||||
|
||||
:param start: Initial value of the change. In physical units.
|
||||
:param stop: Final value of the change. In physical units.
|
||||
:param duration: Duration of the interpolation. In physical units.
|
||||
:param order: Order of the interpolation. Only 0, 1,
|
||||
and 3 are valid: step, linear, cubic.
|
||||
"""
|
||||
if order == 0:
|
||||
delay(duration/2.)
|
||||
self.set_coeff([stop])
|
||||
delay(duration/2.)
|
||||
elif order == 1:
|
||||
self.set_coeff([start, (stop - start)/duration])
|
||||
delay(duration)
|
||||
elif order == 3:
|
||||
v2 = 6.*(stop - start)/(duration*duration)
|
||||
self.set_coeff([start, 0., v2, -2.*v2/duration])
|
||||
delay(duration)
|
||||
else:
|
||||
raise ValueError("Invalid interpolation order. "
|
||||
"Supported orders are: 0, 1, 3.")
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
from artiq.language.core import syscall
|
||||
from artiq.language.types import TInt32, TNone
|
||||
|
||||
|
||||
@syscall(flags={"nounwind", "nowrite"})
|
||||
def mfspr(spr: TInt32) -> TInt32:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
||||
|
||||
@syscall(flags={"nowrite", "nowrite"})
|
||||
def mtspr(spr: TInt32, value: TInt32) -> TNone:
|
||||
raise NotImplementedError("syscall not simulated")
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
from artiq.language.core import kernel, delay, delay_mu, portable
|
||||
from artiq.language.core import kernel, delay, now_mu, delay_mu, portable
|
||||
from artiq.language.units import us, ns
|
||||
from artiq.coredevice.rtio import rtio_output, rtio_input_data
|
||||
from artiq.coredevice import spi2 as spi
|
||||
|
|
@ -6,29 +6,28 @@ from artiq.coredevice import urukul, sampler
|
|||
|
||||
|
||||
COEFF_WIDTH = 18
|
||||
Y_FULL_SCALE_MU = (1 << (COEFF_WIDTH - 1)) - 1
|
||||
COEFF_DEPTH = 10 + 1
|
||||
WE = 1 << COEFF_DEPTH + 1
|
||||
STATE_SEL = 1 << COEFF_DEPTH
|
||||
CONFIG_SEL = 1 << COEFF_DEPTH - 1
|
||||
CONFIG_ADDR = CONFIG_SEL | STATE_SEL
|
||||
T_CYCLE = (2*(8 + 64) + 2)*8*ns # Must match gateware Servo.t_cycle.
|
||||
T_CYCLE = (2*(8 + 64) + 2 + 1)*8*ns
|
||||
COEFF_SHIFT = 11
|
||||
|
||||
|
||||
@portable
|
||||
def y_mu_to_full_scale(y):
|
||||
"""Convert servo Y data from machine units to units of full scale."""
|
||||
return y / Y_FULL_SCALE_MU
|
||||
return y*(1./(1 << COEFF_WIDTH - 1))
|
||||
|
||||
|
||||
@portable
|
||||
def adc_mu_to_volts(x, gain, corrected_fs=True):
|
||||
def adc_mu_to_volts(x, gain):
|
||||
"""Convert servo ADC data from machine units to Volt."""
|
||||
val = (x >> 1) & 0xffff
|
||||
mask = 1 << 15
|
||||
val = -(val & mask) + (val & ~mask)
|
||||
return sampler.adc_mu_to_volt(val, gain, corrected_fs)
|
||||
return sampler.adc_mu_to_volt(val, gain)
|
||||
|
||||
|
||||
class SUServo:
|
||||
|
|
@ -57,38 +56,38 @@ class SUServo:
|
|||
|
||||
:param channel: RTIO channel number
|
||||
:param pgia_device: Name of the Sampler PGIA gain setting SPI bus
|
||||
:param cpld_devices: Names of the Urukul CPLD SPI buses
|
||||
:param dds_devices: Names of the AD9910 devices
|
||||
:param cpld0_device: Name of the first Urukul CPLD SPI bus
|
||||
:param cpld1_device: Name of the second Urukul CPLD SPI bus
|
||||
:param dds0_device: Name of the AD9910 device for the DDS on the first
|
||||
Urukul
|
||||
:param dds1_device: Name of the AD9910 device for the DDS on the second
|
||||
Urukul
|
||||
:param gains: Initial value for PGIA gains shift register
|
||||
(default: 0x0000). Knowledge of this state is not transferred
|
||||
between experiments.
|
||||
:param sampler_hw_rev: Sampler's revision string
|
||||
:param core_device: Core device name
|
||||
"""
|
||||
kernel_invariants = {"channel", "core", "pgia", "cplds", "ddses",
|
||||
"ref_period_mu", "corrected_fs"}
|
||||
kernel_invariants = {"channel", "core", "pgia", "cpld0", "cpld1",
|
||||
"dds0", "dds1", "ref_period_mu"}
|
||||
|
||||
def __init__(self, dmgr, channel, pgia_device,
|
||||
cpld_devices, dds_devices,
|
||||
gains=0x0000, sampler_hw_rev="v2.2", core_device="core"):
|
||||
cpld0_device, cpld1_device,
|
||||
dds0_device, dds1_device,
|
||||
gains=0x0000, core_device="core"):
|
||||
|
||||
self.core = dmgr.get(core_device)
|
||||
self.pgia = dmgr.get(pgia_device)
|
||||
self.pgia.update_xfer_duration_mu(div=4, length=16)
|
||||
assert len(dds_devices) == len(cpld_devices)
|
||||
self.ddses = [dmgr.get(dds) for dds in dds_devices]
|
||||
self.cplds = [dmgr.get(cpld) for cpld in cpld_devices]
|
||||
self.dds0 = dmgr.get(dds0_device)
|
||||
self.dds1 = dmgr.get(dds1_device)
|
||||
self.cpld0 = dmgr.get(cpld0_device)
|
||||
self.cpld1 = dmgr.get(cpld1_device)
|
||||
self.channel = channel
|
||||
self.gains = gains
|
||||
self.ref_period_mu = self.core.seconds_to_mu(
|
||||
self.core.coarse_ref_period)
|
||||
self.corrected_fs = sampler.Sampler.use_corrected_fs(sampler_hw_rev)
|
||||
assert self.ref_period_mu == self.core.ref_multiplier
|
||||
|
||||
@staticmethod
|
||||
def get_rtio_channels(channel, **kwargs):
|
||||
return [(channel, None)]
|
||||
|
||||
@kernel
|
||||
def init(self):
|
||||
"""Initialize the servo, Sampler and both Urukuls.
|
||||
|
|
@ -109,15 +108,17 @@ class SUServo:
|
|||
sampler.SPI_CONFIG | spi.SPI_END,
|
||||
16, 4, sampler.SPI_CS_PGIA)
|
||||
|
||||
for i in range(len(self.cplds)):
|
||||
cpld = self.cplds[i]
|
||||
dds = self.ddses[i]
|
||||
self.cpld0.init(blind=True)
|
||||
cfg0 = self.cpld0.cfg_reg
|
||||
self.cpld0.cfg_write(cfg0 | (0xf << urukul.CFG_MASK_NU))
|
||||
self.dds0.init(blind=True)
|
||||
self.cpld0.cfg_write(cfg0)
|
||||
|
||||
cpld.init(blind=True)
|
||||
prev_cpld_cfg = cpld.cfg_reg
|
||||
cpld.cfg_write(prev_cpld_cfg | (0xf << urukul.CFG_MASK_NU))
|
||||
dds.init(blind=True)
|
||||
cpld.cfg_write(prev_cpld_cfg)
|
||||
self.cpld1.init(blind=True)
|
||||
cfg1 = self.cpld1.cfg_reg
|
||||
self.cpld1.cfg_write(cfg1 | (0xf << urukul.CFG_MASK_NU))
|
||||
self.dds1.init(blind=True)
|
||||
self.cpld1.cfg_write(cfg1)
|
||||
|
||||
@kernel
|
||||
def write(self, addr, value):
|
||||
|
|
@ -128,11 +129,7 @@ class SUServo:
|
|||
:param addr: Memory location address.
|
||||
:param value: Data to be written.
|
||||
"""
|
||||
addr |= WE
|
||||
value &= (1 << COEFF_WIDTH) - 1
|
||||
value |= (addr >> 8) << COEFF_WIDTH
|
||||
addr = addr & 0xff
|
||||
rtio_output((self.channel << 8) | addr, value)
|
||||
rtio_output(now_mu(), self.channel, addr | WE, value)
|
||||
delay_mu(self.ref_period_mu)
|
||||
|
||||
@kernel
|
||||
|
|
@ -143,9 +140,7 @@ class SUServo:
|
|||
|
||||
:param addr: Memory location address.
|
||||
"""
|
||||
value = (addr >> 8) << COEFF_WIDTH
|
||||
addr = addr & 0xff
|
||||
rtio_output((self.channel << 8) | addr, value)
|
||||
rtio_output(now_mu(), self.channel, addr, 0)
|
||||
return rtio_input_data(self.channel)
|
||||
|
||||
@kernel
|
||||
|
|
@ -189,14 +184,10 @@ class SUServo:
|
|||
|
||||
@kernel
|
||||
def get_adc_mu(self, adc):
|
||||
"""Get the latest ADC reading (IIR filter input X0) in machine units.
|
||||
"""Get an ADC reading (IIR filter input X0) in machine units.
|
||||
|
||||
This method does not advance the timeline but consumes all slack.
|
||||
|
||||
If reading servo state through this method collides with the servo
|
||||
writing that same data, the data can become invalid. To ensure
|
||||
consistent and valid data, stop the servo before using this method.
|
||||
|
||||
:param adc: ADC channel number (0-7)
|
||||
:return: 17 bit signed X0
|
||||
"""
|
||||
|
|
@ -223,14 +214,10 @@ class SUServo:
|
|||
|
||||
@kernel
|
||||
def get_adc(self, channel):
|
||||
"""Get the latest ADC reading (IIR filter input X0).
|
||||
"""Get an ADC reading (IIR filter input X0).
|
||||
|
||||
This method does not advance the timeline but consumes all slack.
|
||||
|
||||
If reading servo state through this method collides with the servo
|
||||
writing that same data, the data can become invalid. To ensure
|
||||
consistent and valid data, stop the servo before using this method.
|
||||
|
||||
The PGIA gain setting must be known prior to using this method, either
|
||||
by setting the gain (:meth:`set_pgia_mu`) or by supplying it
|
||||
(:attr:`gains` or via the constructor/device database).
|
||||
|
|
@ -240,7 +227,7 @@ class SUServo:
|
|||
"""
|
||||
val = self.get_adc_mu(channel)
|
||||
gain = (self.gains >> (channel*2)) & 0b11
|
||||
return adc_mu_to_volts(val, gain, self.corrected_fs)
|
||||
return adc_mu_to_volts(val, gain)
|
||||
|
||||
|
||||
class Channel:
|
||||
|
|
@ -255,15 +242,9 @@ class Channel:
|
|||
self.servo = dmgr.get(servo_device)
|
||||
self.core = self.servo.core
|
||||
self.channel = channel
|
||||
# This assumes the mem channel is right after the control channels
|
||||
# Make sure this is always the case in eem.py
|
||||
self.servo_channel = (self.channel + 4 * len(self.servo.cplds) -
|
||||
self.servo.channel)
|
||||
self.dds = self.servo.ddses[self.servo_channel // 4]
|
||||
|
||||
@staticmethod
|
||||
def get_rtio_channels(channel, **kwargs):
|
||||
return [(channel, None)]
|
||||
# FIXME: this assumes the mem channel is right after the control
|
||||
# channels
|
||||
self.servo_channel = self.channel + 8 - self.servo.channel
|
||||
|
||||
@kernel
|
||||
def set(self, en_out, en_iir=0, profile=0):
|
||||
|
|
@ -272,16 +253,16 @@ class Channel:
|
|||
This method does not advance the timeline. Output RF switch setting
|
||||
takes effect immediately and is independent of any other activity
|
||||
(profile settings, other channels). The RF switch behaves like
|
||||
:class:`artiq.coredevice.ttl.TTLOut`. RTIO event replacement is
|
||||
supported. IIR updates take place once the RF switch has been enabled
|
||||
for the configured delay and the profile setting has been stable.
|
||||
Profile changes take between one and two servo cycles to reach the DDS.
|
||||
``TTLOut``. RTIO event replacement is supported. IIR updates take place
|
||||
once the RF switch has been enabled for the configured delay and the
|
||||
profile setting has been stable. Profile changes take between one and
|
||||
two servo cycles to reach the DDS.
|
||||
|
||||
:param en_out: RF switch enable
|
||||
:param en_iir: IIR updates enable
|
||||
:param profile: Active profile (0-31)
|
||||
"""
|
||||
rtio_output(self.channel << 8,
|
||||
rtio_output(now_mu(), self.channel, 0,
|
||||
en_out | (en_iir << 1) | (profile << 2))
|
||||
|
||||
@kernel
|
||||
|
|
@ -297,8 +278,8 @@ class Channel:
|
|||
"""
|
||||
base = (self.servo_channel << 8) | (profile << 3)
|
||||
self.servo.write(base + 0, ftw >> 16)
|
||||
self.servo.write(base + 6, (ftw & 0xffff))
|
||||
self.set_dds_offset_mu(profile, offs)
|
||||
self.servo.write(base + 6, ftw)
|
||||
self.servo.write(base + 4, offs)
|
||||
self.servo.write(base + 2, pow_)
|
||||
|
||||
@kernel
|
||||
|
|
@ -311,49 +292,21 @@ class Channel:
|
|||
|
||||
:param profile: Profile number (0-31)
|
||||
:param frequency: DDS frequency in Hz
|
||||
:param offset: IIR offset (negative setpoint) in units of full scale,
|
||||
see :meth:`dds_offset_to_mu`
|
||||
:param offset: IIR offset (negative setpoint) in units of full scale.
|
||||
For positive ADC voltages as setpoints, this should be negative.
|
||||
Due to rounding and representation as two's complement,
|
||||
``offset=1`` can not be represented while ``offset=-1`` can.
|
||||
:param phase: DDS phase in turns
|
||||
"""
|
||||
ftw = self.dds.frequency_to_ftw(frequency)
|
||||
pow_ = self.dds.turns_to_pow(phase)
|
||||
offs = self.dds_offset_to_mu(offset)
|
||||
if self.servo_channel < 4:
|
||||
dds = self.servo.dds0
|
||||
else:
|
||||
dds = self.servo.dds1
|
||||
ftw = dds.frequency_to_ftw(frequency)
|
||||
pow_ = dds.turns_to_pow(phase)
|
||||
offs = int(round(offset*(1 << COEFF_WIDTH - 1)))
|
||||
self.set_dds_mu(profile, ftw, offs, pow_)
|
||||
|
||||
@kernel
|
||||
def set_dds_offset_mu(self, profile, offs):
|
||||
"""Set only IIR offset in DDS coefficient profile.
|
||||
|
||||
See :meth:`set_dds_mu` for setting the complete DDS profile.
|
||||
|
||||
:param profile: Profile number (0-31)
|
||||
:param offs: IIR offset (17 bit signed)
|
||||
"""
|
||||
base = (self.servo_channel << 8) | (profile << 3)
|
||||
self.servo.write(base + 4, offs)
|
||||
|
||||
@kernel
|
||||
def set_dds_offset(self, profile, offset):
|
||||
"""Set only IIR offset in DDS coefficient profile.
|
||||
|
||||
See :meth:`set_dds` for setting the complete DDS profile.
|
||||
|
||||
:param profile: Profile number (0-31)
|
||||
:param offset: IIR offset (negative setpoint) in units of full scale
|
||||
"""
|
||||
self.set_dds_offset_mu(profile, self.dds_offset_to_mu(offset))
|
||||
|
||||
@portable
|
||||
def dds_offset_to_mu(self, offset):
|
||||
"""Convert IIR offset (negative setpoint) from units of full scale to
|
||||
machine units (see :meth:`set_dds_mu`, :meth:`set_dds_offset_mu`).
|
||||
|
||||
For positive ADC voltages as setpoints, this should be negative. Due to
|
||||
rounding and representation as two's complement, ``offset=1`` can not
|
||||
be represented while ``offset=-1`` can.
|
||||
"""
|
||||
return int(round(offset * (1 << COEFF_WIDTH - 1)))
|
||||
|
||||
@kernel
|
||||
def set_iir_mu(self, profile, adc, a1, b0, b1, dly=0):
|
||||
"""Set profile IIR coefficients in machine units.
|
||||
|
|
@ -490,16 +443,12 @@ class Channel:
|
|||
"""Get a profile's IIR state (filter output, Y0) in machine units.
|
||||
|
||||
The IIR state is also know as the "integrator", or the DDS amplitude
|
||||
scale factor. It is 17 bits wide and unsigned.
|
||||
scale factor. It is 18 bits wide and unsigned.
|
||||
|
||||
This method does not advance the timeline but consumes all slack.
|
||||
|
||||
If reading servo state through this method collides with the servo
|
||||
writing that same data, the data can become invalid. To ensure
|
||||
consistent and valid data, stop the servo before using this method.
|
||||
|
||||
:param profile: Profile number (0-31)
|
||||
:return: 17 bit unsigned Y0
|
||||
:return: 18 bit unsigned Y0
|
||||
"""
|
||||
return self.servo.read(STATE_SEL | (self.servo_channel << 5) | profile)
|
||||
|
||||
|
|
@ -508,14 +457,10 @@ class Channel:
|
|||
"""Get a profile's IIR state (filter output, Y0).
|
||||
|
||||
The IIR state is also know as the "integrator", or the DDS amplitude
|
||||
scale factor. It is 17 bits wide and unsigned.
|
||||
scale factor. It is 18 bits wide and unsigned.
|
||||
|
||||
This method does not advance the timeline but consumes all slack.
|
||||
|
||||
If reading servo state through this method collides with the servo
|
||||
writing that same data, the data can become invalid. To ensure
|
||||
consistent and valid data, stop the servo before using this method.
|
||||
|
||||
:param profile: Profile number (0-31)
|
||||
:return: IIR filter output in Y0 units of full scale
|
||||
"""
|
||||
|
|
@ -526,7 +471,7 @@ class Channel:
|
|||
"""Set a profile's IIR state (filter output, Y0) in machine units.
|
||||
|
||||
The IIR state is also know as the "integrator", or the DDS amplitude
|
||||
scale factor. It is 17 bits wide and unsigned.
|
||||
scale factor. It is 18 bits wide and unsigned.
|
||||
|
||||
This method must not be used when the servo could be writing to the
|
||||
same location. Either deactivate the profile, or deactivate IIR
|
||||
|
|
@ -546,7 +491,7 @@ class Channel:
|
|||
"""Set a profile's IIR state (filter output, Y0).
|
||||
|
||||
The IIR state is also know as the "integrator", or the DDS amplitude
|
||||
scale factor. It is 17 bits wide and unsigned.
|
||||
scale factor. It is 18 bits wide and unsigned.
|
||||
|
||||
This method must not be used when the servo could be writing to the
|
||||
same location. Either deactivate the profile, or deactivate IIR
|
||||
|
|
@ -557,8 +502,4 @@ class Channel:
|
|||
:param profile: Profile number (0-31)
|
||||
:param y: IIR state in units of full scale
|
||||
"""
|
||||
y_mu = int(round(y * Y_FULL_SCALE_MU))
|
||||
if y_mu < 0 or y_mu > (1 << 17) - 1:
|
||||
raise ValueError("Invalid SUServo y-value!")
|
||||
self.set_y_mu(profile, y_mu)
|
||||
return y_mu
|
||||
self.set_y_mu(profile, int(round((1 << COEFF_WIDTH - 1)*y)))
|
||||
|
|
|
|||
|
|
@ -1,136 +0,0 @@
|
|||
class TRF372017:
|
||||
"""TRF372017 settings and register map.
|
||||
|
||||
For possible values, documentation, and explanation, see the datasheet.
|
||||
https://www.ti.com/lit/gpn/trf372017
|
||||
"""
|
||||
rdiv = 2 # 13b - highest valid f_PFD
|
||||
ref_inv = 0
|
||||
neg_vco = 1
|
||||
icp = 0 # 1.94 mA, 5b
|
||||
icp_double = 0
|
||||
cal_clk_sel = 0b1110 # div64, 4b
|
||||
|
||||
# default f_vco is 2.875 GHz
|
||||
nint = 23 # 16b - lowest value suitable for fractional & integer mode
|
||||
pll_div_sel = 0b01 # div2, 2b
|
||||
prsc_sel = 0 # 4/5
|
||||
vco_sel = 2 # 2b
|
||||
vcosel_mode = 0
|
||||
cal_acc = 0b00 # 2b
|
||||
en_cal = 0 # leave at 0 - calibration is performed in `Phaser.init()`
|
||||
|
||||
nfrac = 0 # 25b
|
||||
|
||||
pwd_pll = 0
|
||||
pwd_cp = 0
|
||||
pwd_vco = 0
|
||||
pwd_vcomux = 0
|
||||
pwd_div124 = 0
|
||||
pwd_presc = 0
|
||||
pwd_out_buff = 1 # leave at 1 - only enable outputs after calibration
|
||||
pwd_lo_div = 1 # leave at 1 - only enable outputs after calibration
|
||||
pwd_tx_div = 1 # leave at 1 - only enable outputs after calibration
|
||||
pwd_bb_vcm = 0
|
||||
pwd_dc_off = 0
|
||||
en_extvco = 0
|
||||
en_isource = 0
|
||||
ld_ana_prec = 0 # 2b
|
||||
cp_tristate = 0 # 2b
|
||||
speedup = 0
|
||||
ld_dig_prec = 1
|
||||
en_dith = 1
|
||||
mod_ord = 2 # 3rd order, 2b
|
||||
dith_sel = 0
|
||||
del_sd_clk = 2 # 2b
|
||||
en_frac = 0
|
||||
|
||||
vcobias_rtrim = 4 # 3b
|
||||
pllbias_rtrim = 2 # 2b
|
||||
vco_bias = 8 # 460 µA, 4b
|
||||
vcobuf_bias = 2 # 2b
|
||||
vcomux_bias = 3 # 2b
|
||||
bufout_bias = 0 # 300 µA, 2b
|
||||
vco_cal_ib = 0 # PTAT
|
||||
vco_cal_ref = 2 # 1.04 V, 2b
|
||||
vco_ampl_ctrl = 3 # 2b
|
||||
vco_vb_ctrl = 0 # 1.2 V, 2b
|
||||
en_ld_isource = 0
|
||||
|
||||
ioff = 0x80 # 8b
|
||||
qoff = 0x80 # 8b
|
||||
vref_sel = 4 # 0.85 V, 3b
|
||||
tx_div_sel = 0 # div1, 2b
|
||||
lo_div_sel = 0 # div1, 2b
|
||||
tx_div_bias = 1 # 37.5 µA, 2b
|
||||
lo_div_bias = 2 # 50 µA, 2b
|
||||
|
||||
vco_trim = 0x20 # 6b
|
||||
vco_test_mode = 0
|
||||
cal_bypass = 0
|
||||
mux_ctrl = 1 # lock detect, 3b
|
||||
isource_sink = 0
|
||||
isource_trim = 4 # 3b
|
||||
pd_tc = 0 # 2b
|
||||
ib_vcm_sel = 0 # ptat
|
||||
dcoffset_i = 2 # 150 µA, 2b
|
||||
vco_bias_sel = 1 # spi
|
||||
|
||||
def __init__(self, updates=None):
|
||||
if updates is None:
|
||||
return
|
||||
for key, value in updates.items():
|
||||
if not hasattr(self, key):
|
||||
raise KeyError("invalid setting", key)
|
||||
setattr(self, key, value)
|
||||
|
||||
def get_mmap(self):
|
||||
"""Memory map for TRF372017"""
|
||||
mmap = []
|
||||
mmap.append(
|
||||
0x9 |
|
||||
(self.rdiv << 5) | (self.ref_inv << 19) | (self.neg_vco << 20) |
|
||||
(self.icp << 21) | (self.icp_double << 26) |
|
||||
(self.cal_clk_sel << 27))
|
||||
mmap.append(
|
||||
0xa |
|
||||
(self.nint << 5) | (self.pll_div_sel << 21) |
|
||||
(self.prsc_sel << 23) | (self.vco_sel << 26) |
|
||||
(self.vcosel_mode << 28) | (self.cal_acc << 29) |
|
||||
(self.en_cal << 31))
|
||||
mmap.append(0xb | (self.nfrac << 5))
|
||||
mmap.append(
|
||||
0xc |
|
||||
(self.pwd_pll << 5) | (self.pwd_cp << 6) | (self.pwd_vco << 7) |
|
||||
(self.pwd_vcomux << 8) | (self.pwd_div124 << 9) |
|
||||
(self.pwd_presc << 10) | (self.pwd_out_buff << 12) |
|
||||
(self.pwd_lo_div << 13) | (self.pwd_tx_div << 14) |
|
||||
(self.pwd_bb_vcm << 15) | (self.pwd_dc_off << 16) |
|
||||
(self.en_extvco << 17) | (self.en_isource << 18) |
|
||||
(self.ld_ana_prec << 19) | (self.cp_tristate << 21) |
|
||||
(self.speedup << 23) | (self.ld_dig_prec << 24) |
|
||||
(self.en_dith << 25) | (self.mod_ord << 26) |
|
||||
(self.dith_sel << 28) | (self.del_sd_clk << 29) |
|
||||
(self.en_frac << 31))
|
||||
mmap.append(
|
||||
0xd |
|
||||
(self.vcobias_rtrim << 5) | (self.pllbias_rtrim << 8) |
|
||||
(self.vco_bias << 10) | (self.vcobuf_bias << 14) |
|
||||
(self.vcomux_bias << 16) | (self.bufout_bias << 18) |
|
||||
(1 << 21) | (self.vco_cal_ib << 22) | (self.vco_cal_ref << 23) |
|
||||
(self.vco_ampl_ctrl << 26) | (self.vco_vb_ctrl << 28) |
|
||||
(self.en_ld_isource << 31))
|
||||
mmap.append(
|
||||
0xe |
|
||||
(self.ioff << 5) | (self.qoff << 13) | (self.vref_sel << 21) |
|
||||
(self.tx_div_sel << 24) | (self.lo_div_sel << 26) |
|
||||
(self.tx_div_bias << 28) | (self.lo_div_bias << 30))
|
||||
mmap.append(
|
||||
0xf |
|
||||
(self.vco_trim << 7) | (self.vco_test_mode << 14) |
|
||||
(self.cal_bypass << 15) | (self.mux_ctrl << 16) |
|
||||
(self.isource_sink << 19) | (self.isource_trim << 20) |
|
||||
(self.pd_tc << 23) | (self.ib_vcm_sel << 25) |
|
||||
(1 << 28) | (self.dcoffset_i << 29) |
|
||||
(self.vco_bias_sel << 31))
|
||||
return mmap
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
Drivers for TTL signals on RTIO.
|
||||
|
||||
TTL channels (including the clock generator) all support output event
|
||||
replacement. For example, pulses of "zero" length (e.g. :meth:`TTLInOut.on`
|
||||
immediately followed by :meth:`TTLInOut.off`, without a delay) are suppressed.
|
||||
replacement. For example, pulses of "zero" length (e.g. ``on()``
|
||||
immediately followed by ``off()``, without a delay) are suppressed.
|
||||
"""
|
||||
|
||||
import numpy
|
||||
|
|
@ -29,16 +29,14 @@ class TTLOut:
|
|||
|
||||
:param channel: channel number
|
||||
"""
|
||||
kernel_invariants = {"core", "channel", "target_o"}
|
||||
kernel_invariants = {"core", "channel"}
|
||||
|
||||
def __init__(self, dmgr, channel, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.channel = channel
|
||||
self.target_o = channel << 8
|
||||
|
||||
@staticmethod
|
||||
def get_rtio_channels(channel, **kwargs):
|
||||
return [(channel, None)]
|
||||
# in RTIO cycles
|
||||
self.o_previous_timestamp = numpy.int64(0)
|
||||
|
||||
@kernel
|
||||
def output(self):
|
||||
|
|
@ -46,11 +44,19 @@ class TTLOut:
|
|||
|
||||
@kernel
|
||||
def set_o(self, o):
|
||||
rtio_output(self.target_o, 1 if o else 0)
|
||||
rtio_output(now_mu(), self.channel, 0, 1 if o else 0)
|
||||
self.o_previous_timestamp = now_mu()
|
||||
|
||||
@kernel
|
||||
def sync(self):
|
||||
"""Busy-wait until all programmed level switches have been
|
||||
effected."""
|
||||
while self.core.get_rtio_counter_mu() < self.o_previous_timestamp:
|
||||
pass
|
||||
|
||||
@kernel
|
||||
def on(self):
|
||||
"""Set the output to a logic high state at the current position
|
||||
"""Sets the output to a logic high state at the current position
|
||||
of the time cursor.
|
||||
|
||||
The time cursor is not modified by this function."""
|
||||
|
|
@ -101,8 +107,8 @@ class TTLInOut:
|
|||
This should be used with bidirectional channels.
|
||||
|
||||
Note that the channel is in input mode by default. If you need to drive a
|
||||
signal, you must call :meth:`output`. If the channel is in output mode most of
|
||||
the time in your setup, it is a good idea to call :meth:`output` in the
|
||||
signal, you must call ``output``. If the channel is in output mode most of
|
||||
the time in your setup, it is a good idea to call ``output`` in the
|
||||
startup kernel.
|
||||
|
||||
There are three input APIs: gating, sampling and watching. When one
|
||||
|
|
@ -111,34 +117,20 @@ class TTLInOut:
|
|||
|
||||
:param channel: channel number
|
||||
"""
|
||||
kernel_invariants = {"core", "channel", "gate_latency_mu",
|
||||
"target_o", "target_oe", "target_sens", "target_sample"}
|
||||
kernel_invariants = {"core", "channel"}
|
||||
|
||||
def __init__(self, dmgr, channel, gate_latency_mu=None,
|
||||
core_device="core"):
|
||||
def __init__(self, dmgr, channel, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.channel = channel
|
||||
|
||||
# With TTLs inputs, the gate control is connected to a high-latency
|
||||
# path through SED. When looking at the RTIO counter to determine if
|
||||
# the gate has closed, we need to take this latency into account.
|
||||
# See: https://github.com/m-labs/artiq/issues/1137
|
||||
if gate_latency_mu is None:
|
||||
gate_latency_mu = 13*self.core.ref_multiplier
|
||||
self.gate_latency_mu = gate_latency_mu
|
||||
|
||||
self.target_o = (channel << 8) + 0
|
||||
self.target_oe = (channel << 8) + 1
|
||||
self.target_sens = (channel << 8) + 2
|
||||
self.target_sample = (channel << 8) + 3
|
||||
|
||||
@staticmethod
|
||||
def get_rtio_channels(channel, **kwargs):
|
||||
return [(channel, None)]
|
||||
# in RTIO cycles
|
||||
self.o_previous_timestamp = numpy.int64(0)
|
||||
self.i_previous_timestamp = numpy.int64(0)
|
||||
self.queued_samples = 0
|
||||
|
||||
@kernel
|
||||
def set_oe(self, oe):
|
||||
rtio_output(self.target_oe, 1 if oe else 0)
|
||||
rtio_output(now_mu(), self.channel, 1, 1 if oe else 0)
|
||||
|
||||
@kernel
|
||||
def output(self):
|
||||
|
|
@ -146,11 +138,7 @@ class TTLInOut:
|
|||
cursor.
|
||||
|
||||
There must be a delay of at least one RTIO clock cycle before any
|
||||
other command can be issued.
|
||||
|
||||
This method only configures the direction at the FPGA. When using
|
||||
buffered I/O interfaces, such as the Sinara TTL cards, the buffer
|
||||
direction must be configured separately in the hardware."""
|
||||
other command can be issued."""
|
||||
self.set_oe(True)
|
||||
|
||||
@kernel
|
||||
|
|
@ -159,16 +147,20 @@ class TTLInOut:
|
|||
cursor.
|
||||
|
||||
There must be a delay of at least one RTIO clock cycle before any
|
||||
other command can be issued.
|
||||
|
||||
This method only configures the direction at the FPGA. When using
|
||||
buffered I/O interfaces, such as the Sinara TTL cards, the buffer
|
||||
direction must be configured separately in the hardware."""
|
||||
other command can be issued."""
|
||||
self.set_oe(False)
|
||||
|
||||
@kernel
|
||||
def set_o(self, o):
|
||||
rtio_output(self.target_o, 1 if o else 0)
|
||||
rtio_output(now_mu(), self.channel, 0, 1 if o else 0)
|
||||
self.o_previous_timestamp = now_mu()
|
||||
|
||||
@kernel
|
||||
def sync(self):
|
||||
"""Busy-wait until all programmed level switches have been
|
||||
effected."""
|
||||
while self.core.get_rtio_counter_mu() < self.o_previous_timestamp:
|
||||
pass
|
||||
|
||||
@kernel
|
||||
def on(self):
|
||||
|
|
@ -192,7 +184,7 @@ class TTLInOut:
|
|||
|
||||
@kernel
|
||||
def pulse_mu(self, duration):
|
||||
"""Pulse the output high for the specified duration
|
||||
"""Pulses the output high for the specified duration
|
||||
(in machine units).
|
||||
|
||||
The time cursor is advanced by the specified duration."""
|
||||
|
|
@ -202,7 +194,7 @@ class TTLInOut:
|
|||
|
||||
@kernel
|
||||
def pulse(self, duration):
|
||||
"""Pulse the output high for the specified duration
|
||||
"""Pulses the output high for the specified duration
|
||||
(in seconds).
|
||||
|
||||
The time cursor is advanced by the specified duration."""
|
||||
|
|
@ -213,172 +205,89 @@ class TTLInOut:
|
|||
# Input API: gating
|
||||
@kernel
|
||||
def _set_sensitivity(self, value):
|
||||
rtio_output(self.target_sens, value)
|
||||
rtio_output(now_mu(), self.channel, 2, value)
|
||||
self.i_previous_timestamp = now_mu()
|
||||
|
||||
@kernel
|
||||
def gate_rising_mu(self, duration):
|
||||
"""Register rising edge events for the specified duration
|
||||
(in machine units).
|
||||
|
||||
The time cursor is advanced by the specified duration.
|
||||
|
||||
:return: The timeline cursor at the end of the gate window, for
|
||||
convenience when used with :meth:`count`/:meth:`timestamp_mu`.
|
||||
"""
|
||||
The time cursor is advanced by the specified duration."""
|
||||
self._set_sensitivity(1)
|
||||
delay_mu(duration)
|
||||
self._set_sensitivity(0)
|
||||
return now_mu()
|
||||
|
||||
@kernel
|
||||
def gate_falling_mu(self, duration):
|
||||
"""Register falling edge events for the specified duration
|
||||
(in machine units).
|
||||
|
||||
The time cursor is advanced by the specified duration.
|
||||
|
||||
:return: The timeline cursor at the end of the gate window, for
|
||||
convenience when used with :meth:`count`/:meth:`timestamp_mu`.
|
||||
"""
|
||||
The time cursor is advanced by the specified duration."""
|
||||
self._set_sensitivity(2)
|
||||
delay_mu(duration)
|
||||
self._set_sensitivity(0)
|
||||
return now_mu()
|
||||
|
||||
@kernel
|
||||
def gate_both_mu(self, duration):
|
||||
"""Register both rising and falling edge events for the specified
|
||||
duration (in machine units).
|
||||
|
||||
The time cursor is advanced by the specified duration.
|
||||
|
||||
:return: The timeline cursor at the end of the gate window, for
|
||||
convenience when used with :meth:`count`/:meth:`timestamp_mu`.
|
||||
"""
|
||||
The time cursor is advanced by the specified duration."""
|
||||
self._set_sensitivity(3)
|
||||
delay_mu(duration)
|
||||
self._set_sensitivity(0)
|
||||
return now_mu()
|
||||
|
||||
@kernel
|
||||
def gate_rising(self, duration):
|
||||
"""Register rising edge events for the specified duration
|
||||
(in seconds).
|
||||
|
||||
The time cursor is advanced by the specified duration.
|
||||
|
||||
:return: The timeline cursor at the end of the gate window, for
|
||||
convenience when used with :meth:`count`/:meth:`timestamp_mu`.
|
||||
"""
|
||||
The time cursor is advanced by the specified duration."""
|
||||
self._set_sensitivity(1)
|
||||
delay(duration)
|
||||
self._set_sensitivity(0)
|
||||
return now_mu()
|
||||
|
||||
@kernel
|
||||
def gate_falling(self, duration):
|
||||
"""Register falling edge events for the specified duration
|
||||
(in seconds).
|
||||
|
||||
The time cursor is advanced by the specified duration.
|
||||
|
||||
:return: The timeline cursor at the end of the gate window, for
|
||||
convenience when used with :meth:`count`/:meth:`timestamp_mu`.
|
||||
|
||||
"""
|
||||
The time cursor is advanced by the specified duration."""
|
||||
self._set_sensitivity(2)
|
||||
delay(duration)
|
||||
self._set_sensitivity(0)
|
||||
return now_mu()
|
||||
|
||||
@kernel
|
||||
def gate_both(self, duration):
|
||||
"""Register both rising and falling edge events for the specified
|
||||
duration (in seconds).
|
||||
|
||||
The time cursor is advanced by the specified duration.
|
||||
|
||||
:return: The timeline cursor at the end of the gate window, for
|
||||
convenience when used with :meth:`count`/:meth:`timestamp_mu`.
|
||||
"""
|
||||
The time cursor is advanced by the specified duration."""
|
||||
self._set_sensitivity(3)
|
||||
delay(duration)
|
||||
self._set_sensitivity(0)
|
||||
return now_mu()
|
||||
|
||||
@kernel
|
||||
def count(self, up_to_timestamp_mu):
|
||||
"""Consume RTIO input events until the hardware timestamp counter has
|
||||
reached the specified timestamp and return the number of observed
|
||||
events.
|
||||
def count(self):
|
||||
"""Poll the RTIO input during all the previously programmed gate
|
||||
openings, and returns the number of registered events.
|
||||
|
||||
This function does not interact with the timeline cursor.
|
||||
|
||||
See the ``gate_*()`` family of methods to select the input transitions
|
||||
that generate events, and :meth:`timestamp_mu` to obtain the timestamp
|
||||
of the first event rather than an accumulated count.
|
||||
|
||||
:param up_to_timestamp_mu: The timestamp up to which execution is
|
||||
blocked, that is, up to which input events are guaranteed to be
|
||||
taken into account. (Events with later timestamps might still be
|
||||
registered if they are already available.)
|
||||
|
||||
:return: The number of events before the timeout elapsed (0 if none
|
||||
observed).
|
||||
|
||||
Examples:
|
||||
To count events on channel ``ttl_input``, up to the current timeline
|
||||
position::
|
||||
|
||||
ttl_input.count(now_mu())
|
||||
|
||||
If other events are scheduled between the end of the input gate
|
||||
period and when the number of events is counted, using ``now_mu()``
|
||||
as timeout consumes an unnecessary amount of timeline slack. In
|
||||
such cases, it can be beneficial to pass a more precise timestamp,
|
||||
for example::
|
||||
|
||||
gate_end_mu = ttl_input.gate_rising(100 * us)
|
||||
|
||||
# Schedule a long pulse sequence, represented here by a delay.
|
||||
delay(10 * ms)
|
||||
|
||||
# Get number of rising edges. This will block until the end of
|
||||
# the gate window, but does not wait for the long pulse sequence
|
||||
# afterwards, thus (likely) completing with a large amount of
|
||||
# slack left.
|
||||
num_rising_edges = ttl_input.count(gate_end_mu)
|
||||
|
||||
The ``gate_*()`` family of methods return the cursor at the end
|
||||
of the window, allowing this to be expressed in a compact fashion::
|
||||
|
||||
ttl_input.count(ttl_input.gate_rising(100 * us))
|
||||
"""
|
||||
This function does not interact with the time cursor."""
|
||||
count = 0
|
||||
while rtio_input_timestamp(up_to_timestamp_mu + self.gate_latency_mu, self.channel) >= 0:
|
||||
while rtio_input_timestamp(self.i_previous_timestamp, self.channel) >= 0:
|
||||
count += 1
|
||||
return count
|
||||
|
||||
@kernel
|
||||
def timestamp_mu(self, up_to_timestamp_mu):
|
||||
"""Return the timestamp of the next RTIO input event, or -1 if the
|
||||
hardware timestamp counter reaches the given value before an event is
|
||||
received.
|
||||
def timestamp_mu(self):
|
||||
"""Poll the RTIO input and returns an event timestamp (in machine
|
||||
units), according to the gating.
|
||||
|
||||
This function does not interact with the timeline cursor.
|
||||
If the gate is permanently closed, returns a negative value.
|
||||
|
||||
See the ``gate_*()`` family of methods to select the input transitions
|
||||
that generate events, and :meth:`count` for usage examples.
|
||||
|
||||
:param up_to_timestamp_mu: The timestamp up to which execution is
|
||||
blocked, that is, up to which input events are guaranteed to be
|
||||
taken into account. (Events with later timestamps might still be
|
||||
registered if they are already available.)
|
||||
|
||||
:return: The timestamp (in machine units) of the first event received;
|
||||
-1 on timeout.
|
||||
"""
|
||||
return rtio_input_timestamp(up_to_timestamp_mu + self.gate_latency_mu, self.channel)
|
||||
This function does not interact with the time cursor."""
|
||||
return rtio_input_timestamp(self.i_previous_timestamp, self.channel)
|
||||
|
||||
# Input API: sampling
|
||||
@kernel
|
||||
|
|
@ -387,15 +296,15 @@ class TTLInOut:
|
|||
position of the time cursor.
|
||||
|
||||
The time cursor is not modified by this function."""
|
||||
rtio_output(self.target_sample, 0)
|
||||
rtio_output(now_mu(), self.channel, 3, 0)
|
||||
|
||||
@kernel
|
||||
def sample_get(self):
|
||||
"""Returns the value of a sample previously obtained with
|
||||
:meth:`sample_input`.
|
||||
``sample_input``.
|
||||
|
||||
Multiple samples may be queued (using multiple calls to
|
||||
:meth:`sample_input`) into the RTIO FIFOs and subsequently read out using
|
||||
``sample_input``) into the RTIO FIFOs and subsequently read out using
|
||||
multiple calls to this function.
|
||||
|
||||
This function does not interact with the time cursor."""
|
||||
|
|
@ -415,22 +324,22 @@ class TTLInOut:
|
|||
@kernel
|
||||
def watch_stay_on(self):
|
||||
"""Checks that the input is at a high level at the position
|
||||
of the time cursor and keep checking until :meth:`watch_done`
|
||||
of the time cursor and keep checking until ``watch_done``
|
||||
is called.
|
||||
|
||||
Returns ``True`` if the input is high. A call to this function
|
||||
must always be followed by an eventual call to :meth:`watch_done`
|
||||
must always be followed by an eventual call to ``watch_done``
|
||||
(use e.g. a try/finally construct to ensure this).
|
||||
|
||||
The time cursor is not modified by this function.
|
||||
"""
|
||||
rtio_output(self.target_sample, 2) # gate falling
|
||||
rtio_output(now_mu(), self.channel, 3, 2) # gate falling
|
||||
return rtio_input_data(self.channel) == 1
|
||||
|
||||
@kernel
|
||||
def watch_stay_off(self):
|
||||
"""Like :meth:`watch_stay_on`, but for low levels."""
|
||||
rtio_output(self.target_sample, 1) # gate rising
|
||||
"""Like ``watch_stay_on``, but for low levels."""
|
||||
rtio_output(now_mu(), self.channel, 3, 1) # gate rising
|
||||
return rtio_input_data(self.channel) == 0
|
||||
|
||||
@kernel
|
||||
|
|
@ -443,10 +352,10 @@ class TTLInOut:
|
|||
The time cursor is not modified by this function. This function
|
||||
always makes the slack negative.
|
||||
"""
|
||||
rtio_output(self.target_sens, 0)
|
||||
rtio_output(now_mu(), self.channel, 2, 0)
|
||||
success = True
|
||||
try:
|
||||
while rtio_input_timestamp(now_mu() + self.gate_latency_mu, self.channel) != -1:
|
||||
while rtio_input_timestamp(now_mu(), self.channel) != -1:
|
||||
success = False
|
||||
except RTIOOverflow:
|
||||
success = False
|
||||
|
|
@ -462,20 +371,16 @@ class TTLClockGen:
|
|||
The time cursor is not modified by any function in this class.
|
||||
|
||||
:param channel: channel number
|
||||
:param acc_width: accumulator width in bits
|
||||
"""
|
||||
kernel_invariants = {"core", "channel", "target", "acc_width"}
|
||||
kernel_invariants = {"core", "channel", "acc_width"}
|
||||
|
||||
def __init__(self, dmgr, channel, acc_width=24, core_device="core"):
|
||||
def __init__(self, dmgr, channel, core_device="core"):
|
||||
self.core = dmgr.get(core_device)
|
||||
self.channel = channel
|
||||
self.target = channel << 8
|
||||
|
||||
self.acc_width = numpy.int64(acc_width)
|
||||
|
||||
@staticmethod
|
||||
def get_rtio_channels(channel, **kwargs):
|
||||
return [(channel, None)]
|
||||
# in RTIO cycles
|
||||
self.previous_timestamp = numpy.int64(0)
|
||||
self.acc_width = numpy.int64(24)
|
||||
|
||||
@portable
|
||||
def frequency_to_ftw(self, frequency):
|
||||
|
|
@ -509,14 +414,22 @@ class TTLClockGen:
|
|||
Due to the way the clock generator operates, frequency tuning words
|
||||
that are not powers of two cause jitter of one RTIO clock cycle at the
|
||||
output."""
|
||||
rtio_output(self.target, frequency)
|
||||
rtio_output(now_mu(), self.channel, 0, frequency)
|
||||
self.previous_timestamp = now_mu()
|
||||
|
||||
@kernel
|
||||
def set(self, frequency):
|
||||
"""Like :meth:`set_mu`, but using Hz."""
|
||||
"""Like ``set_mu``, but using Hz."""
|
||||
self.set_mu(self.frequency_to_ftw(frequency))
|
||||
|
||||
@kernel
|
||||
def stop(self):
|
||||
"""Stop the toggling of the clock and set the output level to 0."""
|
||||
self.set_mu(0)
|
||||
|
||||
@kernel
|
||||
def sync(self):
|
||||
"""Busy-wait until all programmed frequency switches and stops have
|
||||
been effected."""
|
||||
while self.core.get_rtio_counter_mu() < self.o_previous_timestamp:
|
||||
pass
|
||||
|
|
|
|||
|
|
@ -1,21 +1,20 @@
|
|||
from numpy import int32, int64
|
||||
|
||||
from artiq.language.core import kernel, delay, portable, at_mu, now_mu
|
||||
from artiq.language.core import kernel, delay, portable
|
||||
from artiq.language.units import us, ms
|
||||
from artiq.language.types import TInt32, TFloat, TBool
|
||||
|
||||
from numpy import int32, int64
|
||||
|
||||
from artiq.coredevice import spi2 as spi
|
||||
|
||||
SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END |
|
||||
0 * spi.SPI_INPUT | 1 * spi.SPI_CS_POLARITY |
|
||||
0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE |
|
||||
0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX)
|
||||
|
||||
SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_END |
|
||||
0*spi.SPI_INPUT | 1*spi.SPI_CS_POLARITY |
|
||||
0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
|
||||
0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
|
||||
|
||||
# SPI clock write and read dividers
|
||||
SPIT_CFG_WR = 2
|
||||
SPIT_CFG_RD = 16
|
||||
# 30 MHz fmax, 20 ns setup, 40 ns shift to latch (limiting)
|
||||
SPIT_ATT_WR = 6
|
||||
SPIT_ATT_WR = 2
|
||||
SPIT_ATT_RD = 16
|
||||
SPIT_DDS_WR = 2
|
||||
SPIT_DDS_RD = 16
|
||||
|
|
@ -26,12 +25,10 @@ CFG_LED = 4
|
|||
CFG_PROFILE = 8
|
||||
CFG_IO_UPDATE = 12
|
||||
CFG_MASK_NU = 13
|
||||
CFG_CLK_SEL0 = 17
|
||||
CFG_CLK_SEL1 = 21
|
||||
CFG_CLK_SEL = 17
|
||||
CFG_SYNC_SEL = 18
|
||||
CFG_RST = 19
|
||||
CFG_IO_RST = 20
|
||||
CFG_CLK_DIV = 22
|
||||
|
||||
# STA status register bit offsets
|
||||
STA_RF_SW = 0
|
||||
|
|
@ -52,25 +49,20 @@ CS_DDS_CH1 = 5
|
|||
CS_DDS_CH2 = 6
|
||||
CS_DDS_CH3 = 7
|
||||
|
||||
# Default profile
|
||||
DEFAULT_PROFILE = 7
|
||||
|
||||
|
||||
@portable
|
||||
def urukul_cfg(rf_sw, led, profile, io_update, mask_nu,
|
||||
clk_sel, sync_sel, rst, io_rst, clk_div):
|
||||
clk_sel, sync_sel, rst, io_rst):
|
||||
"""Build Urukul CPLD configuration register"""
|
||||
return ((rf_sw << CFG_RF_SW) |
|
||||
(led << CFG_LED) |
|
||||
(profile << CFG_PROFILE) |
|
||||
(io_update << CFG_IO_UPDATE) |
|
||||
(mask_nu << CFG_MASK_NU) |
|
||||
((clk_sel & 0x01) << CFG_CLK_SEL0) |
|
||||
((clk_sel & 0x02) << (CFG_CLK_SEL1 - 1)) |
|
||||
(clk_sel << CFG_CLK_SEL) |
|
||||
(sync_sel << CFG_SYNC_SEL) |
|
||||
(rst << CFG_RST) |
|
||||
(io_rst << CFG_IO_RST) |
|
||||
(clk_div << CFG_CLK_DIV))
|
||||
(io_rst << CFG_IO_RST))
|
||||
|
||||
|
||||
@portable
|
||||
|
|
@ -108,72 +100,40 @@ class _RegIOUpdate:
|
|||
self.cpld = cpld
|
||||
|
||||
@kernel
|
||||
def pulse(self, t: TFloat):
|
||||
def pulse(self, t):
|
||||
cfg = self.cpld.cfg_reg
|
||||
self.cpld.cfg_write(cfg | (1 << CFG_IO_UPDATE))
|
||||
delay(t)
|
||||
self.cpld.cfg_write(cfg)
|
||||
|
||||
|
||||
class _DummySync:
|
||||
def __init__(self, cpld):
|
||||
self.cpld = cpld
|
||||
|
||||
@kernel
|
||||
def set_mu(self, ftw: TInt32):
|
||||
pass
|
||||
|
||||
|
||||
class CPLD:
|
||||
"""Urukul CPLD SPI router and configuration interface.
|
||||
|
||||
:param spi_device: SPI bus device name
|
||||
:param io_update_device: IO update RTIO TTLOut channel name
|
||||
:param dds_reset_device: DDS reset RTIO TTLOut channel name
|
||||
:param sync_device: AD9910 SYNC_IN RTIO TTLClockGen channel name
|
||||
:param refclk: Reference clock (SMA, MMCX or on-board 100 MHz oscillator)
|
||||
frequency in Hz
|
||||
:param clk_sel: Reference clock selection. For hardware revision >= 1.3
|
||||
valid options are: 0 - internal 100MHz XO; 1 - front-panel SMA; 2
|
||||
internal MMCX. For hardware revision <= v1.2 valid options are: 0 -
|
||||
either XO or MMCX dependent on component population; 1 SMA. Unsupported
|
||||
clocking options are silently ignored.
|
||||
:param clk_div: Reference clock divider. Valid options are 0: variant
|
||||
dependent default (divide-by-4 for AD9910 and divide-by-1 for AD9912);
|
||||
1: divide-by-1; 2: divide-by-2; 3: divide-by-4.
|
||||
On Urukul boards with CPLD gateware before v1.3.1 only the default
|
||||
(0, i.e. variant dependent divider) is valid.
|
||||
:param sync_sel: SYNC (multi-chip synchronisation) signal source selection.
|
||||
0 corresponds to SYNC_IN being supplied by the FPGA via the EEM
|
||||
connector. 1 corresponds to SYNC_OUT from DDS0 being distributed to the
|
||||
other chips.
|
||||
:param clk_sel: Reference clock selection. 0 corresponds to the internal
|
||||
MMCX or ob-board XO clock. 1 corresponds to the front panel SMA.
|
||||
:param sync_sel: SYNC clock selection. 0 corresponds to SYNC clock over EEM
|
||||
from FPGA. 1 corresponds to SYNC clock from DDS0.
|
||||
:param rf_sw: Initial CPLD RF switch register setting (default: 0x0).
|
||||
Knowledge of this state is not transferred between experiments.
|
||||
:param att: Initial attenuator setting shift register (default:
|
||||
0x00000000). See also :meth:`get_att_mu` which retrieves the hardware
|
||||
state without side effects. Knowledge of this state is not transferred
|
||||
between experiments.
|
||||
:param sync_div: SYNC_IN generator divider. The ratio between the coarse
|
||||
RTIO frequency and the SYNC_IN generator frequency (default: 2 if
|
||||
`sync_device` was specified).
|
||||
0x00000000). See also: :meth:`set_all_att_mu`. Knowledge of this state
|
||||
is not transferred between experiments.
|
||||
:param core_device: Core device name
|
||||
|
||||
If the clocking is incorrect (for example, setting ``clk_sel`` to the
|
||||
front panel SMA with no clock connected), then the ``init()`` method of
|
||||
the DDS channels can fail with the error message ``PLL lock timeout``.
|
||||
"""
|
||||
kernel_invariants = {"refclk", "bus", "core", "io_update", "clk_div"}
|
||||
kernel_invariants = {"refclk", "bus", "core", "io_update"}
|
||||
|
||||
def __init__(self, dmgr, spi_device, io_update_device=None,
|
||||
dds_reset_device=None, sync_device=None,
|
||||
sync_sel=0, clk_sel=0, clk_div=0, rf_sw=0,
|
||||
refclk=125e6, att=0x00000000, sync_div=None,
|
||||
core_device="core"):
|
||||
dds_reset_device=None, sync_sel=0, clk_sel=0, rf_sw=0,
|
||||
refclk=125e6, att=0x00000000, core_device="core"):
|
||||
|
||||
self.core = dmgr.get(core_device)
|
||||
self.core = dmgr.get(core_device)
|
||||
self.refclk = refclk
|
||||
assert 0 <= clk_div <= 3
|
||||
self.clk_div = clk_div
|
||||
|
||||
self.bus = dmgr.get(spi_device)
|
||||
if io_update_device is not None:
|
||||
|
|
@ -182,38 +142,28 @@ class CPLD:
|
|||
self.io_update = _RegIOUpdate(self)
|
||||
if dds_reset_device is not None:
|
||||
self.dds_reset = dmgr.get(dds_reset_device)
|
||||
if sync_device is not None:
|
||||
self.sync = dmgr.get(sync_device)
|
||||
if sync_div is None:
|
||||
sync_div = 2
|
||||
else:
|
||||
self.sync = _DummySync(self)
|
||||
assert sync_div is None
|
||||
sync_div = 0
|
||||
|
||||
self.cfg_reg = urukul_cfg(rf_sw=rf_sw, led=0, profile=DEFAULT_PROFILE,
|
||||
io_update=0, mask_nu=0, clk_sel=clk_sel,
|
||||
sync_sel=sync_sel,
|
||||
rst=0, io_rst=0, clk_div=clk_div)
|
||||
self.att_reg = int32(int64(att))
|
||||
self.sync_div = sync_div
|
||||
self.cfg_reg = urukul_cfg(rf_sw=rf_sw, led=0, profile=0,
|
||||
io_update=0, mask_nu=0, clk_sel=clk_sel,
|
||||
sync_sel=sync_sel, rst=0, io_rst=0)
|
||||
self.att_reg = att
|
||||
|
||||
@kernel
|
||||
def cfg_write(self, cfg: TInt32):
|
||||
def cfg_write(self, cfg):
|
||||
"""Write to the configuration register.
|
||||
|
||||
See :func:`urukul_cfg` for possible flags.
|
||||
|
||||
:param cfg: 24 bit data to be written. Will be stored at
|
||||
:param data: 24 bit data to be written. Will be stored at
|
||||
:attr:`cfg_reg`.
|
||||
"""
|
||||
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 24,
|
||||
SPIT_CFG_WR, CS_CFG)
|
||||
SPIT_CFG_WR, CS_CFG)
|
||||
self.bus.write(cfg << 8)
|
||||
self.cfg_reg = cfg
|
||||
|
||||
@kernel
|
||||
def sta_read(self) -> TInt32:
|
||||
def sta_read(self):
|
||||
"""Read the status register.
|
||||
|
||||
Use any of the following functions to extract values:
|
||||
|
|
@ -227,12 +177,12 @@ class CPLD:
|
|||
:return: The status register value.
|
||||
"""
|
||||
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, 24,
|
||||
SPIT_CFG_RD, CS_CFG)
|
||||
SPIT_CFG_RD, CS_CFG)
|
||||
self.bus.write(self.cfg_reg << 8)
|
||||
return self.bus.read()
|
||||
|
||||
@kernel
|
||||
def init(self, blind: TBool = False):
|
||||
def init(self, blind=False):
|
||||
"""Initialize and detect Urukul.
|
||||
|
||||
Resets the DDS I/O interface and verifies correct CPLD gateware
|
||||
|
|
@ -250,12 +200,9 @@ class CPLD:
|
|||
proto_rev = urukul_sta_proto_rev(self.sta_read())
|
||||
if proto_rev != STA_PROTO_REV_MATCH:
|
||||
raise ValueError("Urukul proto_rev mismatch")
|
||||
delay(100 * us) # reset, slack
|
||||
delay(100*us) # reset, slack
|
||||
self.cfg_write(cfg)
|
||||
if self.sync_div:
|
||||
at_mu(now_mu() & ~0xf) # align to RTIO/2
|
||||
self.set_sync_div(self.sync_div) # 125 MHz/2 = 1 GHz/16
|
||||
delay(1 * ms) # DDS wake up
|
||||
delay(1*ms) # DDS wake up
|
||||
|
||||
@kernel
|
||||
def io_rst(self):
|
||||
|
|
@ -264,7 +211,7 @@ class CPLD:
|
|||
self.cfg_write(self.cfg_reg & ~(1 << CFG_IO_RST))
|
||||
|
||||
@kernel
|
||||
def cfg_sw(self, channel: TInt32, on: TBool):
|
||||
def cfg_sw(self, channel, on):
|
||||
"""Configure the RF switches through the configuration register.
|
||||
|
||||
These values are logically OR-ed with the LVDS lines on EEM1.
|
||||
|
|
@ -280,44 +227,13 @@ class CPLD:
|
|||
self.cfg_write(c)
|
||||
|
||||
@kernel
|
||||
def cfg_switches(self, state: TInt32):
|
||||
"""Configure all four RF switches through the configuration register.
|
||||
|
||||
:param state: RF switch state as a 4 bit integer.
|
||||
"""
|
||||
self.cfg_write((self.cfg_reg & ~0xf) | state)
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def mu_to_att(self, att_mu: TInt32) -> TFloat:
|
||||
"""Convert a digital attenuation setting to dB.
|
||||
|
||||
:param att_mu: Digital attenuation setting.
|
||||
:return: Attenuation setting in dB.
|
||||
"""
|
||||
return (255 - (att_mu & 0xff)) / 8
|
||||
|
||||
@portable(flags={"fast-math"})
|
||||
def att_to_mu(self, att: TFloat) -> TInt32:
|
||||
"""Convert an attenuation setting in dB to machine units.
|
||||
|
||||
:param att: Attenuation setting in dB.
|
||||
:return: Digital attenuation setting.
|
||||
"""
|
||||
code = int32(255) - int32(round(att * 8))
|
||||
if code < 0 or code > 255:
|
||||
raise ValueError("Invalid urukul.CPLD attenuation!")
|
||||
return code
|
||||
|
||||
@kernel
|
||||
def set_att_mu(self, channel: TInt32, att: TInt32):
|
||||
def set_att_mu(self, channel, att):
|
||||
"""Set digital step attenuator in machine units.
|
||||
|
||||
This method will also write the attenuator settings of the three
|
||||
other channels. Use :meth:`get_att_mu` to retrieve the hardware
|
||||
state set in previous experiments.
|
||||
This method will write the attenuator settings of all four channels.
|
||||
|
||||
:param channel: Attenuator channel (0-3).
|
||||
:param att: 8-bit digital attenuation setting:
|
||||
:param att: Digital attenuation setting:
|
||||
255 minimum attenuation, 0 maximum attenuation (31.5 dB)
|
||||
"""
|
||||
a = self.att_reg & ~(0xff << (channel * 8))
|
||||
|
|
@ -325,7 +241,7 @@ class CPLD:
|
|||
self.set_all_att_mu(a)
|
||||
|
||||
@kernel
|
||||
def set_all_att_mu(self, att_reg: TInt32):
|
||||
def set_all_att_mu(self, att_reg):
|
||||
"""Set all four digital step attenuators (in machine units).
|
||||
|
||||
.. seealso:: :meth:`set_att_mu`
|
||||
|
|
@ -333,99 +249,30 @@ class CPLD:
|
|||
:param att_reg: Attenuator setting string (32 bit)
|
||||
"""
|
||||
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 32,
|
||||
SPIT_ATT_WR, CS_ATT)
|
||||
SPIT_ATT_WR, CS_ATT)
|
||||
self.bus.write(att_reg)
|
||||
self.att_reg = att_reg
|
||||
|
||||
@kernel
|
||||
def set_att(self, channel: TInt32, att: TFloat):
|
||||
def set_att(self, channel, att):
|
||||
"""Set digital step attenuator in SI units.
|
||||
|
||||
This method will write the attenuator settings of all four channels.
|
||||
|
||||
.. seealso:: :meth:`set_att_mu`
|
||||
|
||||
:param channel: Attenuator channel (0-3).
|
||||
:param att: Attenuation setting in dB. Higher value is more
|
||||
attenuation. Minimum attenuation is 0*dB, maximum attenuation is
|
||||
31.5*dB.
|
||||
attenuation.
|
||||
"""
|
||||
self.set_att_mu(channel, self.att_to_mu(att))
|
||||
self.set_att_mu(channel, 255 - int32(round(att*8)))
|
||||
|
||||
@kernel
|
||||
def get_att_mu(self) -> TInt32:
|
||||
def get_att_mu(self):
|
||||
"""Return the digital step attenuator settings in machine units.
|
||||
|
||||
The result is stored and will be used in future calls of
|
||||
:meth:`set_att_mu` and :meth:`set_att`.
|
||||
|
||||
.. seealso:: :meth:`get_channel_att_mu`
|
||||
This method will also (as a side effect) write the attenuator
|
||||
settings of all four channels.
|
||||
|
||||
:return: 32 bit attenuator settings
|
||||
"""
|
||||
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_INPUT, 32,
|
||||
SPIT_ATT_RD, CS_ATT)
|
||||
self.bus.write(0) # shift in zeros, shift out current value
|
||||
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 32,
|
||||
SPIT_ATT_WR, CS_ATT)
|
||||
delay(10 * us)
|
||||
self.att_reg = self.bus.read()
|
||||
self.bus.write(self.att_reg) # shift in current value again and latch
|
||||
return self.att_reg
|
||||
|
||||
@kernel
|
||||
def get_channel_att_mu(self, channel: TInt32) -> TInt32:
|
||||
"""Get digital step attenuator value for a channel in machine units.
|
||||
|
||||
The result is stored and will be used in future calls of
|
||||
:meth:`set_att_mu` and :meth:`set_att`.
|
||||
|
||||
.. seealso:: :meth:`get_att_mu`
|
||||
|
||||
:param channel: Attenuator channel (0-3).
|
||||
:return: 8-bit digital attenuation setting:
|
||||
255 minimum attenuation, 0 maximum attenuation (31.5 dB)
|
||||
"""
|
||||
return int32((self.get_att_mu() >> (channel * 8)) & 0xff)
|
||||
|
||||
@kernel
|
||||
def get_channel_att(self, channel: TInt32) -> TFloat:
|
||||
"""Get digital step attenuator value for a channel in SI units.
|
||||
|
||||
.. seealso:: :meth:`get_channel_att_mu`
|
||||
|
||||
:param channel: Attenuator channel (0-3).
|
||||
:return: Attenuation setting in dB. Higher value is more
|
||||
attenuation. Minimum attenuation is 0*dB, maximum attenuation is
|
||||
31.5*dB.
|
||||
"""
|
||||
return self.mu_to_att(self.get_channel_att_mu(channel))
|
||||
|
||||
@kernel
|
||||
def set_sync_div(self, div: TInt32):
|
||||
"""Set the SYNC_IN AD9910 pulse generator frequency
|
||||
and align it to the current RTIO timestamp.
|
||||
|
||||
The SYNC_IN signal is derived from the coarse RTIO clock
|
||||
and the divider must be a power of two.
|
||||
Configure ``sync_sel == 0``.
|
||||
|
||||
:param div: SYNC_IN frequency divider. Must be a power of two.
|
||||
Minimum division ratio is 2. Maximum division ratio is 16.
|
||||
"""
|
||||
ftw_max = 1 << 4
|
||||
ftw = ftw_max // div
|
||||
assert ftw * div == ftw_max
|
||||
self.sync.set_mu(ftw)
|
||||
|
||||
@kernel
|
||||
def set_profile(self, profile: TInt32):
|
||||
"""Set the PROFILE pins.
|
||||
|
||||
The PROFILE pins are common to all four DDS channels.
|
||||
|
||||
:param profile: PROFILE pins in numeric representation (0-7).
|
||||
"""
|
||||
cfg = self.cfg_reg & ~(7 << CFG_PROFILE)
|
||||
cfg |= (profile & 7) << CFG_PROFILE
|
||||
self.cfg_write(cfg)
|
||||
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, 32,
|
||||
SPIT_ATT_RD, CS_ATT)
|
||||
self.bus.write(self.att_reg)
|
||||
return self.bus.read()
|
||||
|
|
|
|||
|
|
@ -27,15 +27,15 @@ class Zotino(AD53xx):
|
|||
:param clr_device: CLR RTIO TTLOut channel name.
|
||||
:param div_write: SPI clock divider for write operations (default: 4,
|
||||
50MHz max SPI clock)
|
||||
:param div_read: SPI clock divider for read operations (default: 16, not
|
||||
optimized for speed; datasheet says t22: 25ns min SCLK edge to SDO
|
||||
valid, and suggests the SPI speed for reads should be <=20 MHz)
|
||||
:param div_read: SPI clock divider for read operations (default: 8, not
|
||||
optimized for speed, but cf data sheet t22: 25ns min SCLK edge to SDO
|
||||
valid)
|
||||
:param vref: DAC reference voltage (default: 5.)
|
||||
:param core_device: Core device name (default: "core")
|
||||
"""
|
||||
|
||||
def __init__(self, dmgr, spi_device, ldac_device=None, clr_device=None,
|
||||
div_write=4, div_read=16, vref=5., core="core"):
|
||||
div_write=4, div_read=8, vref=5., core="core"):
|
||||
AD53xx.__init__(self, dmgr=dmgr, spi_device=spi_device,
|
||||
ldac_device=ldac_device, clr_device=clr_device,
|
||||
chip_select=_SPI_CS_DAC, div_write=div_write,
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
import asyncio
|
||||
import logging
|
||||
|
||||
from PyQt5 import QtCore, QtWidgets
|
||||
|
|
@ -45,7 +44,6 @@ class AppletsCCBDock(applets.AppletsDock):
|
|||
self.ccbp_group_action.setMenu(ccbp_group_menu)
|
||||
self.table.addAction(self.ccbp_group_action)
|
||||
self.table.itemSelectionChanged.connect(self.update_group_ccbp_menu)
|
||||
self.update_group_ccbp_menu()
|
||||
|
||||
ccbp_global_menu = QtWidgets.QMenu()
|
||||
actiongroup = QtWidgets.QActionGroup(self.table)
|
||||
|
|
@ -151,16 +149,15 @@ class AppletsCCBDock(applets.AppletsDock):
|
|||
corresponds to a single group. If ``group`` is ``None`` or an empty
|
||||
list, it corresponds to the root.
|
||||
|
||||
``command`` gives the command line used to run the applet, as if it was
|
||||
started from a shell. The dashboard substitutes variables such as
|
||||
``$python`` that gives the complete file name of the Python interpreter
|
||||
running the dashboard.
|
||||
``command`` gives the command line used to run the applet, as if it
|
||||
was started from a shell. The dashboard substitutes variables such as
|
||||
``$python`` that gives the complete file name of the Python
|
||||
interpreter running the dashboard.
|
||||
|
||||
If the name already exists (after following any specified groups), the
|
||||
command or code of the existing applet with that name is replaced, and
|
||||
the applet is restarted and shown at its previous position. If not, a
|
||||
new applet entry is created and the applet is shown at any position on
|
||||
the screen.
|
||||
the applet is shown at its previous position. If not, a new applet
|
||||
entry is created and the applet is shown at any position on the screen.
|
||||
|
||||
If the group(s) do not exist, they are created.
|
||||
|
||||
|
|
@ -184,17 +181,9 @@ class AppletsCCBDock(applets.AppletsDock):
|
|||
else:
|
||||
spec = {"ty": "code", "code": code, "command": command}
|
||||
if applet is None:
|
||||
logger.debug("Applet %s does not exist: creating", name)
|
||||
applet = self.new(name=name, spec=spec, parent=parent)
|
||||
else:
|
||||
if spec != self.get_spec(applet):
|
||||
logger.debug("Applet %s already exists: updating existing spec", name)
|
||||
self.set_spec(applet, spec)
|
||||
if applet.applet_dock:
|
||||
asyncio.ensure_future(applet.applet_dock.restart())
|
||||
else:
|
||||
logger.debug("Applet %s already exists and no update required", name)
|
||||
|
||||
self.set_spec(applet, spec)
|
||||
if ccbp == "enable":
|
||||
applet.setCheckState(0, QtCore.Qt.Checked)
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,8 @@ import logging
|
|||
|
||||
import numpy as np
|
||||
from PyQt5 import QtCore, QtWidgets
|
||||
from sipyco import pyon
|
||||
|
||||
from artiq.tools import scale_from_metadata, short_format, exc_to_warning
|
||||
from artiq.tools import short_format
|
||||
from artiq.gui.tools import LayoutWidget, QRecursiveFilterProxyModel
|
||||
from artiq.gui.models import DictSyncTreeSepModel
|
||||
from artiq.gui.scientific_spinbox import ScientificSpinBox
|
||||
|
|
@ -14,152 +13,73 @@ from artiq.gui.scientific_spinbox import ScientificSpinBox
|
|||
logger = logging.getLogger(__name__)
|
||||
|
||||
|
||||
async def rename(key, new_key, value, metadata, persist, dataset_ctl):
|
||||
if key != new_key:
|
||||
await dataset_ctl.delete(key)
|
||||
await dataset_ctl.set(new_key, value, metadata=metadata, persist=persist)
|
||||
|
||||
|
||||
class CreateEditDialog(QtWidgets.QDialog):
|
||||
def __init__(self, parent, dataset_ctl, key=None, value=None, metadata=None, persist=False):
|
||||
class Editor(QtWidgets.QDialog):
|
||||
def __init__(self, parent, dataset_ctl, key, value):
|
||||
QtWidgets.QDialog.__init__(self, parent=parent)
|
||||
self.dataset_ctl = dataset_ctl
|
||||
self.key = key
|
||||
self.initial_type = type(value)
|
||||
|
||||
self.setWindowTitle("Create dataset" if key is None else "Edit dataset")
|
||||
self.setWindowTitle("Edit dataset")
|
||||
grid = QtWidgets.QGridLayout()
|
||||
grid.setRowMinimumHeight(1, 40)
|
||||
grid.setColumnMinimumWidth(2, 60)
|
||||
self.setLayout(grid)
|
||||
|
||||
grid.addWidget(QtWidgets.QLabel("Name:"), 0, 0)
|
||||
self.name_widget = QtWidgets.QLineEdit()
|
||||
grid.addWidget(self.name_widget, 0, 1)
|
||||
grid.addWidget(QtWidgets.QLabel(key), 0, 1)
|
||||
|
||||
grid.addWidget(QtWidgets.QLabel("Value:"), 1, 0)
|
||||
self.value_widget = QtWidgets.QLineEdit()
|
||||
self.value_widget.setPlaceholderText('PYON (Python)')
|
||||
grid.addWidget(self.value_widget, 1, 1)
|
||||
self.data_type = QtWidgets.QLabel("data type")
|
||||
grid.addWidget(self.data_type, 1, 2)
|
||||
self.value_widget.textChanged.connect(self.dtype)
|
||||
grid.addWidget(self.get_edit_widget(value), 1, 1)
|
||||
|
||||
grid.addWidget(QtWidgets.QLabel("Unit:"), 2, 0)
|
||||
self.unit_widget = QtWidgets.QLineEdit()
|
||||
grid.addWidget(self.unit_widget, 2, 1)
|
||||
|
||||
grid.addWidget(QtWidgets.QLabel("Scale:"), 3, 0)
|
||||
self.scale_widget = QtWidgets.QLineEdit()
|
||||
grid.addWidget(self.scale_widget, 3, 1)
|
||||
|
||||
grid.addWidget(QtWidgets.QLabel("Precision:"), 4, 0)
|
||||
self.precision_widget = QtWidgets.QLineEdit()
|
||||
grid.addWidget(self.precision_widget, 4, 1)
|
||||
|
||||
grid.addWidget(QtWidgets.QLabel("Persist:"), 5, 0)
|
||||
self.box_widget = QtWidgets.QCheckBox()
|
||||
grid.addWidget(self.box_widget, 5, 1)
|
||||
|
||||
self.ok = QtWidgets.QPushButton('&Ok')
|
||||
self.ok.setEnabled(False)
|
||||
self.cancel = QtWidgets.QPushButton('&Cancel')
|
||||
self.buttons = QtWidgets.QDialogButtonBox(self)
|
||||
self.buttons.addButton(
|
||||
self.ok, QtWidgets.QDialogButtonBox.AcceptRole)
|
||||
self.buttons.addButton(
|
||||
self.cancel, QtWidgets.QDialogButtonBox.RejectRole)
|
||||
grid.setRowStretch(6, 1)
|
||||
grid.addWidget(self.buttons, 7, 0, 1, 3, alignment=QtCore.Qt.AlignHCenter)
|
||||
self.buttons.accepted.connect(self.accept)
|
||||
self.buttons.rejected.connect(self.reject)
|
||||
|
||||
self.key = key
|
||||
self.name_widget.setText(key)
|
||||
|
||||
value_edit_string = self.value_to_edit_string(value)
|
||||
if metadata is not None:
|
||||
scale = scale_from_metadata(metadata)
|
||||
t = value.dtype if value is np.ndarray else type(value)
|
||||
if scale != 1 and np.issubdtype(t, np.number):
|
||||
# degenerates to float type
|
||||
value_edit_string = self.value_to_edit_string(
|
||||
np.float64(value / scale))
|
||||
self.unit_widget.setText(metadata.get('unit', ''))
|
||||
self.scale_widget.setText(str(metadata.get('scale', '')))
|
||||
self.precision_widget.setText(str(metadata.get('precision', '')))
|
||||
|
||||
self.value_widget.setText(value_edit_string)
|
||||
self.box_widget.setChecked(persist)
|
||||
buttons = QtWidgets.QDialogButtonBox(
|
||||
QtWidgets.QDialogButtonBox.Ok | QtWidgets.QDialogButtonBox.Cancel)
|
||||
grid.setRowStretch(2, 1)
|
||||
grid.addWidget(buttons, 3, 0, 1, 2)
|
||||
buttons.accepted.connect(self.accept)
|
||||
buttons.rejected.connect(self.reject)
|
||||
|
||||
def accept(self):
|
||||
key = self.name_widget.text()
|
||||
value = self.value_widget.text()
|
||||
persist = self.box_widget.isChecked()
|
||||
unit = self.unit_widget.text()
|
||||
scale = self.scale_widget.text()
|
||||
precision = self.precision_widget.text()
|
||||
metadata = {}
|
||||
if unit != "":
|
||||
metadata['unit'] = unit
|
||||
if scale != "":
|
||||
metadata['scale'] = float(scale)
|
||||
if precision != "":
|
||||
metadata['precision'] = int(precision)
|
||||
scale = scale_from_metadata(metadata)
|
||||
value = self.parse_edit_string(value)
|
||||
t = value.dtype if value is np.ndarray else type(value)
|
||||
if scale != 1 and np.issubdtype(t, np.number):
|
||||
# degenerates to float type
|
||||
value = np.float64(value * scale)
|
||||
if self.key and self.key != key:
|
||||
asyncio.ensure_future(exc_to_warning(rename(self.key, key, value, metadata, persist, self.dataset_ctl)))
|
||||
else:
|
||||
asyncio.ensure_future(exc_to_warning(self.dataset_ctl.set(key, value, metadata=metadata, persist=persist)))
|
||||
self.key = key
|
||||
value = self.initial_type(self.get_edit_widget_value())
|
||||
asyncio.ensure_future(self.dataset_ctl.set(self.key, value))
|
||||
QtWidgets.QDialog.accept(self)
|
||||
|
||||
def dtype(self):
|
||||
txt = self.value_widget.text()
|
||||
try:
|
||||
result = self.parse_edit_string(txt)
|
||||
# ensure only pyon compatible types are permissable
|
||||
pyon.encode(result)
|
||||
except:
|
||||
pixmap = self.style().standardPixmap(
|
||||
QtWidgets.QStyle.SP_MessageBoxWarning)
|
||||
self.data_type.setPixmap(pixmap)
|
||||
self.ok.setEnabled(False)
|
||||
else:
|
||||
self.data_type.setText(type(result).__name__)
|
||||
self.ok.setEnabled(True)
|
||||
def get_edit_widget(self, initial_value):
|
||||
raise NotImplementedError
|
||||
|
||||
@staticmethod
|
||||
def parse_edit_string(s):
|
||||
if s == "":
|
||||
raise TypeError
|
||||
_eval_dict = {
|
||||
"__builtins__": {},
|
||||
"array": np.array,
|
||||
"null": np.nan,
|
||||
"inf": np.inf
|
||||
}
|
||||
for t_ in pyon._numpy_scalar:
|
||||
_eval_dict[t_] = eval("np.{}".format(t_), {"np": np})
|
||||
return eval(s, _eval_dict, {})
|
||||
def get_edit_widget_value(self):
|
||||
raise NotImplementedError
|
||||
|
||||
@staticmethod
|
||||
def value_to_edit_string(v):
|
||||
t = type(v)
|
||||
r = ""
|
||||
if isinstance(v, np.generic):
|
||||
r += t.__name__
|
||||
r += "("
|
||||
r += repr(v)
|
||||
r += ")"
|
||||
elif v is None:
|
||||
return r
|
||||
else:
|
||||
r += repr(v)
|
||||
return r
|
||||
|
||||
class NumberEditor(Editor):
|
||||
def get_edit_widget(self, initial_value):
|
||||
self.edit_widget = ScientificSpinBox()
|
||||
self.edit_widget.setDecimals(13)
|
||||
self.edit_widget.setPrecision()
|
||||
self.edit_widget.setRelativeStep()
|
||||
self.edit_widget.setValue(float(initial_value))
|
||||
return self.edit_widget
|
||||
|
||||
def get_edit_widget_value(self):
|
||||
return self.edit_widget.value()
|
||||
|
||||
|
||||
class BoolEditor(Editor):
|
||||
def get_edit_widget(self, initial_value):
|
||||
self.edit_widget = QtWidgets.QCheckBox()
|
||||
self.edit_widget.setChecked(bool(initial_value))
|
||||
return self.edit_widget
|
||||
|
||||
def get_edit_widget_value(self):
|
||||
return self.edit_widget.isChecked()
|
||||
|
||||
|
||||
class StringEditor(Editor):
|
||||
def get_edit_widget(self, initial_value):
|
||||
self.edit_widget = QtWidgets.QLineEdit()
|
||||
self.edit_widget.setText(initial_value)
|
||||
return self.edit_widget
|
||||
|
||||
def get_edit_widget_value(self):
|
||||
return self.edit_widget.text()
|
||||
|
||||
|
||||
class Model(DictSyncTreeSepModel):
|
||||
|
|
@ -172,13 +92,13 @@ class Model(DictSyncTreeSepModel):
|
|||
if column == 1:
|
||||
return "Y" if v[0] else "N"
|
||||
elif column == 2:
|
||||
return short_format(v[1], v[2])
|
||||
return short_format(v[1])
|
||||
else:
|
||||
raise ValueError
|
||||
|
||||
|
||||
class DatasetsDock(QtWidgets.QDockWidget):
|
||||
def __init__(self, dataset_sub, dataset_ctl):
|
||||
def __init__(self, datasets_sub, dataset_ctl):
|
||||
QtWidgets.QDockWidget.__init__(self, "Datasets")
|
||||
self.setObjectName("Datasets")
|
||||
self.setFeatures(QtWidgets.QDockWidget.DockWidgetMovable |
|
||||
|
|
@ -200,11 +120,6 @@ class DatasetsDock(QtWidgets.QDockWidget):
|
|||
grid.addWidget(self.table, 1, 0)
|
||||
|
||||
self.table.setContextMenuPolicy(QtCore.Qt.ActionsContextMenu)
|
||||
create_action = QtWidgets.QAction("New dataset", self.table)
|
||||
create_action.triggered.connect(self.create_clicked)
|
||||
create_action.setShortcut("CTRL+N")
|
||||
create_action.setShortcutContext(QtCore.Qt.WidgetShortcut)
|
||||
self.table.addAction(create_action)
|
||||
edit_action = QtWidgets.QAction("Edit dataset", self.table)
|
||||
edit_action.triggered.connect(self.edit_clicked)
|
||||
edit_action.setShortcut("RETURN")
|
||||
|
|
@ -218,7 +133,7 @@ class DatasetsDock(QtWidgets.QDockWidget):
|
|||
self.table.addAction(delete_action)
|
||||
|
||||
self.table_model = Model(dict())
|
||||
dataset_sub.add_setmodel_callback(self.set_model)
|
||||
datasets_sub.add_setmodel_callback(self.set_model)
|
||||
|
||||
def _search_datasets(self):
|
||||
if hasattr(self, "table_model_filter"):
|
||||
|
|
@ -231,17 +146,25 @@ class DatasetsDock(QtWidgets.QDockWidget):
|
|||
self.table_model_filter.setSourceModel(self.table_model)
|
||||
self.table.setModel(self.table_model_filter)
|
||||
|
||||
def create_clicked(self):
|
||||
CreateEditDialog(self, self.dataset_ctl).open()
|
||||
|
||||
def edit_clicked(self):
|
||||
idx = self.table.selectedIndexes()
|
||||
if idx:
|
||||
idx = self.table_model_filter.mapToSource(idx[0])
|
||||
key = self.table_model.index_to_key(idx)
|
||||
if key is not None:
|
||||
persist, value, metadata = self.table_model.backing_store[key]
|
||||
CreateEditDialog(self, self.dataset_ctl, key, value, metadata, persist).open()
|
||||
persist, value = self.table_model.backing_store[key]
|
||||
t = type(value)
|
||||
if np.issubdtype(t, np.number):
|
||||
dialog_cls = NumberEditor
|
||||
elif np.issubdtype(t, np.bool_):
|
||||
dialog_cls = BoolEditor
|
||||
elif np.issubdtype(t, np.unicode_):
|
||||
dialog_cls = StringEditor
|
||||
else:
|
||||
logger.error("Cannot edit dataset %s: "
|
||||
"type %s is not supported", key, t)
|
||||
return
|
||||
dialog_cls(self, self.dataset_ctl, key, value).open()
|
||||
|
||||
def delete_clicked(self):
|
||||
idx = self.table.selectedIndexes()
|
||||
|
|
|
|||
|
|
@ -7,13 +7,9 @@ from collections import OrderedDict
|
|||
from PyQt5 import QtCore, QtGui, QtWidgets
|
||||
import h5py
|
||||
|
||||
from sipyco import pyon
|
||||
|
||||
from artiq.gui.tools import LayoutWidget, log_level_to_name, get_open_file_name
|
||||
from artiq.gui.entries import procdesc_to_entry, ScanEntry
|
||||
from artiq.gui.fuzzy_select import FuzzySelectWidget
|
||||
from artiq.gui.tools import (LayoutWidget, WheelFilter,
|
||||
log_level_to_name, get_open_file_name)
|
||||
from artiq.tools import parse_devarg_override, unparse_devarg_override
|
||||
from artiq.protocols import pyon
|
||||
|
||||
|
||||
logger = logging.getLogger(__name__)
|
||||
|
|
@ -25,6 +21,15 @@ logger = logging.getLogger(__name__)
|
|||
# 2. file:<class name>@<file name>
|
||||
|
||||
|
||||
class _WheelFilter(QtCore.QObject):
|
||||
def eventFilter(self, obj, event):
|
||||
if (event.type() == QtCore.QEvent.Wheel and
|
||||
event.modifiers() != QtCore.Qt.NoModifier):
|
||||
event.ignore()
|
||||
return True
|
||||
return False
|
||||
|
||||
|
||||
class _ArgumentEditor(QtWidgets.QTreeWidget):
|
||||
def __init__(self, manager, dock, expurl):
|
||||
self.manager = manager
|
||||
|
|
@ -48,7 +53,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
|
|||
self.setStyleSheet("QTreeWidget {background: " +
|
||||
self.palette().midlight().color().name() + " ;}")
|
||||
|
||||
self.viewport().installEventFilter(WheelFilter(self.viewport(), True))
|
||||
self.viewport().installEventFilter(_WheelFilter(self.viewport()))
|
||||
|
||||
self._groups = dict()
|
||||
self._arg_to_widgets = dict()
|
||||
|
|
@ -152,15 +157,31 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
|
|||
self._groups[name] = group
|
||||
return group
|
||||
|
||||
def update_argument(self, name, argument):
|
||||
widgets = self._arg_to_widgets[name]
|
||||
def _recompute_argument_clicked(self, name):
|
||||
asyncio.ensure_future(self._recompute_argument(name))
|
||||
|
||||
async def _recompute_argument(self, name):
|
||||
try:
|
||||
arginfo = await self.manager.compute_arginfo(self.expurl)
|
||||
except:
|
||||
logger.error("Could not recompute argument '%s' of '%s'",
|
||||
name, self.expurl, exc_info=True)
|
||||
return
|
||||
argument = self.manager.get_submission_arguments(self.expurl)[name]
|
||||
|
||||
procdesc = arginfo[name][0]
|
||||
state = procdesc_to_entry(procdesc).default_state(procdesc)
|
||||
argument["desc"] = procdesc
|
||||
argument["state"] = state
|
||||
|
||||
# Qt needs a setItemWidget() to handle layout correctly,
|
||||
# simply replacing the entry inside the LayoutWidget
|
||||
# results in a bug.
|
||||
|
||||
widgets = self._arg_to_widgets[name]
|
||||
|
||||
widgets["entry"].deleteLater()
|
||||
widgets["entry"] = procdesc_to_entry(argument["desc"])(argument)
|
||||
widgets["entry"] = procdesc_to_entry(procdesc)(argument)
|
||||
widgets["disable_other_scans"].setVisible(
|
||||
isinstance(widgets["entry"], ScanEntry))
|
||||
widgets["fix_layout"].deleteLater()
|
||||
|
|
@ -169,24 +190,6 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
|
|||
self.setItemWidget(widgets["widget_item"], 1, widgets["fix_layout"])
|
||||
self.updateGeometries()
|
||||
|
||||
def _recompute_argument_clicked(self, name):
|
||||
asyncio.ensure_future(self._recompute_argument(name))
|
||||
|
||||
async def _recompute_argument(self, name):
|
||||
try:
|
||||
expdesc, _ = await self.manager.compute_expdesc(self.expurl)
|
||||
except:
|
||||
logger.error("Could not recompute argument '%s' of '%s'",
|
||||
name, self.expurl, exc_info=True)
|
||||
return
|
||||
argument = self.manager.get_submission_arguments(self.expurl)[name]
|
||||
|
||||
procdesc = expdesc["arginfo"][name][0]
|
||||
state = procdesc_to_entry(procdesc).default_state(procdesc)
|
||||
argument["desc"] = procdesc
|
||||
argument["state"] = state
|
||||
self.update_argument(name, argument)
|
||||
|
||||
def _disable_other_scans(self, current_name):
|
||||
for name, widgets in self._arg_to_widgets.items():
|
||||
if (name != current_name
|
||||
|
|
@ -211,15 +214,6 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
|
|||
pass
|
||||
self.verticalScrollBar().setValue(state["scroll"])
|
||||
|
||||
# Hooks that allow user-supplied argument editors to react to imminent user
|
||||
# actions. Here, we always keep the manager-stored submission arguments
|
||||
# up-to-date, so no further action is required.
|
||||
def about_to_submit(self):
|
||||
pass
|
||||
|
||||
def about_to_close(self):
|
||||
pass
|
||||
|
||||
|
||||
log_levels = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"]
|
||||
|
||||
|
|
@ -245,8 +239,7 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
self.manager = manager
|
||||
self.expurl = expurl
|
||||
|
||||
editor_class = self.manager.get_argument_editor_class(expurl)
|
||||
self.argeditor = editor_class(self.manager, self, self.expurl)
|
||||
self.argeditor = _ArgumentEditor(self.manager, self, self.expurl)
|
||||
self.layout.addWidget(self.argeditor, 0, 0, 1, 5)
|
||||
self.layout.setRowStretch(0, 1)
|
||||
|
||||
|
|
@ -263,7 +256,7 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
datetime.setDate(QtCore.QDate.currentDate())
|
||||
else:
|
||||
datetime.setDateTime(QtCore.QDateTime.fromMSecsSinceEpoch(
|
||||
int(scheduling["due_date"]*1000)))
|
||||
scheduling["due_date"]*1000))
|
||||
datetime_en.setChecked(scheduling["due_date"] is not None)
|
||||
|
||||
def update_datetime(dt):
|
||||
|
|
@ -279,8 +272,7 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
scheduling["due_date"] = due_date
|
||||
datetime_en.stateChanged.connect(update_datetime_en)
|
||||
|
||||
self.pipeline_name = QtWidgets.QLineEdit()
|
||||
pipeline_name = self.pipeline_name
|
||||
pipeline_name = QtWidgets.QLineEdit()
|
||||
self.layout.addWidget(QtWidgets.QLabel("Pipeline:"), 1, 2)
|
||||
self.layout.addWidget(pipeline_name, 1, 3)
|
||||
|
||||
|
|
@ -288,10 +280,9 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
|
||||
def update_pipeline_name(text):
|
||||
scheduling["pipeline_name"] = text
|
||||
pipeline_name.textChanged.connect(update_pipeline_name)
|
||||
pipeline_name.textEdited.connect(update_pipeline_name)
|
||||
|
||||
self.priority = QtWidgets.QSpinBox()
|
||||
priority = self.priority
|
||||
priority = QtWidgets.QSpinBox()
|
||||
priority.setRange(-99, 99)
|
||||
self.layout.addWidget(QtWidgets.QLabel("Priority:"), 2, 0)
|
||||
self.layout.addWidget(priority, 2, 1)
|
||||
|
|
@ -302,11 +293,10 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
scheduling["priority"] = value
|
||||
priority.valueChanged.connect(update_priority)
|
||||
|
||||
self.flush = QtWidgets.QCheckBox("Flush")
|
||||
flush = self.flush
|
||||
flush = QtWidgets.QCheckBox("Flush")
|
||||
flush.setToolTip("Flush the pipeline (of current- and higher-priority "
|
||||
"experiments) before starting the experiment")
|
||||
self.layout.addWidget(flush, 2, 2)
|
||||
self.layout.addWidget(flush, 2, 2, 1, 2)
|
||||
|
||||
flush.setChecked(scheduling["flush"])
|
||||
|
||||
|
|
@ -314,20 +304,6 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
scheduling["flush"] = bool(checked)
|
||||
flush.stateChanged.connect(update_flush)
|
||||
|
||||
devarg_override = QtWidgets.QComboBox()
|
||||
devarg_override.setEditable(True)
|
||||
devarg_override.lineEdit().setPlaceholderText("Override device arguments")
|
||||
devarg_override.lineEdit().setClearButtonEnabled(True)
|
||||
devarg_override.insertItem(0, "core:analyze_at_run_end=True")
|
||||
self.layout.addWidget(devarg_override, 2, 3)
|
||||
|
||||
devarg_override.setCurrentText(options["devarg_override"])
|
||||
|
||||
def update_devarg_override(text):
|
||||
options["devarg_override"] = text
|
||||
devarg_override.editTextChanged.connect(update_devarg_override)
|
||||
self.devarg_override = devarg_override
|
||||
|
||||
log_level = QtWidgets.QComboBox()
|
||||
log_level.addItems(log_levels)
|
||||
log_level.setCurrentIndex(1)
|
||||
|
|
@ -348,7 +324,6 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
if "repo_rev" in options:
|
||||
repo_rev = QtWidgets.QLineEdit()
|
||||
repo_rev.setPlaceholderText("current")
|
||||
repo_rev.setClearButtonEnabled(True)
|
||||
repo_rev_label = QtWidgets.QLabel("Revision:")
|
||||
repo_rev_label.setToolTip("Experiment repository revision "
|
||||
"(commit ID) to use")
|
||||
|
|
@ -389,7 +364,6 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
self.hdf5_load_directory = os.path.expanduser("~")
|
||||
|
||||
def submit_clicked(self):
|
||||
self.argeditor.about_to_submit()
|
||||
try:
|
||||
self.manager.submit(self.expurl)
|
||||
except:
|
||||
|
|
@ -412,12 +386,11 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
|
||||
async def _recompute_arguments_task(self, overrides=dict()):
|
||||
try:
|
||||
expdesc, ui_name = await self.manager.compute_expdesc(self.expurl)
|
||||
arginfo = await self.manager.compute_arginfo(self.expurl)
|
||||
except:
|
||||
logger.error("Could not recompute experiment description of '%s'",
|
||||
logger.error("Could not recompute arguments of '%s'",
|
||||
self.expurl, exc_info=True)
|
||||
return
|
||||
arginfo = expdesc["arginfo"]
|
||||
for k, v in overrides.items():
|
||||
# Some values (e.g. scans) may have multiple defaults in a list
|
||||
if ("default" in arginfo[k][0]
|
||||
|
|
@ -425,38 +398,15 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
arginfo[k][0]["default"].insert(0, v)
|
||||
else:
|
||||
arginfo[k][0]["default"] = v
|
||||
self.manager.initialize_submission_arguments(self.expurl, arginfo, ui_name)
|
||||
self.manager.initialize_submission_arguments(self.expurl, arginfo)
|
||||
|
||||
argeditor_state = self.argeditor.save_state()
|
||||
self.argeditor.deleteLater()
|
||||
|
||||
editor_class = self.manager.get_argument_editor_class(self.expurl)
|
||||
self.argeditor = editor_class(self.manager, self, self.expurl)
|
||||
self.argeditor = _ArgumentEditor(self.manager, self, self.expurl)
|
||||
self.argeditor.restore_state(argeditor_state)
|
||||
self.layout.addWidget(self.argeditor, 0, 0, 1, 5)
|
||||
|
||||
def contextMenuEvent(self, event):
|
||||
menu = QtWidgets.QMenu(self)
|
||||
reset_sched = menu.addAction("Reset scheduler settings")
|
||||
action = menu.exec_(self.mapToGlobal(event.pos()))
|
||||
if action == reset_sched:
|
||||
asyncio.ensure_future(self._recompute_sched_options_task())
|
||||
|
||||
async def _recompute_sched_options_task(self):
|
||||
try:
|
||||
expdesc, _ = await self.manager.compute_expdesc(self.expurl)
|
||||
except:
|
||||
logger.error("Could not recompute experiment description of '%s'",
|
||||
self.expurl, exc_info=True)
|
||||
return
|
||||
sched_defaults = expdesc["scheduler_defaults"]
|
||||
|
||||
scheduling = self.manager.get_submission_scheduling(self.expurl)
|
||||
scheduling.update(sched_defaults)
|
||||
self.priority.setValue(scheduling["priority"])
|
||||
self.pipeline_name.setText(scheduling["pipeline_name"])
|
||||
self.flush.setChecked(scheduling["flush"])
|
||||
|
||||
def _load_hdf5_clicked(self):
|
||||
asyncio.ensure_future(self._load_hdf5_task())
|
||||
|
||||
|
|
@ -481,9 +431,6 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
return
|
||||
|
||||
try:
|
||||
if "devarg_override" in expid:
|
||||
self.devarg_override.setCurrentText(
|
||||
unparse_devarg_override(expid["devarg_override"]))
|
||||
self.log_level.setCurrentIndex(log_levels.index(
|
||||
log_level_to_name(expid["log_level"])))
|
||||
if ("repo_rev" in expid and
|
||||
|
|
@ -498,7 +445,6 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
await self._recompute_arguments_task(arguments)
|
||||
|
||||
def closeEvent(self, event):
|
||||
self.argeditor.about_to_close()
|
||||
self.sigClosed.emit()
|
||||
QtWidgets.QMdiSubWindow.closeEvent(self, event)
|
||||
|
||||
|
|
@ -515,68 +461,8 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
|
|||
self.hdf5_load_directory = state["hdf5_load_directory"]
|
||||
|
||||
|
||||
class _QuickOpenDialog(QtWidgets.QDialog):
|
||||
"""Modal dialog for opening/submitting experiments from a
|
||||
FuzzySelectWidget."""
|
||||
closed = QtCore.pyqtSignal()
|
||||
|
||||
def __init__(self, manager):
|
||||
super().__init__(manager.main_window)
|
||||
self.setModal(True)
|
||||
|
||||
self.manager = manager
|
||||
|
||||
self.setWindowTitle("Quick open...")
|
||||
|
||||
layout = QtWidgets.QGridLayout(self)
|
||||
layout.setSpacing(0)
|
||||
layout.setContentsMargins(0, 0, 0, 0)
|
||||
self.setLayout(layout)
|
||||
|
||||
# Find matching experiment names. Open experiments are preferred to
|
||||
# matches from the repository to ease quick window switching.
|
||||
open_exps = list(self.manager.open_experiments.keys())
|
||||
repo_exps = set("repo:" + k
|
||||
for k in self.manager.explist.keys()) - set(open_exps)
|
||||
choices = [(o, 100) for o in open_exps] + [(r, 0) for r in repo_exps]
|
||||
|
||||
self.select_widget = FuzzySelectWidget(choices)
|
||||
layout.addWidget(self.select_widget)
|
||||
self.select_widget.aborted.connect(self.close)
|
||||
self.select_widget.finished.connect(self._open_experiment)
|
||||
|
||||
font_metrics = QtGui.QFontMetrics(self.select_widget.line_edit.font())
|
||||
self.select_widget.setMinimumWidth(font_metrics.averageCharWidth() * 70)
|
||||
|
||||
def done(self, r):
|
||||
if self.select_widget:
|
||||
self.select_widget.abort()
|
||||
self.closed.emit()
|
||||
QtWidgets.QDialog.done(self, r)
|
||||
|
||||
def _open_experiment(self, exp_name, modifiers):
|
||||
if modifiers & QtCore.Qt.ControlModifier:
|
||||
try:
|
||||
self.manager.submit(exp_name)
|
||||
except:
|
||||
# Not all open_experiments necessarily still exist in the explist
|
||||
# (e.g. if the repository has been re-scanned since).
|
||||
logger.warning("failed to submit experiment '%s'",
|
||||
exp_name,
|
||||
exc_info=True)
|
||||
else:
|
||||
self.manager.open_experiment(exp_name)
|
||||
self.close()
|
||||
|
||||
|
||||
class ExperimentManager:
|
||||
#: Global registry for custom argument editor classes, indexed by the experiment
|
||||
#: `argument_ui` string; can be populated by dashboard plugins such as ndscan.
|
||||
#: If no handler for a requested UI name is found, the default built-in argument
|
||||
#: editor will be used.
|
||||
argument_ui_classes = dict()
|
||||
|
||||
def __init__(self, main_window, dataset_sub,
|
||||
def __init__(self, main_window,
|
||||
explist_sub, schedule_sub,
|
||||
schedule_ctl, experiment_db_ctl):
|
||||
self.main_window = main_window
|
||||
|
|
@ -587,10 +473,7 @@ class ExperimentManager:
|
|||
self.submission_scheduling = dict()
|
||||
self.submission_options = dict()
|
||||
self.submission_arguments = dict()
|
||||
self.argument_ui_names = dict()
|
||||
|
||||
self.datasets = dict()
|
||||
dataset_sub.add_setmodel_callback(self.set_dataset_model)
|
||||
self.explist = dict()
|
||||
explist_sub.add_setmodel_callback(self.set_explist_model)
|
||||
self.schedule = dict()
|
||||
|
|
@ -598,16 +481,6 @@ class ExperimentManager:
|
|||
|
||||
self.open_experiments = dict()
|
||||
|
||||
self.is_quick_open_shown = False
|
||||
quick_open_shortcut = QtWidgets.QShortcut(
|
||||
QtCore.Qt.CTRL + QtCore.Qt.Key_P,
|
||||
main_window)
|
||||
quick_open_shortcut.setContext(QtCore.Qt.ApplicationShortcut)
|
||||
quick_open_shortcut.activated.connect(self.show_quick_open)
|
||||
|
||||
def set_dataset_model(self, model):
|
||||
self.datasets = model
|
||||
|
||||
def set_explist_model(self, model):
|
||||
self.explist = model.backing_store
|
||||
|
||||
|
|
@ -624,17 +497,6 @@ class ExperimentManager:
|
|||
else:
|
||||
raise ValueError("Malformed experiment URL")
|
||||
|
||||
def get_argument_editor_class(self, expurl):
|
||||
ui_name = self.argument_ui_names.get(expurl, None)
|
||||
if not ui_name and expurl[:5] == "repo:":
|
||||
ui_name = self.explist.get(expurl[5:], {}).get("argument_ui", None)
|
||||
if ui_name:
|
||||
result = self.argument_ui_classes.get(ui_name, None)
|
||||
if result:
|
||||
return result
|
||||
logger.warning("Ignoring unknown argument UI '%s'", ui_name)
|
||||
return _ArgumentEditor
|
||||
|
||||
def get_submission_scheduling(self, expurl):
|
||||
if expurl in self.submission_scheduling:
|
||||
return self.submission_scheduling[expurl]
|
||||
|
|
@ -646,8 +508,6 @@ class ExperimentManager:
|
|||
"due_date": None,
|
||||
"flush": False
|
||||
}
|
||||
if expurl[:5] == "repo:":
|
||||
scheduling.update(self.explist[expurl[5:]]["scheduler_defaults"])
|
||||
self.submission_scheduling[expurl] = scheduling
|
||||
return scheduling
|
||||
|
||||
|
|
@ -657,15 +517,14 @@ class ExperimentManager:
|
|||
else:
|
||||
# mutated by _ExperimentDock
|
||||
options = {
|
||||
"log_level": logging.WARNING,
|
||||
"devarg_override": ""
|
||||
"log_level": logging.WARNING
|
||||
}
|
||||
if expurl[:5] == "repo:":
|
||||
options["repo_rev"] = None
|
||||
self.submission_options[expurl] = options
|
||||
return options
|
||||
|
||||
def initialize_submission_arguments(self, expurl, arginfo, ui_name):
|
||||
def initialize_submission_arguments(self, expurl, arginfo):
|
||||
arguments = OrderedDict()
|
||||
for name, (procdesc, group, tooltip) in arginfo.items():
|
||||
state = procdesc_to_entry(procdesc).default_state(procdesc)
|
||||
|
|
@ -676,22 +535,7 @@ class ExperimentManager:
|
|||
"state": state, # mutated by entries
|
||||
}
|
||||
self.submission_arguments[expurl] = arguments
|
||||
self.argument_ui_names[expurl] = ui_name
|
||||
return arguments
|
||||
|
||||
def set_argument_value(self, expurl, name, value):
|
||||
try:
|
||||
argument = self.submission_arguments[expurl][name]
|
||||
if argument["desc"]["ty"] == "Scannable":
|
||||
ty = value["ty"]
|
||||
argument["state"]["selected"] = ty
|
||||
argument["state"][ty] = value
|
||||
else:
|
||||
argument["state"] = value
|
||||
if expurl in self.open_experiments.keys():
|
||||
self.open_experiments[expurl].argeditor.update_argument(name, argument)
|
||||
except:
|
||||
logger.warn("Failed to set value for argument \"{}\" in experiment: {}.".format(name, expurl), exc_info=1)
|
||||
|
||||
def get_submission_arguments(self, expurl):
|
||||
if expurl in self.submission_arguments:
|
||||
|
|
@ -700,9 +544,9 @@ class ExperimentManager:
|
|||
if expurl[:5] != "repo:":
|
||||
raise ValueError("Submission arguments must be preinitialized "
|
||||
"when not using repository")
|
||||
class_desc = self.explist[expurl[5:]]
|
||||
return self.initialize_submission_arguments(expurl,
|
||||
class_desc["arginfo"], class_desc.get("argument_ui", None))
|
||||
arginfo = self.explist[expurl[5:]]["arginfo"]
|
||||
arguments = self.initialize_submission_arguments(expurl, arginfo)
|
||||
return arguments
|
||||
|
||||
def open_experiment(self, expurl):
|
||||
if expurl in self.open_experiments:
|
||||
|
|
@ -753,14 +597,7 @@ class ExperimentManager:
|
|||
entry_cls = procdesc_to_entry(argument["desc"])
|
||||
argument_values[name] = entry_cls.state_to_value(argument["state"])
|
||||
|
||||
try:
|
||||
devarg_override = parse_devarg_override(options["devarg_override"])
|
||||
except:
|
||||
logger.error("Failed to parse device argument overrides for %s", expurl)
|
||||
return
|
||||
|
||||
expid = {
|
||||
"devarg_override": devarg_override,
|
||||
"log_level": options["log_level"],
|
||||
"file": file,
|
||||
"class_name": class_name,
|
||||
|
|
@ -798,12 +635,12 @@ class ExperimentManager:
|
|||
else:
|
||||
repo_match = "repo_rev" not in expid
|
||||
if (repo_match and
|
||||
("file" in expid and expid["file"] == file) and
|
||||
expid["file"] == file and
|
||||
expid["class_name"] == class_name):
|
||||
rids.append(rid)
|
||||
asyncio.ensure_future(self._request_term_multiple(rids))
|
||||
|
||||
async def compute_expdesc(self, expurl):
|
||||
async def compute_arginfo(self, expurl):
|
||||
file, class_name, use_repository = self.resolve_expurl(expurl)
|
||||
if use_repository:
|
||||
revision = self.get_submission_options(expurl)["repo_rev"]
|
||||
|
|
@ -811,15 +648,13 @@ class ExperimentManager:
|
|||
revision = None
|
||||
description = await self.experiment_db_ctl.examine(
|
||||
file, use_repository, revision)
|
||||
class_desc = description[class_name]
|
||||
return class_desc, class_desc.get("argument_ui", None)
|
||||
return description[class_name]["arginfo"]
|
||||
|
||||
async def open_file(self, file):
|
||||
description = await self.experiment_db_ctl.examine(file, False)
|
||||
for class_name, class_desc in description.items():
|
||||
expurl = "file:{}@{}".format(class_name, file)
|
||||
self.initialize_submission_arguments(expurl, class_desc["arginfo"],
|
||||
class_desc.get("argument_ui", None))
|
||||
self.initialize_submission_arguments(expurl, class_desc["arginfo"])
|
||||
if expurl in self.open_experiments:
|
||||
self.open_experiments[expurl].close()
|
||||
self.open_experiment(expurl)
|
||||
|
|
@ -832,7 +667,6 @@ class ExperimentManager:
|
|||
"options": self.submission_options,
|
||||
"arguments": self.submission_arguments,
|
||||
"docks": self.dock_states,
|
||||
"argument_uis": self.argument_ui_names,
|
||||
"open_docks": set(self.open_experiments.keys())
|
||||
}
|
||||
|
||||
|
|
@ -843,17 +677,5 @@ class ExperimentManager:
|
|||
self.submission_scheduling = state["scheduling"]
|
||||
self.submission_options = state["options"]
|
||||
self.submission_arguments = state["arguments"]
|
||||
self.argument_ui_names = state.get("argument_uis", {})
|
||||
for expurl in state["open_docks"]:
|
||||
self.open_experiment(expurl)
|
||||
|
||||
def show_quick_open(self):
|
||||
if self.is_quick_open_shown:
|
||||
return
|
||||
|
||||
self.is_quick_open_shown = True
|
||||
dialog = _QuickOpenDialog(self)
|
||||
def closed():
|
||||
self.is_quick_open_shown = False
|
||||
dialog.closed.connect(closed)
|
||||
dialog.show()
|
||||
|
|
|
|||
|
|
@ -159,7 +159,7 @@ class WaitingPanel(LayoutWidget):
|
|||
class ExplorerDock(QtWidgets.QDockWidget):
|
||||
def __init__(self, exp_manager, d_shortcuts,
|
||||
explist_sub, explist_status_sub,
|
||||
schedule_ctl, experiment_db_ctl, device_db_ctl):
|
||||
schedule_ctl, experiment_db_ctl):
|
||||
QtWidgets.QDockWidget.__init__(self, "Explorer")
|
||||
self.setObjectName("Explorer")
|
||||
self.setFeatures(QtWidgets.QDockWidget.DockWidgetMovable |
|
||||
|
|
@ -251,12 +251,6 @@ class ExplorerDock(QtWidgets.QDockWidget):
|
|||
scan_repository_action.triggered.connect(scan_repository)
|
||||
self.el.addAction(scan_repository_action)
|
||||
|
||||
scan_ddb_action = QtWidgets.QAction("Scan device database", self.el)
|
||||
def scan_ddb():
|
||||
asyncio.ensure_future(device_db_ctl.scan())
|
||||
scan_ddb_action.triggered.connect(scan_ddb)
|
||||
self.el.addAction(scan_ddb_action)
|
||||
|
||||
self.current_directory = ""
|
||||
open_file_action = QtWidgets.QAction("Open file outside repository",
|
||||
self.el)
|
||||
|
|
|
|||
|
|
@ -1,34 +1,17 @@
|
|||
import asyncio
|
||||
import logging
|
||||
import textwrap
|
||||
from collections import namedtuple
|
||||
|
||||
from PyQt5 import QtCore, QtWidgets, QtGui
|
||||
|
||||
from sipyco.sync_struct import Subscriber
|
||||
|
||||
from artiq.protocols.sync_struct import Subscriber
|
||||
from artiq.coredevice.comm_moninj import *
|
||||
from artiq.coredevice.ad9910 import (
|
||||
_AD9910_REG_PROFILE0, _AD9910_REG_PROFILE7,
|
||||
_AD9910_REG_FTW, _AD9910_REG_CFR1
|
||||
)
|
||||
from artiq.coredevice.ad9912_reg import AD9912_POW1, AD9912_SER_CONF
|
||||
from artiq.gui.tools import LayoutWidget
|
||||
from artiq.gui.flowlayout import FlowLayout
|
||||
|
||||
|
||||
logger = logging.getLogger(__name__)
|
||||
|
||||
class _CancellableLineEdit(QtWidgets.QLineEdit):
|
||||
def escapePressedConnect(self, cb):
|
||||
self.esc_cb = cb
|
||||
|
||||
def keyPressEvent(self, event):
|
||||
key = event.key()
|
||||
if key == QtCore.Qt.Key_Escape:
|
||||
self.esc_cb(event)
|
||||
QtWidgets.QLineEdit.keyPressEvent(self, event)
|
||||
|
||||
|
||||
class _TTLWidget(QtWidgets.QFrame):
|
||||
def __init__(self, dm, channel, force_out, title):
|
||||
|
|
@ -91,7 +74,6 @@ class _TTLWidget(QtWidgets.QFrame):
|
|||
self.cur_level = False
|
||||
self.cur_oe = False
|
||||
self.cur_override = False
|
||||
self.cur_override_level = False
|
||||
self.refresh_display()
|
||||
|
||||
def enterEvent(self, event):
|
||||
|
|
@ -124,9 +106,7 @@ class _TTLWidget(QtWidgets.QFrame):
|
|||
self.set_mode(self.channel, "0")
|
||||
|
||||
def refresh_display(self):
|
||||
level = self.cur_override_level if self.cur_override else self.cur_level
|
||||
value_s = "1" if level else "0"
|
||||
|
||||
value_s = "1" if self.cur_level else "0"
|
||||
if self.cur_override:
|
||||
value_s = "<b>" + value_s + "</b>"
|
||||
color = " color=\"red\""
|
||||
|
|
@ -184,172 +164,15 @@ class _SimpleDisplayWidget(QtWidgets.QFrame):
|
|||
raise NotImplementedError
|
||||
|
||||
|
||||
class _DDSModel:
|
||||
def __init__(self, dds_type, ref_clk, cpld=None, pll=1, clk_div=0):
|
||||
self.cpld = cpld
|
||||
self.cur_frequency = 0
|
||||
self.cur_reg = 0
|
||||
self.dds_type = dds_type
|
||||
self.is_urukul = dds_type in ["AD9910", "AD9912"]
|
||||
|
||||
if dds_type == "AD9914":
|
||||
self.ftw_per_hz = 2**32 / ref_clk
|
||||
else:
|
||||
if dds_type == "AD9910":
|
||||
max_freq = 1 << 32
|
||||
clk_mult = [4, 1, 2, 4]
|
||||
elif dds_type == "AD9912": # AD9912
|
||||
max_freq = 1 << 48
|
||||
clk_mult = [1, 1, 2, 4]
|
||||
else:
|
||||
raise NotImplementedError
|
||||
sysclk = ref_clk / clk_mult[clk_div] * pll
|
||||
self.ftw_per_hz = 1 / sysclk * max_freq
|
||||
|
||||
def monitor_update(self, probe, value):
|
||||
if self.dds_type == "AD9912":
|
||||
value = value << 16
|
||||
self.cur_frequency = self._ftw_to_freq(value)
|
||||
|
||||
def _ftw_to_freq(self, ftw):
|
||||
return ftw / self.ftw_per_hz
|
||||
|
||||
|
||||
class _DDSWidget(QtWidgets.QFrame):
|
||||
def __init__(self, dm, title, bus_channel=0, channel=0, dds_model=None):
|
||||
self.dm = dm
|
||||
class _DDSWidget(_SimpleDisplayWidget):
|
||||
def __init__(self, dm, bus_channel, channel, title):
|
||||
self.bus_channel = bus_channel
|
||||
self.channel = channel
|
||||
self.dds_name = title
|
||||
self.cur_frequency = 0
|
||||
self.dds_model = dds_model
|
||||
|
||||
QtWidgets.QFrame.__init__(self)
|
||||
|
||||
self.setFrameShape(QtWidgets.QFrame.Box)
|
||||
self.setFrameShadow(QtWidgets.QFrame.Raised)
|
||||
|
||||
grid = QtWidgets.QGridLayout()
|
||||
grid.setContentsMargins(0, 0, 0, 0)
|
||||
grid.setHorizontalSpacing(0)
|
||||
grid.setVerticalSpacing(0)
|
||||
self.setLayout(grid)
|
||||
label = QtWidgets.QLabel(title)
|
||||
label.setAlignment(QtCore.Qt.AlignCenter)
|
||||
grid.addWidget(label, 1, 1)
|
||||
|
||||
# FREQ DATA/EDIT FIELD
|
||||
self.data_stack = QtWidgets.QStackedWidget()
|
||||
|
||||
# page 1: display data
|
||||
grid_disp = LayoutWidget()
|
||||
grid_disp.layout.setContentsMargins(0, 0, 0, 0)
|
||||
grid_disp.layout.setHorizontalSpacing(0)
|
||||
grid_disp.layout.setVerticalSpacing(0)
|
||||
|
||||
self.value_label = QtWidgets.QLabel()
|
||||
self.value_label.setAlignment(QtCore.Qt.AlignCenter)
|
||||
grid_disp.addWidget(self.value_label, 0, 1, 1, 2)
|
||||
|
||||
unit = QtWidgets.QLabel("MHz")
|
||||
unit.setAlignment(QtCore.Qt.AlignCenter)
|
||||
grid_disp.addWidget(unit, 0, 3, 1, 1)
|
||||
|
||||
self.data_stack.addWidget(grid_disp)
|
||||
|
||||
# page 2: edit data
|
||||
grid_edit = LayoutWidget()
|
||||
grid_edit.layout.setContentsMargins(0, 0, 0, 0)
|
||||
grid_edit.layout.setHorizontalSpacing(0)
|
||||
grid_edit.layout.setVerticalSpacing(0)
|
||||
|
||||
self.value_edit = _CancellableLineEdit(self)
|
||||
self.value_edit.setAlignment(QtCore.Qt.AlignRight)
|
||||
grid_edit.addWidget(self.value_edit, 0, 1, 1, 2)
|
||||
unit = QtWidgets.QLabel("MHz")
|
||||
unit.setAlignment(QtCore.Qt.AlignCenter)
|
||||
grid_edit.addWidget(unit, 0, 3, 1, 1)
|
||||
self.data_stack.addWidget(grid_edit)
|
||||
|
||||
grid.addWidget(self.data_stack, 2, 1)
|
||||
|
||||
# BUTTONS
|
||||
self.button_stack = QtWidgets.QStackedWidget()
|
||||
|
||||
# page 1: SET button
|
||||
set_grid = LayoutWidget()
|
||||
|
||||
set_btn = QtWidgets.QToolButton()
|
||||
set_btn.setText("Set")
|
||||
set_btn.setToolTip("Set frequency")
|
||||
set_grid.addWidget(set_btn, 0, 1, 1, 1)
|
||||
|
||||
# for urukuls also allow switching off RF
|
||||
if self.dds_model.is_urukul:
|
||||
off_btn = QtWidgets.QToolButton()
|
||||
off_btn.setText("Off")
|
||||
off_btn.setToolTip("Switch off the output")
|
||||
set_grid.addWidget(off_btn, 0, 2, 1, 1)
|
||||
|
||||
self.button_stack.addWidget(set_grid)
|
||||
|
||||
# page 2: apply/cancel buttons
|
||||
apply_grid = LayoutWidget()
|
||||
apply = QtWidgets.QToolButton()
|
||||
apply.setText("Apply")
|
||||
apply.setToolTip("Apply changes")
|
||||
apply_grid.addWidget(apply, 0, 1, 1, 1)
|
||||
cancel = QtWidgets.QToolButton()
|
||||
cancel.setText("Cancel")
|
||||
cancel.setToolTip("Cancel changes")
|
||||
apply_grid.addWidget(cancel, 0, 2, 1, 1)
|
||||
self.button_stack.addWidget(apply_grid)
|
||||
grid.addWidget(self.button_stack, 3, 1)
|
||||
|
||||
grid.setRowStretch(1, 1)
|
||||
grid.setRowStretch(2, 1)
|
||||
grid.setRowStretch(3, 1)
|
||||
|
||||
set_btn.clicked.connect(self.set_clicked)
|
||||
apply.clicked.connect(self.apply_changes)
|
||||
if self.dds_model.is_urukul:
|
||||
off_btn.clicked.connect(self.off_clicked)
|
||||
off_btn.setToolTip(textwrap.dedent(
|
||||
"""Note: If TTL RTIO sw for the channel is switched high,
|
||||
this button will not disable the channel.
|
||||
Use the TTL override instead."""))
|
||||
self.value_edit.returnPressed.connect(lambda: self.apply_changes(None))
|
||||
self.value_edit.escapePressedConnect(self.cancel_changes)
|
||||
cancel.clicked.connect(self.cancel_changes)
|
||||
|
||||
self.refresh_display()
|
||||
|
||||
def set_clicked(self, set):
|
||||
self.data_stack.setCurrentIndex(1)
|
||||
self.button_stack.setCurrentIndex(1)
|
||||
self.value_edit.setText("{:.7f}"
|
||||
.format(self.cur_frequency/1e6))
|
||||
self.value_edit.setFocus()
|
||||
self.value_edit.selectAll()
|
||||
|
||||
def off_clicked(self, set):
|
||||
self.dm.dds_channel_toggle(self.dds_name, self.dds_model, sw=False)
|
||||
|
||||
def apply_changes(self, apply):
|
||||
self.data_stack.setCurrentIndex(0)
|
||||
self.button_stack.setCurrentIndex(0)
|
||||
frequency = float(self.value_edit.text())*1e6
|
||||
self.dm.dds_set_frequency(self.dds_name, self.dds_model, frequency)
|
||||
|
||||
def cancel_changes(self, cancel):
|
||||
self.data_stack.setCurrentIndex(0)
|
||||
self.button_stack.setCurrentIndex(0)
|
||||
_SimpleDisplayWidget.__init__(self, title)
|
||||
|
||||
def refresh_display(self):
|
||||
self.cur_frequency = self.dds_model.cur_frequency
|
||||
self.value_label.setText("<font size=\"4\">{:.7f}</font>"
|
||||
.format(self.cur_frequency/1e6))
|
||||
self.value_edit.setText("{:.7f}"
|
||||
self.value.setText("<font size=\"4\">{:.7f}</font><font size=\"2\"> MHz</font>"
|
||||
.format(self.cur_frequency/1e6))
|
||||
|
||||
def sort_key(self):
|
||||
|
|
@ -375,74 +198,51 @@ _WidgetDesc = namedtuple("_WidgetDesc", "uid comment cls arguments")
|
|||
|
||||
|
||||
def setup_from_ddb(ddb):
|
||||
mi_addr = None
|
||||
mi_port = None
|
||||
core_addr = None
|
||||
dds_sysclk = None
|
||||
description = set()
|
||||
|
||||
for k, v in ddb.items():
|
||||
comment = None
|
||||
if "comment" in v:
|
||||
comment = v["comment"]
|
||||
try:
|
||||
if isinstance(v, dict):
|
||||
comment = v.get("comment")
|
||||
if v["type"] == "local":
|
||||
if v["module"] == "artiq.coredevice.ttl":
|
||||
if "ttl_urukul" in k:
|
||||
continue
|
||||
channel = v["arguments"]["channel"]
|
||||
force_out = v["class"] == "TTLOut"
|
||||
widget = _WidgetDesc(k, comment, _TTLWidget, (channel, force_out, k))
|
||||
description.add(widget)
|
||||
elif (v["module"] == "artiq.coredevice.ad9914"
|
||||
and v["class"] == "AD9914"):
|
||||
bus_channel = v["arguments"]["bus_channel"]
|
||||
channel = v["arguments"]["channel"]
|
||||
dds_sysclk = v["arguments"]["sysclk"]
|
||||
model = _DDSModel(v["class"], dds_sysclk)
|
||||
widget = _WidgetDesc(k, comment, _DDSWidget, (k, bus_channel, channel, model))
|
||||
description.add(widget)
|
||||
elif (v["module"] == "artiq.coredevice.ad9910"
|
||||
and v["class"] == "AD9910") or \
|
||||
(v["module"] == "artiq.coredevice.ad9912"
|
||||
and v["class"] == "AD9912"):
|
||||
channel = v["arguments"]["chip_select"] - 4
|
||||
if channel < 0:
|
||||
continue
|
||||
dds_cpld = v["arguments"]["cpld_device"]
|
||||
spi_dev = ddb[dds_cpld]["arguments"]["spi_device"]
|
||||
bus_channel = ddb[spi_dev]["arguments"]["channel"]
|
||||
pll = v["arguments"]["pll_n"]
|
||||
refclk = ddb[dds_cpld]["arguments"]["refclk"]
|
||||
clk_div = v["arguments"].get("clk_div", 0)
|
||||
model = _DDSModel( v["class"], refclk, dds_cpld, pll, clk_div)
|
||||
widget = _WidgetDesc(k, comment, _DDSWidget, (k, bus_channel, channel, model))
|
||||
description.add(widget)
|
||||
elif ( (v["module"] == "artiq.coredevice.ad53xx" and v["class"] == "AD53xx")
|
||||
or (v["module"] == "artiq.coredevice.zotino" and v["class"] == "Zotino")):
|
||||
spi_device = v["arguments"]["spi_device"]
|
||||
if isinstance(v, dict) and v["type"] == "local":
|
||||
if k == "core":
|
||||
core_addr = v["arguments"]["host"]
|
||||
elif v["module"] == "artiq.coredevice.ttl":
|
||||
channel = v["arguments"]["channel"]
|
||||
force_out = v["class"] == "TTLOut"
|
||||
widget = _WidgetDesc(k, comment, _TTLWidget, (channel, force_out, k))
|
||||
description.add(widget)
|
||||
elif (v["module"] == "artiq.coredevice.ad9914"
|
||||
and v["class"] == "AD9914"):
|
||||
bus_channel = v["arguments"]["bus_channel"]
|
||||
channel = v["arguments"]["channel"]
|
||||
dds_sysclk = v["arguments"]["sysclk"]
|
||||
widget = _WidgetDesc(k, comment, _DDSWidget, (bus_channel, channel, k))
|
||||
description.add(widget)
|
||||
elif ( (v["module"] == "artiq.coredevice.ad53xx" and v["class"] == "AD53XX")
|
||||
or (v["module"] == "artiq.coredevice.zotino" and v["class"] == "Zotino")):
|
||||
spi_device = v["arguments"]["spi_device"]
|
||||
spi_device = ddb[spi_device]
|
||||
while isinstance(spi_device, str):
|
||||
spi_device = ddb[spi_device]
|
||||
while isinstance(spi_device, str):
|
||||
spi_device = ddb[spi_device]
|
||||
spi_channel = spi_device["arguments"]["channel"]
|
||||
for channel in range(32):
|
||||
widget = _WidgetDesc((k, channel), comment, _DACWidget, (spi_channel, channel, k))
|
||||
description.add(widget)
|
||||
elif v["type"] == "controller" and k == "core_moninj":
|
||||
mi_addr = v["host"]
|
||||
mi_port = v.get("port_proxy", 1383)
|
||||
spi_channel = spi_device["arguments"]["channel"]
|
||||
for channel in range(32):
|
||||
widget = _WidgetDesc((k, channel), comment, _DACWidget, (spi_channel, channel, k))
|
||||
description.add(widget)
|
||||
except KeyError:
|
||||
pass
|
||||
return mi_addr, mi_port, description
|
||||
return core_addr, dds_sysclk, description
|
||||
|
||||
|
||||
class _DeviceManager:
|
||||
def __init__(self, schedule_ctl):
|
||||
self.mi_addr = None
|
||||
self.mi_port = None
|
||||
self.reconnect_mi = asyncio.Event()
|
||||
self.mi_connection = None
|
||||
self.mi_connector_task = asyncio.ensure_future(self.mi_connector())
|
||||
|
||||
self.schedule_ctl = schedule_ctl
|
||||
def __init__(self):
|
||||
self.core_addr = None
|
||||
self.new_core_addr = asyncio.Event()
|
||||
self.core_connection = None
|
||||
self.core_connector_task = asyncio.ensure_future(self.core_connector())
|
||||
|
||||
self.ddb = dict()
|
||||
self.description = set()
|
||||
|
|
@ -461,12 +261,13 @@ class _DeviceManager:
|
|||
return ddb
|
||||
|
||||
def notify(self, mod):
|
||||
mi_addr, mi_port, description = setup_from_ddb(self.ddb)
|
||||
core_addr, dds_sysclk, description = setup_from_ddb(self.ddb)
|
||||
|
||||
if (mi_addr, mi_port) != (self.mi_addr, self.mi_port):
|
||||
self.mi_addr = mi_addr
|
||||
self.mi_port = mi_port
|
||||
self.reconnect_mi.set()
|
||||
if core_addr != self.core_addr:
|
||||
self.core_addr = core_addr
|
||||
self.new_core_addr.set()
|
||||
|
||||
self.dds_sysclk = dds_sysclk
|
||||
|
||||
for to_remove in self.description - description:
|
||||
widget = self.widgets_by_uid[to_remove.uid]
|
||||
|
|
@ -514,172 +315,44 @@ class _DeviceManager:
|
|||
self.description = description
|
||||
|
||||
def ttl_set_mode(self, channel, mode):
|
||||
if self.mi_connection is not None:
|
||||
if self.core_connection is not None:
|
||||
widget = self.ttl_widgets[channel]
|
||||
if mode == "0":
|
||||
widget.cur_override = True
|
||||
widget.cur_level = False
|
||||
self.mi_connection.inject(channel, TTLOverride.level.value, 0)
|
||||
self.mi_connection.inject(channel, TTLOverride.oe.value, 1)
|
||||
self.mi_connection.inject(channel, TTLOverride.en.value, 1)
|
||||
self.core_connection.inject(channel, TTLOverride.level.value, 0)
|
||||
self.core_connection.inject(channel, TTLOverride.oe.value, 1)
|
||||
self.core_connection.inject(channel, TTLOverride.en.value, 1)
|
||||
elif mode == "1":
|
||||
widget.cur_override = True
|
||||
widget.cur_level = True
|
||||
self.mi_connection.inject(channel, TTLOverride.level.value, 1)
|
||||
self.mi_connection.inject(channel, TTLOverride.oe.value, 1)
|
||||
self.mi_connection.inject(channel, TTLOverride.en.value, 1)
|
||||
self.core_connection.inject(channel, TTLOverride.level.value, 1)
|
||||
self.core_connection.inject(channel, TTLOverride.oe.value, 1)
|
||||
self.core_connection.inject(channel, TTLOverride.en.value, 1)
|
||||
elif mode == "exp":
|
||||
widget.cur_override = False
|
||||
self.mi_connection.inject(channel, TTLOverride.en.value, 0)
|
||||
self.core_connection.inject(channel, TTLOverride.en.value, 0)
|
||||
else:
|
||||
raise ValueError
|
||||
# override state may have changed
|
||||
widget.refresh_display()
|
||||
|
||||
async def _submit_by_content(self, content, class_name, title):
|
||||
expid = {
|
||||
"log_level": logging.WARNING,
|
||||
"content": content,
|
||||
"class_name": class_name,
|
||||
"arguments": {}
|
||||
}
|
||||
scheduling = {
|
||||
"pipeline_name": "main",
|
||||
"priority": 0,
|
||||
"due_date": None,
|
||||
"flush": False
|
||||
}
|
||||
rid = await self.schedule_ctl.submit(
|
||||
scheduling["pipeline_name"],
|
||||
expid,
|
||||
scheduling["priority"], scheduling["due_date"],
|
||||
scheduling["flush"])
|
||||
logger.info("Submitted '%s', RID is %d", title, rid)
|
||||
|
||||
def _dds_faux_injection(self, dds_channel, dds_model, action, title, log_msg):
|
||||
# create kernel and fill it in and send-by-content
|
||||
|
||||
# initialize CPLD (if applicable)
|
||||
if dds_model.is_urukul:
|
||||
# urukuls need CPLD init and switch to on
|
||||
cpld_dev = """self.setattr_device("core_cache")
|
||||
self.setattr_device("{}")""".format(dds_model.cpld)
|
||||
|
||||
# `sta`/`rf_sw`` variables are guaranteed for urukuls
|
||||
# so {action} can use it
|
||||
# if there's no RF enabled, CPLD may have not been initialized
|
||||
# but if there is, it has been initialised - no need to do again
|
||||
cpld_init = """delay(15*ms)
|
||||
was_init = self.core_cache.get("_{cpld}_init")
|
||||
sta = self.{cpld}.sta_read()
|
||||
rf_sw = urukul_sta_rf_sw(sta)
|
||||
if rf_sw == 0 and len(was_init) == 0:
|
||||
delay(15*ms)
|
||||
self.{cpld}.init()
|
||||
self.core_cache.put("_{cpld}_init", [1])
|
||||
""".format(cpld=dds_model.cpld)
|
||||
else:
|
||||
cpld_dev = ""
|
||||
cpld_init = ""
|
||||
|
||||
# AD9912/9910: init channel (if uninitialized)
|
||||
if dds_model.dds_type == "AD9912":
|
||||
# 0xFF before init, 0x99 after
|
||||
channel_init = """
|
||||
if self.{dds_channel}.read({cfgreg}, length=1) == 0xFF:
|
||||
delay(10*ms)
|
||||
self.{dds_channel}.init()
|
||||
""".format(dds_channel=dds_channel, cfgreg=AD9912_SER_CONF)
|
||||
elif dds_model.dds_type == "AD9910":
|
||||
# -1 before init, 2 after
|
||||
channel_init = """
|
||||
if self.{dds_channel}.read32({cfgreg}) == -1:
|
||||
delay(10*ms)
|
||||
self.{dds_channel}.init()
|
||||
""".format(dds_channel=dds_channel, cfgreg=AD9912_SER_CONF)
|
||||
else:
|
||||
channel_init = "self.{dds_channel}.init()".format(dds_channel=dds_channel)
|
||||
|
||||
dds_exp = textwrap.dedent("""
|
||||
from artiq.experiment import *
|
||||
from artiq.coredevice.urukul import *
|
||||
|
||||
class {title}(EnvExperiment):
|
||||
def build(self):
|
||||
self.setattr_device("core")
|
||||
self.setattr_device("{dds_channel}")
|
||||
{cpld_dev}
|
||||
|
||||
@kernel
|
||||
def run(self):
|
||||
self.core.break_realtime()
|
||||
{cpld_init}
|
||||
delay(10*ms)
|
||||
{channel_init}
|
||||
delay(15*ms)
|
||||
{action}
|
||||
""".format(title=title, action=action,
|
||||
dds_channel=dds_channel,
|
||||
cpld_dev=cpld_dev, cpld_init=cpld_init,
|
||||
channel_init=channel_init))
|
||||
asyncio.ensure_future(
|
||||
self._submit_by_content(
|
||||
dds_exp,
|
||||
title,
|
||||
log_msg))
|
||||
|
||||
def dds_set_frequency(self, dds_channel, dds_model, freq):
|
||||
action = "self.{ch}.set({freq})".format(
|
||||
freq=freq, ch=dds_channel)
|
||||
if dds_model.is_urukul:
|
||||
action += """
|
||||
ch_no = self.{ch}.chip_select - 4
|
||||
self.{cpld}.cfg_switches(rf_sw | 1 << ch_no)
|
||||
""".format(ch=dds_channel, cpld=dds_model.cpld)
|
||||
self._dds_faux_injection(
|
||||
dds_channel,
|
||||
dds_model,
|
||||
action,
|
||||
"SetDDS",
|
||||
"Set DDS {} {}MHz".format(dds_channel, freq/1e6))
|
||||
|
||||
def dds_channel_toggle(self, dds_channel, dds_model, sw=True):
|
||||
# urukul only
|
||||
if sw:
|
||||
switch = "| 1 << ch_no"
|
||||
else:
|
||||
switch = "& ~(1 << ch_no)"
|
||||
action = """
|
||||
ch_no = self.{dds_channel}.chip_select - 4
|
||||
self.{cpld}.cfg_switches(rf_sw {switch})
|
||||
""".format(
|
||||
dds_channel=dds_channel,
|
||||
cpld=dds_model.cpld,
|
||||
switch=switch
|
||||
)
|
||||
self._dds_faux_injection(
|
||||
dds_channel,
|
||||
dds_model,
|
||||
action,
|
||||
"ToggleDDS",
|
||||
"Toggle DDS {} {}".format(dds_channel, "on" if sw else "off"))
|
||||
|
||||
def setup_ttl_monitoring(self, enable, channel):
|
||||
if self.mi_connection is not None:
|
||||
self.mi_connection.monitor_probe(enable, channel, TTLProbe.level.value)
|
||||
self.mi_connection.monitor_probe(enable, channel, TTLProbe.oe.value)
|
||||
self.mi_connection.monitor_injection(enable, channel, TTLOverride.en.value)
|
||||
self.mi_connection.monitor_injection(enable, channel, TTLOverride.level.value)
|
||||
if self.core_connection is not None:
|
||||
self.core_connection.monitor_probe(enable, channel, TTLProbe.level.value)
|
||||
self.core_connection.monitor_probe(enable, channel, TTLProbe.oe.value)
|
||||
self.core_connection.monitor_injection(enable, channel, TTLOverride.en.value)
|
||||
self.core_connection.monitor_injection(enable, channel, TTLOverride.level.value)
|
||||
if enable:
|
||||
self.mi_connection.get_injection_status(channel, TTLOverride.en.value)
|
||||
self.core_connection.get_injection_status(channel, TTLOverride.en.value)
|
||||
|
||||
def setup_dds_monitoring(self, enable, bus_channel, channel):
|
||||
if self.mi_connection is not None:
|
||||
self.mi_connection.monitor_probe(enable, bus_channel, channel)
|
||||
if self.core_connection is not None:
|
||||
self.core_connection.monitor_probe(enable, bus_channel, channel)
|
||||
|
||||
def setup_dac_monitoring(self, enable, spi_channel, channel):
|
||||
if self.mi_connection is not None:
|
||||
self.mi_connection.monitor_probe(enable, spi_channel, channel)
|
||||
if self.core_connection is not None:
|
||||
self.core_connection.monitor_probe(enable, spi_channel, channel)
|
||||
|
||||
def monitor_cb(self, channel, probe, value):
|
||||
if channel in self.ttl_widgets:
|
||||
|
|
@ -689,11 +362,11 @@ class _DeviceManager:
|
|||
elif probe == TTLProbe.oe.value:
|
||||
widget.cur_oe = bool(value)
|
||||
widget.refresh_display()
|
||||
elif (channel, probe) in self.dds_widgets:
|
||||
if (channel, probe) in self.dds_widgets:
|
||||
widget = self.dds_widgets[(channel, probe)]
|
||||
widget.dds_model.monitor_update(probe, value)
|
||||
widget.cur_frequency = value*self.dds_sysclk/2**32
|
||||
widget.refresh_display()
|
||||
elif (channel, probe) in self.dac_widgets:
|
||||
if (channel, probe) in self.dac_widgets:
|
||||
widget = self.dac_widgets[(channel, probe)]
|
||||
widget.cur_value = value
|
||||
widget.refresh_display()
|
||||
|
|
@ -704,35 +377,24 @@ class _DeviceManager:
|
|||
if override == TTLOverride.en.value:
|
||||
widget.cur_override = bool(value)
|
||||
if override == TTLOverride.level.value:
|
||||
widget.cur_override_level = bool(value)
|
||||
widget.cur_level = bool(value)
|
||||
widget.refresh_display()
|
||||
|
||||
def disconnect_cb(self):
|
||||
logger.error("lost connection to moninj")
|
||||
self.reconnect_mi.set()
|
||||
|
||||
async def mi_connector(self):
|
||||
async def core_connector(self):
|
||||
while True:
|
||||
await self.reconnect_mi.wait()
|
||||
self.reconnect_mi.clear()
|
||||
if self.mi_connection is not None:
|
||||
await self.mi_connection.close()
|
||||
self.mi_connection = None
|
||||
new_mi_connection = CommMonInj(self.monitor_cb, self.injection_status_cb,
|
||||
self.disconnect_cb)
|
||||
await self.new_core_addr.wait()
|
||||
self.new_core_addr.clear()
|
||||
if self.core_connection is not None:
|
||||
await self.core_connection.close()
|
||||
self.core_connection = None
|
||||
new_core_connection = CommMonInj(self.monitor_cb, self.injection_status_cb,
|
||||
lambda: logger.error("lost connection to core device moninj"))
|
||||
try:
|
||||
await new_mi_connection.connect(self.mi_addr, self.mi_port)
|
||||
except asyncio.CancelledError:
|
||||
logger.info("cancelled connection to moninj")
|
||||
break
|
||||
await new_core_connection.connect(self.core_addr, 1383)
|
||||
except:
|
||||
logger.error("failed to connect to moninj. Is aqctl_moninj_proxy running?", exc_info=True)
|
||||
await asyncio.sleep(10.)
|
||||
self.reconnect_mi.set()
|
||||
logger.error("failed to connect to core device moninj", exc_info=True)
|
||||
else:
|
||||
logger.info("ARTIQ dashboard connected to moninj (%s)",
|
||||
self.mi_addr)
|
||||
self.mi_connection = new_mi_connection
|
||||
self.core_connection = new_core_connection
|
||||
for ttl_channel in self.ttl_widgets.keys():
|
||||
self.setup_ttl_monitoring(True, ttl_channel)
|
||||
for bus_channel, channel in self.dds_widgets.keys():
|
||||
|
|
@ -741,13 +403,13 @@ class _DeviceManager:
|
|||
self.setup_dac_monitoring(True, spi_channel, channel)
|
||||
|
||||
async def close(self):
|
||||
self.mi_connector_task.cancel()
|
||||
self.core_connector_task.cancel()
|
||||
try:
|
||||
await asyncio.wait_for(self.mi_connector_task, None)
|
||||
await asyncio.wait_for(self.core_connector_task, None)
|
||||
except asyncio.CancelledError:
|
||||
pass
|
||||
if self.mi_connection is not None:
|
||||
await self.mi_connection.close()
|
||||
if self.core_connection is not None:
|
||||
await self.core_connection.close()
|
||||
|
||||
|
||||
class _MonInjDock(QtWidgets.QDockWidget):
|
||||
|
|
@ -773,12 +435,12 @@ class _MonInjDock(QtWidgets.QDockWidget):
|
|||
|
||||
|
||||
class MonInj:
|
||||
def __init__(self, schedule_ctl):
|
||||
def __init__(self):
|
||||
self.ttl_dock = _MonInjDock("TTL")
|
||||
self.dds_dock = _MonInjDock("DDS")
|
||||
self.dac_dock = _MonInjDock("DAC")
|
||||
|
||||
self.dm = _DeviceManager(schedule_ctl)
|
||||
self.dm = _DeviceManager()
|
||||
self.dm.ttl_cb = lambda: self.ttl_dock.layout_widgets(
|
||||
self.dm.ttl_widgets.values())
|
||||
self.dm.dds_cb = lambda: self.dds_dock.layout_widgets(
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ class Model(DictSyncModel):
|
|||
else:
|
||||
return "Outside repo."
|
||||
elif column == 6:
|
||||
return v["expid"].get("file", "<none>")
|
||||
return v["expid"]["file"]
|
||||
elif column == 7:
|
||||
if v["expid"]["class_name"] is None:
|
||||
return ""
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue