conda: pin openocd (artiq, artiq-dev) #932

closes #863

.readthedocs.yml

@@ -0,0 +1,5 @@
+python:
+  version: 3
+  pip_install: false
+conda:
+  file: conda/artiq-doc.yml

CONTRIBUTING.rst

@@ -51,7 +51,7 @@ Copyright and Sign-Off
 ----------------------
 
 Authors retain copyright of their contributions to ARTIQ, but whenever possible
-should use the GNU GPL version 3 license for them to be merged.
+should use the GNU LGPL version 3 license for them to be merged.
 
 Works of US government employees are not copyrighted but can also be merged.
 

LICENSE

@@ -1,674 +1,165 @@
-                    GNU GENERAL PUBLIC LICENSE
+                   GNU LESSER GENERAL PUBLIC LICENSE
                        Version 3, 29 June 2007
 
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+
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+
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+
+   a) Accompany the combined library with a copy of the same work based
+   on the Library, uncombined with any other library facilities,
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+
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+   is a work based on the Library, and explaining where to find the
+   accompanying uncombined form of the same work.
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+
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+of the GNU Lesser General Public License from time to time. Such new
+versions will be similar in spirit to the present version, but may
+differ in detail to address new problems or concerns.
 
   Each version is given a distinguishing version number. If the
-Program specifies that a certain numbered version of the GNU General
-Public License "or any later version" applies to it, you have the
-option of following the terms and conditions either of that numbered
-version or of any later version published by the Free Software
-Foundation.  If the Program does not specify a version number of the
-GNU General Public License, you may choose any version ever published
-by the Free Software Foundation.
+Library as you received it specifies that a certain numbered version
+of the GNU Lesser General Public License "or any later version"
+applies to it, you have the option of following the terms and
+conditions either of that published version or of any later version
+published by the Free Software Foundation. If the Library as you
+received it does not specify a version number of the GNU Lesser
+General Public License, you may choose any version of the GNU Lesser
+General Public License ever published by the Free Software Foundation.
 
-  If the Program specifies that a proxy can decide which future
-versions of the GNU General Public License can be used, that proxy's
-public statement of acceptance of a version permanently authorizes you
-to choose that version for the Program.
-
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-permissions.  However, no additional obligations are imposed on any
-author or copyright holder as a result of your choosing to follow a
-later version.
-
-  15. Disclaimer of Warranty.
-
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-APPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
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-copy of the Program in return for a fee.
-
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-
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-
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-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
-  To do so, attach the following notices to the program.  It is safest
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-state the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
-    <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) <year>  <name of author>
-
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-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation, either version 3 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
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-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
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-    This is free software, and you are welcome to redistribute it
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-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License.  Of course, your program's commands
-might be different; for a GUI interface, you would use an "about box".
-
-  You should also get your employer (if you work as a programmer) or school,
-if any, to sign a "copyright disclaimer" for the program, if necessary.
-For more information on this, and how to apply and follow the GNU GPL, see
-<http://www.gnu.org/licenses/>.
-
-  The GNU General Public License does not permit incorporating your program
-into proprietary programs.  If your program is a subroutine library, you
-may consider it more useful to permit linking proprietary applications with
-the library.  If this is what you want to do, use the GNU Lesser General
-Public License instead of this License.  But first, please read
-<http://www.gnu.org/philosophy/why-not-lgpl.html>.
+  If the Library as you received it specifies that a proxy can decide
+whether future versions of the GNU Lesser General Public License shall
+apply, that proxy's public statement of acceptance of any version is
+permanent authorization for you to choose that version for the
+Library.

README.rst

@@ -5,7 +5,7 @@
   :target: https://m-labs.hk/artiq
 
 ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) is the next-generation control system for quantum information experiments.
-It is developed by `M-Labs <https://m-labs.hk>`_ for and in partnership with the `Ion Storage Group at NIST <http://www.nist.gov/pml/div688/grp10/index.cfm>`_ as free software.
+It is developed by `M-Labs <https://m-labs.hk>`_ for and in partnership with the `Ion Storage Group at NIST <https://www.nist.gov/pml/time-and-frequency-division/ion-storage>`_ as free software.
 It is offered to the entire research community as a solution equally applicable to other challenging control tasks outside the field of ion trapping.
 
 The system features a high-level programming language that helps describing complex experiments, which is compiled and executed on dedicated hardware with nanosecond timing resolution and sub-microsecond latency. It includes graphical user interfaces to parametrize and schedule experiments and to visualize and explore the results.
@@ -15,7 +15,7 @@ It is designed to be portable to hardware platforms from different vendors and F
 Currently, one configuration of a `low-cost open hardware FPGA board <http://pipistrello.saanlima.com/>`_ and several different configurations of a `high-end FPGA evaluation kit <http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html>`_ are used and supported.
 Any of these FPGA platforms can be combined with any number of additional peripherals, either already accessible from ARTIQ or made accessible with little effort.
 
-Custom hardware components with widely extended capabilities and advanced support for scalable and fully distributed real-time control of experiments `are being designed <https://github.com/m-labs/artiq-hardware>`_.
+Custom hardware components with widely extended capabilities and advanced support for scalable and fully distributed real-time control of experiments `are being designed <https://github.com/m-labs/sinara>`_.
 
 ARTIQ and its dependencies are available in the form of `conda packages <https://conda.anaconda.org/m-labs/label/main>`_ for both Linux and Windows.
 Packages containing pre-compiled binary images to be loaded onto the hardware platforms are supplied for each configuration.
@@ -30,4 +30,17 @@ Website: https://m-labs.hk/artiq
 
 `Cite ARTIQ <http://dx.doi.org/10.5281/zenodo.51303>`_ as ``Bourdeauducq, Sébastien et al. (2016). ARTIQ 1.0. Zenodo. 10.5281/zenodo.51303``.
 
-Copyright (C) 2014-2016 M-Labs Limited. Licensed under GNU GPL version 3.
+Copyright (C) 2014-2017 M-Labs Limited.
+
+ARTIQ is free software: you can redistribute it and/or modify
+it under the terms of the GNU Lesser General Public License as published by
+the Free Software Foundation, either version 3 of the License, or
+(at your option) any later version.
+
+ARTIQ is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU Lesser General Public License for more details.
+
+You should have received a copy of the GNU Lesser General Public License
+along with ARTIQ.  If not, see <http://www.gnu.org/licenses/>.

RELEASE_NOTES.rst

@@ -3,8 +3,50 @@
 Release notes
 =============
 
-unreleased [2.x]
-----------------
+2.5
+---
+
+No further notes.
+
+
+2.4
+---
+
+No further notes.
+
+
+2.3
+---
+
+* When using conda, add the conda-forge channel before installing ARTIQ.
+
+
+2.2
+---
+
+No further notes.
+
+
+2.1
+---
+
+No further notes.
+
+
+2.0
+---
+
+No further notes.
+
+
+2.0rc2
+------
+
+No further notes.
+
+
+2.0rc1
+------
 
 * The format of the influxdb pattern file is simplified. The procedure to
   edit patterns is also changed to modifying the pattern file and calling:
@@ -34,6 +76,8 @@ unreleased [2.x]
   (i.e. grouping by day and then by hour, instead of by day and then by minute)
 * The ``parent`` keyword argument of ``HasEnvironment`` (and ``EnvExperiment``)
   has been replaced. Pass the parent as first argument instead.
+* During experiment examination (and a fortiori repository scan), the values of
+  all arguments are set to ``None`` regardless of any default values supplied.
 * In the dashboard's experiment windows, partial or full argument recomputation
   takes into account the repository revision field.
 * By default, ``NumberValue`` and ``Scannable`` infer the scale from the unit
@@ -50,6 +94,7 @@ unreleased [2.x]
   numpy.int64). If you pass an integer as a RPC argument, the target function
   receives a numpy type.
 
+
 1.3
 ---
 

RELEASING.rst

@@ -11,9 +11,11 @@ Major releases
 3. Ensure that release versions of all packages required are available under the ``main`` label in conda. Ensure that new packages in ``main`` do not break older ARTIQ releases.
 4. In the release-X branch, remove any unfinished features.
 5. Test and fix any problems found. Apply fixes to both master and release-X.
-6. If you have willing testers for release candidates, tag X.0rc1 in the release-X branch, have it build, and point testers there. Iterate over the previous points with new release candidates if necessary.
+6. If you have willing testers for release candidates, tag X.0rc1 in the release-X branch (generally use signed annotated tags, i.e. ``git tag -sa X.0rc1``), have it build, and point testers there. Iterate over the previous points with new release candidates if necessary.
 7. Tag X.0 in the release-X branch, build it, and copy its packages to ``main`` channel.
 8. Mint a new DOI from Zenodo and update the README/introduction.
+9. Update the m-labs.hk/artiq/manual redirect to point to m-labs.hk/artiq/manual-release-X (edit /artiq/.htaccess).
+10. "Draft a new release" on GitHub.
 
 Minor (bugfix) releases
 -----------------------
@@ -21,3 +23,4 @@ Minor (bugfix) releases
 1. Backport bugfixes from the master branch or fix bugs specific to old releases into the currently maintained release-X branch(es).
 2. When significant bugs have been fixed, tag X.Y+1.
 3. To help dealing with regressions, no new features or refactorings should be implemented in release-X branches. Those happen in the master branch, and then a new release-X+1 branch is created.
+4. "Draft a new release" on GitHub.

artiq/__init__.py

@@ -5,3 +5,7 @@ del get_versions
 import os
 __artiq_dir__ = os.path.dirname(os.path.abspath(__file__))
 del os
+
+from ._version import get_versions
+__version__ = get_versions()['version']
+del get_versions

artiq/_version.py

@@ -6,7 +6,7 @@
 # that just contains the computed version number.
 
 # This file is released into the public domain. Generated by
-# versioneer-0.15+dev (https://github.com/warner/python-versioneer)
+# versioneer-0.18 (https://github.com/warner/python-versioneer)
 
 """Git implementation of _version.py."""
 
@@ -25,12 +25,12 @@ def get_keywords():
     # get_keywords().
     git_refnames = "$Format:%d$"
     git_full = "$Format:%H$"
-    keywords = {"refnames": git_refnames, "full": git_full}
+    git_date = "$Format:%ci$"
+    keywords = {"refnames": git_refnames, "full": git_full, "date": git_date}
     return keywords
 
 
 class VersioneerConfig:
-
     """Container for Versioneer configuration parameters."""
 
 
@@ -49,7 +49,6 @@ def get_config():
 
 
 class NotThisMethod(Exception):
-
     """Exception raised if a method is not valid for the current scenario."""
 
 
@@ -68,7 +67,8 @@ def register_vcs_handler(vcs, method):  # decorator
     return decorate
 
 
-def run_command(commands, args, cwd=None, verbose=False, hide_stderr=False):
+def run_command(commands, args, cwd=None, verbose=False, hide_stderr=False,
+                env=None):
     """Call the given command(s)."""
     assert isinstance(commands, list)
     p = None
@@ -76,7 +76,8 @@ def run_command(commands, args, cwd=None, verbose=False, hide_stderr=False):
         try:
             dispcmd = str([c] + args)
             # remember shell=False, so use git.cmd on windows, not just git
-            p = subprocess.Popen([c] + args, cwd=cwd, stdout=subprocess.PIPE,
+            p = subprocess.Popen([c] + args, cwd=cwd, env=env,
+                                 stdout=subprocess.PIPE,
                                  stderr=(subprocess.PIPE if hide_stderr
                                          else None))
             break
@@ -87,36 +88,45 @@ def run_command(commands, args, cwd=None, verbose=False, hide_stderr=False):
             if verbose:
                 print("unable to run %s" % dispcmd)
                 print(e)
-            return None
+            return None, None
     else:
         if verbose:
             print("unable to find command, tried %s" % (commands,))
-        return None
+        return None, None
     stdout = p.communicate()[0].strip()
     if sys.version_info[0] >= 3:
         stdout = stdout.decode()
     if p.returncode != 0:
         if verbose:
             print("unable to run %s (error)" % dispcmd)
-        return None
-    return stdout
+            print("stdout was %s" % stdout)
+        return None, p.returncode
+    return stdout, p.returncode
 
 
 def versions_from_parentdir(parentdir_prefix, root, verbose):
     """Try to determine the version from the parent directory name.
 
-    Source tarballs conventionally unpack into a directory that includes
-    both the project name and a version string.
+    Source tarballs conventionally unpack into a directory that includes both
+    the project name and a version string. We will also support searching up
+    two directory levels for an appropriately named parent directory
     """
+    rootdirs = []
+
+    for i in range(3):
         dirname = os.path.basename(root)
-    if not dirname.startswith(parentdir_prefix):
-        if verbose:
-            print("guessing rootdir is '%s', but '%s' doesn't start with "
-                  "prefix '%s'" % (root, dirname, parentdir_prefix))
-        raise NotThisMethod("rootdir doesn't start with parentdir_prefix")
+        if dirname.startswith(parentdir_prefix):
             return {"version": dirname[len(parentdir_prefix):],
                     "full-revisionid": None,
-            "dirty": False, "error": None}
+                    "dirty": False, "error": None, "date": None}
+        else:
+            rootdirs.append(root)
+            root = os.path.dirname(root)  # up a level
+
+    if verbose:
+        print("Tried directories %s but none started with prefix %s" %
+              (str(rootdirs), parentdir_prefix))
+    raise NotThisMethod("rootdir doesn't start with parentdir_prefix")
 
 
 @register_vcs_handler("git", "get_keywords")
@@ -138,6 +148,10 @@ def git_get_keywords(versionfile_abs):
                 mo = re.search(r'=\s*"(.*)"', line)
                 if mo:
                     keywords["full"] = mo.group(1)
+            if line.strip().startswith("git_date ="):
+                mo = re.search(r'=\s*"(.*)"', line)
+                if mo:
+                    keywords["date"] = mo.group(1)
         f.close()
     except EnvironmentError:
         pass
@@ -149,6 +163,15 @@ def git_versions_from_keywords(keywords, tag_prefix, verbose):
     """Get version information from git keywords."""
     if not keywords:
         raise NotThisMethod("no keywords at all, weird")
+    date = keywords.get("date")
+    if date is not None:
+        # git-2.2.0 added "%cI", which expands to an ISO-8601 -compliant
+        # datestamp. However we prefer "%ci" (which expands to an "ISO-8601
+        # -like" string, which we must then edit to make compliant), because
+        # it's been around since git-1.5.3, and it's too difficult to
+        # discover which version we're using, or to work around using an
+        # older one.
+        date = date.strip().replace(" ", "T", 1).replace(" ", "", 1)
     refnames = keywords["refnames"].strip()
     if refnames.startswith("$Format"):
         if verbose:
@@ -169,7 +192,7 @@ def git_versions_from_keywords(keywords, tag_prefix, verbose):
         # "stabilization", as well as "HEAD" and "master".
         tags = set([r for r in refs if re.search(r'\d', r)])
         if verbose:
-            print("discarding '%s', no digits" % ",".join(refs-tags))
+            print("discarding '%s', no digits" % ",".join(refs - tags))
     if verbose:
         print("likely tags: %s" % ",".join(sorted(tags)))
     for ref in sorted(tags):
@@ -180,14 +203,14 @@ def git_versions_from_keywords(keywords, tag_prefix, verbose):
                 print("picking %s" % r)
             return {"version": r,
                     "full-revisionid": keywords["full"].strip(),
-                    "dirty": False, "error": None
-                    }
+                    "dirty": False, "error": None,
+                    "date": date}
     # no suitable tags, so version is "0+unknown", but full hex is still there
     if verbose:
         print("no suitable tags, using unknown + full revision id")
     return {"version": "0+unknown",
             "full-revisionid": keywords["full"].strip(),
-            "dirty": False, "error": "no suitable tags"}
+            "dirty": False, "error": "no suitable tags", "date": None}
 
 
 @register_vcs_handler("git", "pieces_from_vcs")
@@ -198,32 +221,35 @@ def git_pieces_from_vcs(tag_prefix, root, verbose, run_command=run_command):
     expanded, and _version.py hasn't already been rewritten with a short
     version string, meaning we're inside a checked out source tree.
     """
-    if not os.path.exists(os.path.join(root, ".git")):
-        if verbose:
-            print("no .git in %s" % root)
-        raise NotThisMethod("no .git directory")
-
     GITS = ["git"]
     if sys.platform == "win32":
         GITS = ["git.cmd", "git.exe"]
+
+    out, rc = run_command(GITS, ["rev-parse", "--git-dir"], cwd=root,
+                          hide_stderr=True)
+    if rc != 0:
+        if verbose:
+            print("Directory %s not under git control" % root)
+        raise NotThisMethod("'git rev-parse --git-dir' returned error")
+
     # if there is a tag matching tag_prefix, this yields TAG-NUM-gHEX[-dirty]
     # if there isn't one, this yields HEX[-dirty] (no NUM)
-    describe_out = run_command(GITS, ["describe", "--tags", "--dirty",
-                                      "--always", "--long",
+    describe_out, rc = run_command(GITS, ["describe", "--tags", "--dirty",
+                                          "--always", "--long", "--abbrev=8",
                                           "--match", "%s*" % tag_prefix],
                                    cwd=root)
     # --long was added in git-1.5.5
     if describe_out is None:
         raise NotThisMethod("'git describe' failed")
     describe_out = describe_out.strip()
-    full_out = run_command(GITS, ["rev-parse", "HEAD"], cwd=root)
+    full_out, rc = run_command(GITS, ["rev-parse", "HEAD"], cwd=root)
     if full_out is None:
         raise NotThisMethod("'git rev-parse' failed")
     full_out = full_out.strip()
 
     pieces = {}
     pieces["long"] = full_out
-    pieces["short"] = full_out[:7]  # maybe improved later
+    pieces["short"] = full_out[:8]  # maybe improved later
     pieces["error"] = None
 
     # parse describe_out. It will be like TAG-NUM-gHEX[-dirty] or HEX[-dirty]
@@ -267,10 +293,15 @@ def git_pieces_from_vcs(tag_prefix, root, verbose, run_command=run_command):
     else:
         # HEX: no tags
         pieces["closest-tag"] = None
-        count_out = run_command(GITS, ["rev-list", "HEAD", "--count"],
+        count_out, rc = run_command(GITS, ["rev-list", "HEAD", "--count"],
                                     cwd=root)
         pieces["distance"] = int(count_out)  # total number of commits
 
+    # commit date: see ISO-8601 comment in git_versions_from_keywords()
+    date = run_command(GITS, ["show", "-s", "--format=%ci", "HEAD"],
+                       cwd=root)[0].strip()
+    pieces["date"] = date.strip().replace(" ", "T", 1).replace(" ", "", 1)
+
     return pieces
 
 
@@ -417,7 +448,8 @@ def render(pieces, style):
         return {"version": "unknown",
                 "full-revisionid": pieces.get("long"),
                 "dirty": None,
-                "error": pieces["error"]}
+                "error": pieces["error"],
+                "date": None}
 
     if not style or style == "default":
         style = "pep440"  # the default
@@ -438,7 +470,8 @@ def render(pieces, style):
         raise ValueError("unknown style '%s'" % style)
 
     return {"version": rendered, "full-revisionid": pieces["long"],
-            "dirty": pieces["dirty"], "error": None}
+            "dirty": pieces["dirty"], "error": None,
+            "date": pieces.get("date")}
 
 
 def get_versions():
@@ -467,7 +500,8 @@ def get_versions():
     except NameError:
         return {"version": "0+unknown", "full-revisionid": None,
                 "dirty": None,
-                "error": "unable to find root of source tree"}
+                "error": "unable to find root of source tree",
+                "date": None}
 
     try:
         pieces = git_pieces_from_vcs(cfg.tag_prefix, root, verbose)
@@ -483,4 +517,4 @@ def get_versions():
 
     return {"version": "0+unknown", "full-revisionid": None,
             "dirty": None,
-            "error": "unable to compute version"}
+            "error": "unable to compute version", "date": None}

artiq/browser/experiments.py

@@ -9,7 +9,7 @@ import h5py
 
 from artiq import __artiq_dir__ as artiq_dir
 from artiq.gui.tools import LayoutWidget, log_level_to_name, get_open_file_name
-from artiq.gui.entries import argty_to_entry
+from artiq.gui.entries import procdesc_to_entry
 from artiq.protocols import pyon
 from artiq.master.worker import Worker, log_worker_exception
 
@@ -48,7 +48,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
         self.viewport().installEventFilter(_WheelFilter(self.viewport()))
 
         self._groups = dict()
-        self._arg_to_entry_widgetitem = dict()
+        self._arg_to_widgets = dict()
         self._dock = dock
 
         if not self._dock.arguments:
@@ -59,12 +59,13 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
         gradient.setColorAt(1, self.palette().midlight().color())
 
         for name, argument in self._dock.arguments.items():
-            try:
-                entry = argty_to_entry[argument["desc"]["ty"]](argument)
-            except:
-                print(name, argument)
+            widgets = dict()
+            self._arg_to_widgets[name] = widgets
+
+            entry = procdesc_to_entry(argument["desc"])(argument)
             widget_item = QtWidgets.QTreeWidgetItem([name])
-            self._arg_to_entry_widgetitem[name] = entry, widget_item
+            widgets["entry"] = entry
+            widgets["widget_item"] = widget_item
 
             for col in range(3):
                 widget_item.setBackground(col, gradient)
@@ -77,6 +78,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
             else:
                 self._get_group(argument["group"]).addChild(widget_item)
             fix_layout = LayoutWidget()
+            widgets["fix_layout"] = fix_layout
             fix_layout.addWidget(entry)
             self.setItemWidget(widget_item, 1, fix_layout)
 
@@ -146,16 +148,18 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
         argument = self._dock.arguments[name]
 
         procdesc = arginfo[name][0]
-        state = argty_to_entry[procdesc["ty"]].default_state(procdesc)
+        state = procdesc_to_entry(procdesc).default_state(procdesc)
         argument["desc"] = procdesc
         argument["state"] = state
 
-        old_entry, widget_item = self._arg_to_entry_widgetitem[name]
-        old_entry.deleteLater()
+        widgets = self._arg_to_widgets[name]
 
-        entry = argty_to_entry[procdesc["ty"]](argument)
-        self._arg_to_entry_widgetitem[name] = entry, widget_item
-        self.setItemWidget(widget_item, 1, entry)
+        widgets["entry"].deleteLater()
+        widgets["entry"] = procdesc_to_entry(procdesc)(argument)
+        widgets["fix_layout"] = LayoutWidget()
+        widgets["fix_layout"].addWidget(widgets["entry"])
+        self.setItemWidget(widgets["widget_item"], 1, widgets["fix_layout"])
+        self.updateGeometries()
 
     def save_state(self):
         expanded = []
@@ -314,7 +318,7 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
             "class_name": class_name,
             "log_level": self.options["log_level"],
             "arguments": {
-                name: argty_to_entry[argument["desc"]["ty"]].state_to_value(
+                name: procdesc_to_entry(argument["desc"]).state_to_value(
                     argument["state"])
                 for name, argument in self.arguments.items()},
         }
@@ -466,7 +470,7 @@ class ExperimentsArea(QtWidgets.QMdiArea):
     def initialize_submission_arguments(self, arginfo):
         arguments = OrderedDict()
         for name, (procdesc, group) in arginfo.items():
-            state = argty_to_entry[procdesc["ty"]].default_state(procdesc)
+            state = procdesc_to_entry(procdesc).default_state(procdesc)
             arguments[name] = {
                 "desc": procdesc,
                 "group": group,
@@ -500,6 +504,7 @@ class ExperimentsArea(QtWidgets.QMdiArea):
                            exc_info=True)
             dock = _ExperimentDock(self, expurl, {})
             asyncio.ensure_future(dock._recompute_arguments())
+        dock.setAttribute(QtCore.Qt.WA_DeleteOnClose)
         self.addSubWindow(dock)
         dock.show()
         dock.sigClosed.connect(partial(self.on_dock_closed, dock))

artiq/compiler/analyses/constness.py

@@ -17,6 +17,12 @@ class Constness(algorithm.Visitor):
         self.visit(node.targets)
         self.in_assign = False
 
+    def visit_SubscriptT(self, node):
+        old_in_assign, self.in_assign = self.in_assign, False
+        self.visit(node.value)
+        self.visit(node.slice)
+        self.in_assign = old_in_assign
+
     def visit_AttributeT(self, node):
         self.generic_visit(node)
         if self.in_assign:

artiq/compiler/builtins.py

@@ -126,10 +126,10 @@ def fn_int():
     return types.TConstructor(TInt())
 
 def fn_int32():
-    return types.TConstructor(TInt32())
+    return types.TBuiltinFunction("int32")
 
 def fn_int64():
-    return types.TConstructor(TInt64())
+    return types.TBuiltinFunction("int64")
 
 def fn_float():
     return types.TConstructor(TFloat())

artiq/compiler/embedding.py

@@ -15,7 +15,7 @@ from Levenshtein import ratio as similarity, jaro_winkler
 
 from ..language import core as language_core
 from . import types, builtins, asttyped, prelude
-from .transforms import ASTTypedRewriter, Inferencer, IntMonomorphizer
+from .transforms import ASTTypedRewriter, Inferencer, IntMonomorphizer, TypedtreePrinter
 from .transforms.asttyped_rewriter import LocalExtractor
 
 
@@ -85,6 +85,14 @@ class EmbeddingMap:
                 n += 1
                 new_instance_type.name = "{}.{}".format(new_instance_type.name, n)
 
+    def attribute_count(self):
+        count = 0
+        for host_type in self.type_map:
+            instance_type, constructor_type = self.type_map[host_type]
+            count += len(instance_type.attributes)
+            count += len(constructor_type.attributes)
+        return count
+
     # Functions
     def store_function(self, function, ir_function_name):
         self.function_map[function] = ir_function_name
@@ -382,23 +390,6 @@ class ASTSynthesizer:
 
         return node
 
-    def assign_attribute(self, obj, attr_name, value):
-        obj_node   = self.quote(obj)
-        dot_loc    = self._add(".")
-        name_loc   = self._add(attr_name)
-        _          = self._add(" ")
-        equals_loc = self._add("=")
-        _          = self._add(" ")
-        value_node = self.quote(value)
-
-        attr_node  = asttyped.AttributeT(value=obj_node, attr=attr_name, ctx=None,
-                                         type=value_node.type,
-                                         dot_loc=dot_loc, attr_loc=name_loc,
-                                         loc=obj_node.loc.join(name_loc))
-
-        return ast.Assign(targets=[attr_node], value=value_node,
-                          op_locs=[equals_loc], loc=name_loc.join(value_node.loc))
-
 
 def suggest_identifier(id, names):
     sorted_names = sorted(names, key=lambda other: jaro_winkler(id, other), reverse=True)
@@ -561,7 +552,13 @@ class StitchingInferencer(Inferencer):
         # of having the host-to-ARTIQ mapping code in only one place and
         # also immediately getting proper diagnostics on type errors.
         attr_value = getattr(object_value, attr_name)
-        if inspect.ismethod(attr_value) and types.is_instance(object_type):
+        if (inspect.ismethod(attr_value) and
+                types.is_instance(object_type) and
+                # Check that the method is indeed defined on the class,
+                # and not just this instance. The check is written in
+                # the inverted form and not as hasattr(type(attr_value))
+                # since the method may as well be defined on a superclass.
+                attr_name not in object_value.__dict__):
             # In cases like:
             #     class c:
             #         @kernel
@@ -671,6 +668,8 @@ class TypedtreeHasher(algorithm.Visitor):
         def freeze(obj):
             if isinstance(obj, ast.AST):
                 return self.visit(obj)
+            elif isinstance(obj, list):
+                return hash(tuple(freeze(elem) for elem in obj))
             elif isinstance(obj, types.Type):
                 return hash(obj.find())
             else:
@@ -683,7 +682,7 @@ class TypedtreeHasher(algorithm.Visitor):
         return hash(tuple(freeze(getattr(node, field_name)) for field_name in fields))
 
 class Stitcher:
-    def __init__(self, core, dmgr, engine=None):
+    def __init__(self, core, dmgr, engine=None, print_as_rpc=True):
         self.core = core
         self.dmgr = dmgr
         if engine is None:
@@ -699,6 +698,7 @@ class Stitcher:
         # We don't want some things from the prelude as they are provided in
         # the host Python namespace and gain special meaning when quoted.
         self.prelude = prelude.globals()
+        if print_as_rpc:
             self.prelude.pop("print")
         self.prelude.pop("array")
 
@@ -719,22 +719,48 @@ class Stitcher:
         inferencer = StitchingInferencer(engine=self.engine,
                                          value_map=self.value_map,
                                          quote=self._quote)
-        hasher = TypedtreeHasher()
+        typedtree_hasher = TypedtreeHasher()
 
         # Iterate inference to fixed point.
         old_typedtree_hash = None
+        old_attr_count = None
         while True:
             inferencer.visit(self.typedtree)
-            typedtree_hash = hasher.visit(self.typedtree)
+            typedtree_hash = typedtree_hasher.visit(self.typedtree)
+            attr_count = self.embedding_map.attribute_count()
 
-            if old_typedtree_hash == typedtree_hash:
+            if old_typedtree_hash == typedtree_hash and old_attr_count == attr_count:
                 break
             old_typedtree_hash = typedtree_hash
+            old_attr_count = attr_count
 
-        # When we have an excess of type information, sometimes we can infer every type
-        # in the AST without discovering every referenced attribute of host objects, so
-        # do one last pass unconditionally.
-        inferencer.visit(self.typedtree)
+        # After we've discovered every referenced attribute, check if any kernel_invariant
+        # specifications refers to ones we didn't encounter.
+        for host_type in self.embedding_map.type_map:
+            instance_type, constructor_type = self.embedding_map.type_map[host_type]
+            if not hasattr(instance_type, "constant_attributes"):
+                # Exceptions lack user-definable attributes.
+                continue
+
+            for attribute in instance_type.constant_attributes:
+                if attribute in instance_type.attributes:
+                    # Fast path; if the ARTIQ Python type has the attribute, then every observed
+                    # value is guaranteed to have it too.
+                    continue
+
+                for value, loc in self.value_map[instance_type]:
+                    if hasattr(value, attribute):
+                        continue
+
+                    diag = diagnostic.Diagnostic("warning",
+                        "object {value} of type {typ} declares attribute '{attr}' as "
+                        "kernel invariant, but the instance referenced here does not "
+                        "have this attribute",
+                        {"value": repr(value),
+                         "typ": types.TypePrinter().name(instance_type, max_depth=0),
+                         "attr": attribute},
+                        loc)
+                    self.engine.process(diag)
 
         # After we have found all functions, synthesize a module to hold them.
         source_buffer = source.Buffer("", "<synthesized>")

artiq/compiler/import_cache.py

@@ -29,7 +29,10 @@ def hook_exec_module(self, module):
         fn = module.__file__
         try:
             with tokenize.open(fn) as fp:
-                cache[fn] = fp.readlines()
+                lines = fp.readlines()
+            if lines and not lines[-1].endswith("\n"):
+                lines[-1] += "\n"
+            cache[fn] = lines
         except:
             logger.warning("failed to add '%s' to cache", fn, exc_info=True)
         else:

artiq/compiler/module.py

@@ -40,7 +40,8 @@ class Source:
             return cls(source.Buffer(f.read(), filename, 1), engine=engine)
 
 class Module:
-    def __init__(self, src, ref_period=1e-6):
+    def __init__(self, src, ref_period=1e-6, attribute_writeback=True):
+        self.attribute_writeback = attribute_writeback
         self.engine = src.engine
         self.embedding_map = src.embedding_map
         self.name = src.name
@@ -79,7 +80,8 @@ class Module:
         llvm_ir_generator = transforms.LLVMIRGenerator(
             engine=self.engine, module_name=self.name, target=target,
             embedding_map=self.embedding_map)
-        return llvm_ir_generator.process(self.artiq_ir, attribute_writeback=True)
+        return llvm_ir_generator.process(self.artiq_ir,
+            attribute_writeback=self.attribute_writeback)
 
     def entry_point(self):
         """Return the name of the function that is the entry point of this module."""

artiq/compiler/prelude.py

@@ -14,6 +14,8 @@ def globals():
         "list":                 builtins.fn_list(),
         "array":                builtins.fn_array(),
         "range":                builtins.fn_range(),
+        "int32":                builtins.fn_int32(),
+        "int64":                builtins.fn_int64(),
 
         # Exception constructors
         "Exception":            builtins.fn_Exception(),

artiq/compiler/transforms/__init__.py

@@ -6,3 +6,4 @@ from .artiq_ir_generator import ARTIQIRGenerator
 from .dead_code_eliminator import DeadCodeEliminator
 from .llvm_ir_generator import LLVMIRGenerator
 from .interleaver import Interleaver
+from .typedtree_printer import TypedtreePrinter

artiq/compiler/transforms/artiq_ir_generator.py

@@ -317,7 +317,15 @@ class ARTIQIRGenerator(algorithm.Visitor):
                     self.current_block.append(ir.Return(ir.Constant(None, builtins.TNone())))
             else:
                 if not self.current_block.is_terminated():
+                    if len(self.current_block.predecessors()) != 0:
+                        diag = diagnostic.Diagnostic("error",
+                            "this function must return a value of type {typ} explicitly",
+                            {"typ": types.TypePrinter().name(typ.ret)},
+                            node.keyword_loc)
+                        self.engine.process(diag)
+
                     self.current_block.append(ir.Unreachable())
+
         finally:
             self.name = old_name
             self.current_args = old_args
@@ -443,6 +451,7 @@ class ARTIQIRGenerator(algorithm.Visitor):
             self.current_block = head
             old_continue, self.continue_target = self.continue_target, head
             cond = self.visit(node.test)
+            cond = self.coerce_to_bool(cond)
             post_head = self.current_block
 
             break_block = self.add_block("while.break")
@@ -452,6 +461,9 @@ class ARTIQIRGenerator(algorithm.Visitor):
             self.current_block = body
             self.visit(node.body)
             post_body = self.current_block
+        finally:
+            self.break_target = old_break
+            self.continue_target = old_continue
 
         if any(node.orelse):
             else_tail = self.add_block("while.else")
@@ -472,9 +484,6 @@ class ARTIQIRGenerator(algorithm.Visitor):
         if not post_body.is_terminated():
             post_body.append(ir.Branch(head))
         break_block.append(ir.Branch(tail))
-        finally:
-            self.break_target = old_break
-            self.continue_target = old_continue
 
     def iterable_len(self, value, typ=_size_type):
         if builtins.is_listish(value.type):
@@ -482,8 +491,9 @@ class ARTIQIRGenerator(algorithm.Visitor):
                 name = None
             else:
                 name = "{}.len".format(value.name)
-            return self.append(ir.Builtin("len", [value], typ,
+            len = self.append(ir.Builtin("len", [value], builtins.TInt32(),
                                          name=name))
+            return self.append(ir.Coerce(len, typ))
         elif builtins.is_range(value.type):
             start  = self.append(ir.GetAttr(value, "start"))
             stop   = self.append(ir.GetAttr(value, "stop"))
@@ -541,6 +551,9 @@ class ARTIQIRGenerator(algorithm.Visitor):
                 self.current_assign = None
             self.visit(node.body)
             post_body = self.current_block
+        finally:
+            self.break_target = old_break
+            self.continue_target = old_continue
 
         if any(node.orelse):
             else_tail = self.add_block("for.else")
@@ -564,9 +577,6 @@ class ARTIQIRGenerator(algorithm.Visitor):
         if not post_body.is_terminated():
             post_body.append(ir.Branch(continue_block))
         break_block.append(ir.Branch(tail))
-        finally:
-            self.break_target = old_break
-            self.continue_target = old_continue
 
     def visit_Break(self, node):
         self.append(ir.Branch(self.break_target))
@@ -1279,6 +1289,10 @@ class ARTIQIRGenerator(algorithm.Visitor):
             return self.append(ir.Select(cond,
                         ir.Constant(False, builtins.TBool()),
                         ir.Constant(True,  builtins.TBool())))
+        elif isinstance(node.op, ast.Invert):
+            operand = self.visit(node.operand)
+            return self.append(ir.Arith(ast.BitXor(loc=None),
+                                        ir.Constant(-1, operand.type), operand))
         elif isinstance(node.op, ast.USub):
             operand = self.visit(node.operand)
             return self.append(ir.Arith(ast.Sub(loc=None),
@@ -1309,7 +1323,7 @@ class ARTIQIRGenerator(algorithm.Visitor):
                     lambda: self.alloc_exn(builtins.TException("ValueError"),
                         ir.Constant("shift amount must be nonnegative", builtins.TStr())),
                     loc=node.right.loc)
-            elif isinstance(node.op, (ast.Div, ast.FloorDiv)):
+            elif isinstance(node.op, (ast.Div, ast.FloorDiv, ast.Mod)):
                 self._make_check(
                     self.append(ir.Compare(ast.NotEq(loc=None), rhs, ir.Constant(0, rhs.type))),
                     lambda: self.alloc_exn(builtins.TException("ZeroDivisionError"),
@@ -1599,7 +1613,8 @@ class ARTIQIRGenerator(algorithm.Visitor):
                 return self.coerce_to_bool(arg)
             else:
                 assert False
-        elif types.is_builtin(typ, "int"):
+        elif types.is_builtin(typ, "int") or \
+                types.is_builtin(typ, "int32") or types.is_builtin(typ, "int64"):
             if len(node.args) == 0 and len(node.keywords) == 0:
                 return ir.Constant(0, node.type)
             elif len(node.args) == 1 and \
@@ -1723,7 +1738,7 @@ class ARTIQIRGenerator(algorithm.Visitor):
             if len(node.args) == 1 and len(node.keywords) == 0:
                 arg = self.visit(node.args[0])
                 arg_mu_float = self.append(ir.Arith(ast.Div(loc=None), arg, self.ref_period))
-                arg_mu = self.append(ir.Coerce(arg_mu_float, builtins.TInt64()))
+                arg_mu = self.append(ir.Builtin("round", [arg_mu_float], builtins.TInt64()))
                 return self.append(ir.Builtin("delay_mu", [arg_mu], builtins.TNone()))
             else:
                 assert False

artiq/compiler/transforms/inferencer.py

@@ -5,6 +5,7 @@
 from collections import OrderedDict
 from pythonparser import algorithm, diagnostic, ast
 from .. import asttyped, types, builtins
+from .typedtree_printer import TypedtreePrinter
 
 class Inferencer(algorithm.Visitor):
     """
@@ -293,7 +294,8 @@ class Inferencer(algorithm.Visitor):
             return coerced_node
         elif isinstance(coerced_node, asttyped.CoerceT):
             node = coerced_node
-            node.type, node.other_value = typ, other_node
+            node.type.unify(typ)
+            node.other_value = other_node
         else:
             node = asttyped.CoerceT(type=typ, value=coerced_node, other_value=other_node,
                                     loc=coerced_node.loc)
@@ -622,14 +624,28 @@ class Inferencer(algorithm.Visitor):
 
             self._unify(node.type, builtins.TBool(),
                         node.loc, None)
-        elif types.is_builtin(typ, "int"):
+        elif types.is_builtin(typ, "int") or \
+                types.is_builtin(typ, "int32") or types.is_builtin(typ, "int64"):
+            if types.is_builtin(typ, "int"):
                 valid_forms = lambda: [
                     valid_form("int() -> numpy.int?"),
-                valid_form("int(x:'a) -> numpy.int?"),
-                valid_form("int(x:'a, width=?) -> numpy.int?")
+                    valid_form("int(x:'a) -> numpy.int? where 'a is numeric")
                 ]
+                result_typ = builtins.TInt()
+            elif types.is_builtin(typ, "int32"):
+                valid_forms = lambda: [
+                    valid_form("numpy.int32() -> numpy.int32"),
+                    valid_form("numpy.int32(x:'a) -> numpy.int32 where 'a is numeric")
+                ]
+                result_typ = builtins.TInt32()
+            elif types.is_builtin(typ, "int64"):
+                valid_forms = lambda: [
+                    valid_form("numpy.int64() -> numpy.int64"),
+                    valid_form("numpy.int64(x:'a) -> numpy.int64 where 'a is numeric")
+                ]
+                result_typ = builtins.TInt64()
 
-            self._unify(node.type, builtins.TInt(),
+            self._unify(node.type, result_typ,
                         node.loc, None)
 
             if len(node.args) == 0 and len(node.keywords) == 0:
@@ -639,20 +655,7 @@ class Inferencer(algorithm.Visitor):
                 pass # undetermined yet
             elif len(node.args) == 1 and len(node.keywords) == 0 and \
                     builtins.is_numeric(node.args[0].type):
-                self._unify(node.type, builtins.TInt(),
-                            node.loc, None)
-            elif len(node.args) == 1 and len(node.keywords) == 1 and \
-                    builtins.is_numeric(node.args[0].type) and \
-                    node.keywords[0].arg == 'width':
-                width = node.keywords[0].value
-                if not (isinstance(width, asttyped.NumT) and isinstance(width.n, int)):
-                    diag = diagnostic.Diagnostic("error",
-                        "the width argument of int() must be an integer literal", {},
-                        node.keywords[0].loc)
-                    self.engine.process(diag)
-                    return
-
-                self._unify(node.type, builtins.TInt(types.TValue(width.n)),
+                self._unify(node.type, result_typ,
                             node.loc, None)
             else:
                 diagnose(valid_forms())
@@ -1049,22 +1052,10 @@ class Inferencer(algorithm.Visitor):
         if coerced:
             return_type, target_type, value_type = coerced
 
-            try:
-                node.target.type.unify(target_type)
-            except types.UnificationError as e:
-                printer = types.TypePrinter()
-                note = diagnostic.Diagnostic("note",
-                    "expression of type {typec}",
-                    {"typec": printer.name(node.value.type)},
-                    node.value.loc)
-                diag = diagnostic.Diagnostic("error",
-                    "expression of type {typea} has to be coerced to {typeb}, "
-                    "which makes assignment invalid",
-                    {"typea": printer.name(node.target.type),
-                     "typeb": printer.name(target_type)},
-                    node.op.loc, [node.target.loc], [note])
-                self.engine.process(diag)
-                return
+            if isinstance(node.value, asttyped.CoerceT):
+                orig_value_type = node.value.value.type
+            else:
+                orig_value_type = node.value.type
 
             try:
                 node.target.type.unify(return_type)
@@ -1072,17 +1063,34 @@ class Inferencer(algorithm.Visitor):
                 printer = types.TypePrinter()
                 note = diagnostic.Diagnostic("note",
                     "expression of type {typec}",
-                    {"typec": printer.name(node.value.type)},
+                    {"typec": printer.name(orig_value_type)},
                     node.value.loc)
                 diag = diagnostic.Diagnostic("error",
                     "the result of this operation has type {typeb}, "
-                    "which makes assignment to a slot of type {typea} invalid",
+                    "which cannot be assigned to a left-hand side of type {typea}",
                     {"typea": printer.name(node.target.type),
                      "typeb": printer.name(return_type)},
                     node.op.loc, [node.target.loc], [note])
                 self.engine.process(diag)
                 return
 
+            try:
+                node.target.type.unify(target_type)
+            except types.UnificationError as e:
+                printer = types.TypePrinter()
+                note = diagnostic.Diagnostic("note",
+                    "expression of type {typec}",
+                    {"typec": printer.name(orig_value_type)},
+                    node.value.loc)
+                diag = diagnostic.Diagnostic("error",
+                    "this operation requires the left-hand side of type {typea} "
+                    "to be coerced to {typeb}, which cannot be done",
+                    {"typea": printer.name(node.target.type),
+                     "typeb": printer.name(target_type)},
+                    node.op.loc, [node.target.loc], [note])
+                self.engine.process(diag)
+                return
+
             node.value = self._coerce_one(value_type, node.value, other_node=node.target)
 
     def visit_ForT(self, node):

artiq/compiler/transforms/int_monomorphizer.py

@@ -5,7 +5,7 @@ do not.
 """
 
 from pythonparser import algorithm, diagnostic
-from .. import types, builtins
+from .. import types, builtins, asttyped
 
 class IntMonomorphizer(algorithm.Visitor):
     def __init__(self, engine):
@@ -35,3 +35,13 @@ class IntMonomorphizer(algorithm.Visitor):
             typ = node.type.find()
             if types.is_var(typ["width"]):
                 typ["width"].unify(types.TValue(32))
+
+    def visit_CoerceT(self, node):
+        if isinstance(node.value, asttyped.NumT) and \
+                builtins.is_int(node.type) and \
+                builtins.is_int(node.value.type) and \
+                not types.is_var(node.type["width"]) and \
+                types.is_var(node.value.type["width"]):
+            node.value.type.unify(node.type)
+
+        self.generic_visit(node)

artiq/compiler/transforms/llvm_ir_generator.py

@@ -334,6 +334,12 @@ class LLVMIRGenerator:
             llty = ll.FunctionType(llptr, [])
         elif name == "llvm.stackrestore":
             llty = ll.FunctionType(llvoid, [llptr])
+        elif name == "__py_modsi3":
+            llty = ll.FunctionType(lli32, [lli32, lli32])
+        elif name == "__py_moddi3":
+            llty = ll.FunctionType(lli64, [lli64, lli64])
+        elif name == "__py_moddf3":
+            llty = ll.FunctionType(lldouble, [lldouble, lldouble])
         elif name == self.target.print_function:
             llty = ll.FunctionType(llvoid, [llptr], var_arg=True)
         elif name == "rtio_log":
@@ -369,11 +375,94 @@ class LLVMIRGenerator:
             if name in ("rtio_log", "send_rpc", "watchdog_set", "watchdog_clear",
                         self.target.print_function):
                 llglobal.attributes.add("nounwind")
+            if name.find("__py_") == 0:
+                llglobal.linkage = 'linkonce_odr'
+                self.emit_intrinsic(name, llglobal)
         else:
             llglobal = ll.GlobalVariable(self.llmodule, llty, name)
 
         return llglobal
 
+    def emit_intrinsic(self, name, llfun):
+        llbuilder = ll.IRBuilder()
+        llbuilder.position_at_end(llfun.append_basic_block("entry"))
+
+        if name == "__py_modsi3" or name == "__py_moddi3":
+            if name == "__py_modsi3":
+                llty = lli32
+            elif name == "__py_moddi3":
+                llty = lli64
+            else:
+                assert False
+
+            """
+            Reference Objects/intobject.c
+                xdivy = x / y;
+                xmody = (long)(x - (unsigned long)xdivy * y);
+                /* If the signs of x and y differ, and the remainder is non-0,
+                 * C89 doesn't define whether xdivy is now the floor or the
+                 * ceiling of the infinitely precise quotient.  We want the floor,
+                 * and we have it iff the remainder's sign matches y's.
+                 */
+                if (xmody && ((y ^ xmody) < 0) /* i.e. and signs differ */) {
+                    xmody += y;
+                    // ...
+                }
+            """
+            llx, lly = llfun.args
+            llxdivy = llbuilder.sdiv(llx, lly)
+            llxremy = llbuilder.srem(llx, lly)
+
+            llxmodynonzero = llbuilder.icmp_signed('!=', llxremy, ll.Constant(llty, 0))
+            lldiffsign = llbuilder.icmp_signed('<', llbuilder.xor(llx, lly), ll.Constant(llty, 0))
+
+            llcond = llbuilder.and_(llxmodynonzero, lldiffsign)
+            with llbuilder.if_then(llcond):
+                llbuilder.ret(llbuilder.add(llxremy, lly))
+            llbuilder.ret(llxremy)
+        elif name == "__py_moddf3":
+            """
+            Reference Objects/floatobject.c
+                mod = fmod(vx, wx);
+                /* fmod is typically exact, so vx-mod is *mathematically* an
+                   exact multiple of wx.  But this is fp arithmetic, and fp
+                   vx - mod is an approximation; the result is that div may
+                   not be an exact integral value after the division, although
+                   it will always be very close to one.
+                */
+                // ...
+                if (mod) {
+                    /* ensure the remainder has the same sign as the denominator */
+                    if ((wx < 0) != (mod < 0)) {
+                        mod += wx;
+                        // ...
+                    }
+                }
+                else {
+                    /* the remainder is zero, and in the presence of signed zeroes
+                       fmod returns different results across platforms; ensure
+                       it has the same sign as the denominator; we'd like to do
+                       "mod = wx * 0.0", but that may get optimized away */
+                    mod *= mod;  /* hide "mod = +0" from optimizer */
+                    if (wx < 0.0)
+                        mod = -mod;
+                }
+            """
+            llv, llw = llfun.args
+            llrem = llbuilder.frem(llv, llw)
+
+            llremnonzero = llbuilder.fcmp_unordered('!=', llrem, ll.Constant(lldouble, 0.0))
+            llwltzero = llbuilder.fcmp_ordered('<', llw, ll.Constant(lldouble, 0.0))
+            llremltzero = llbuilder.fcmp_ordered('<', llrem, ll.Constant(lldouble, 0.0))
+            lldiffsign = llbuilder.icmp_unsigned('!=', llwltzero, llremltzero)
+
+            llcond = llbuilder.and_(llremnonzero, lldiffsign)
+            with llbuilder.if_then(llcond):
+                llbuilder.ret(llbuilder.fadd(llrem, llw))
+            llbuilder.ret(llrem)
+        else:
+            assert False
+
     def get_function(self, typ, name):
         llfun = self.llmodule.get_global(name)
         if llfun is None:
@@ -849,6 +938,8 @@ class LLVMIRGenerator:
 
     def process_Coerce(self, insn):
         typ, value_typ = insn.type, insn.value().type
+        if typ == value_typ:
+            return self.map(insn.value())
         if builtins.is_int(typ) and builtins.is_float(value_typ):
             return self.llbuilder.fptosi(self.map(insn.value()), self.llty_of_type(typ),
                                          name=insn.name)
@@ -920,22 +1011,15 @@ class LLVMIRGenerator:
                 return self.llbuilder.sdiv(self.map(insn.lhs()), self.map(insn.rhs()),
                                            name=insn.name)
         elif isinstance(insn.op, ast.Mod):
-            # Python only has the modulo operator, LLVM only has the remainder
-            if builtins.is_float(insn.type):
-                llvalue = self.llbuilder.frem(self.map(insn.lhs()), self.map(insn.rhs()))
-                self.add_fast_math_flags(llvalue)
-                return self.llbuilder.call(self.llbuiltin("llvm.copysign.f64"),
-                                           [llvalue, self.map(insn.rhs())],
-                                           name=insn.name)
-            else:
             lllhs, llrhs = map(self.map, (insn.lhs(), insn.rhs()))
-                llxorsign = self.llbuilder.and_(self.llbuilder.xor(lllhs, llrhs),
-                                                ll.Constant(lllhs.type, 1 << lllhs.type.width - 1))
-                llnegate = self.llbuilder.icmp_unsigned('!=',
-                                                        llxorsign, ll.Constant(llxorsign.type, 0))
-                llvalue = self.llbuilder.srem(lllhs, llrhs)
-                llnegvalue = self.llbuilder.sub(ll.Constant(llvalue.type, 0), llvalue)
-                return self.llbuilder.select(llnegate, llnegvalue, llvalue)
+            if builtins.is_float(insn.type):
+                intrinsic = "__py_moddf3"
+            elif builtins.is_int32(insn.type):
+                intrinsic = "__py_modsi3"
+            elif builtins.is_int64(insn.type):
+                intrinsic = "__py_moddi3"
+            return self.llbuilder.call(self.llbuiltin(intrinsic), [lllhs, llrhs],
+                                       name=insn.name)
         elif isinstance(insn.op, ast.Pow):
             if builtins.is_float(insn.type):
                 return self.llbuilder.call(self.llbuiltin("llvm.pow.f64"),
@@ -1252,10 +1336,12 @@ class LLVMIRGenerator:
         self.llbuilder.call(self.llbuiltin("llvm.stackrestore"), [llstackptr])
 
         # T result = {
-        #   void *ptr = NULL;
-        #   loop: int size = rpc_recv("tag", ptr);
+        #   void *ret_ptr = alloca(sizeof(T));
+        #   void *ptr = ret_ptr;
+        #   loop: int size = recv_rpc(ptr);
+        #   // Non-zero: Provide `size` bytes of extra storage for variable-length data.
         #   if(size) { ptr = alloca(size); goto loop; }
-        #   else *(T*)ptr
+        #   else *(T*)ret_ptr
         # }
         llprehead   = self.llbuilder.basic_block
         llhead      = self.llbuilder.append_basic_block(name="rpc.head")
@@ -1270,7 +1356,7 @@ class LLVMIRGenerator:
         self.llbuilder.branch(llhead)
 
         self.llbuilder.position_at_end(llhead)
-        llphi = self.llbuilder.phi(llslotgen.type, name="rpc.size")
+        llphi = self.llbuilder.phi(llslotgen.type, name="rpc.ptr")
         llphi.add_incoming(llslotgen, llprehead)
         if llunwindblock:
             llsize = self.llbuilder.invoke(self.llbuiltin("recv_rpc"), [llphi],

artiq/compiler/transforms/typedtree_printer.py

@@ -0,0 +1,89 @@
+"""
+:class:`TypedtreePrinter` prints a human-readable representation of typedtrees.
+"""
+
+from pythonparser import algorithm, ast
+from .. import types, asttyped
+
+class TypedtreePrinter(algorithm.Visitor):
+    def __init__(self):
+        self.str = None
+        self.level = None
+        self.last_nl = None
+        self.type_printer = None
+
+    def print(self, node):
+        try:
+            self.str = ""
+            self.level = 0
+            self.last_nl = 0
+            self.type_printer = types.TypePrinter()
+            self.visit(node)
+            self._nl()
+            return self.str
+        finally:
+            self.str = None
+            self.level = None
+            self.last_nl = 0
+            self.type_printer = None
+
+    def _nl(self):
+        # self.str += "·"
+        if len(self.str) != self.last_nl:
+            self.str += "\n" + ("  " * self.level)
+            self.last_nl = len(self.str)
+
+    def _indent(self):
+        self.level += 1
+        self._nl()
+
+    def _dedent(self):
+        self._nl()
+        self.level -= 1
+        self.str = self.str[:-2]
+        self.last_nl -= 2
+
+    def visit(self, obj):
+        if isinstance(obj, ast.AST):
+            attrs = set(obj._fields) - {'ctx'}
+            if isinstance(obj, asttyped.commontyped):
+                attrs.update(set(obj._types))
+
+            for attr in set(attrs):
+                if not getattr(obj, attr):
+                    attrs.remove(attr) # omit falsey stuff
+
+            self.str += obj.__class__.__name__ + "("
+            if len(attrs) > 1:
+                self._indent()
+
+            for attr in attrs:
+                if len(attrs) > 1:
+                    self._nl()
+                self.str += attr + "="
+                self.visit(getattr(obj, attr))
+                if len(attrs) > 1:
+                    self._nl()
+
+            if len(attrs) > 1:
+                self._dedent()
+            self.str += ")"
+        elif isinstance(obj, types.Type):
+            self.str += self.type_printer.name(obj, max_depth=0)
+        elif isinstance(obj, list):
+            self.str += "["
+            if len(obj) > 1:
+                self._indent()
+
+            for elem in obj:
+                if len(obj) > 1:
+                    self._nl()
+                self.visit(elem)
+                if len(obj) > 1:
+                    self._nl()
+
+            if len(obj) > 1:
+                self._dedent()
+            self.str += "]"
+        else:
+            self.str += repr(obj)

artiq/compiler/types.py

@@ -194,6 +194,9 @@ class TTuple(Type):
     def __ne__(self, other):
         return not (self == other)
 
+    def __hash__(self):
+        return hash(tuple(self.elts))
+
 class _TPointer(TMono):
     def __init__(self):
         super().__init__("pointer")

artiq/compiler/validators/escape.py

@@ -298,8 +298,8 @@ class EscapeValidator(algorithm.Visitor):
     # and exceptions can only refer to strings, so we don't actually check
     # this property. But we will need to, if string operations are ever added.
 
-    def visit_assignment(self, target, value, is_aug_assign=False):
-        value_region  = self._region_of(value) if not is_aug_assign else self.youngest_region
+    def visit_assignment(self, target, value):
+        value_region  = self._region_of(value)
 
         # If this is a variable, we might need to contract the live range.
         if isinstance(value_region, Region):
@@ -316,19 +316,11 @@ class EscapeValidator(algorithm.Visitor):
         target_regions = [self._region_of(name) for name in target_names]
         for target_region in target_regions:
             if not Region.outlives(value_region, target_region):
-                if is_aug_assign:
-                    target_desc = "the assignment target, allocated here,"
-                else:
-                    target_desc = "the assignment target"
-                note = diagnostic.Diagnostic("note",
-                    "this expression has type {type}",
-                    {"type": types.TypePrinter().name(value.type)},
-                    value.loc)
                 diag = diagnostic.Diagnostic("error",
                     "the assigned value does not outlive the assignment target", {},
                     value.loc, [target.loc],
                     notes=self._diagnostics_for(target_region, target.loc,
-                                                target_desc) +
+                                                "the assignment target") +
                           self._diagnostics_for(value_region, value.loc,
                                                 "the assigned value"))
                 self.engine.process(diag)
@@ -339,9 +331,19 @@ class EscapeValidator(algorithm.Visitor):
 
     def visit_AugAssign(self, node):
         if builtins.is_allocated(node.target.type):
-            # If the target is mutable, op-assignment will allocate
-            # in the youngest region.
-            self.visit_assignment(node.target, node.value, is_aug_assign=True)
+            note = diagnostic.Diagnostic("note",
+                "try using `{lhs} = {lhs} {op} {rhs}` instead",
+                {"lhs": node.target.loc.source(),
+                 "rhs": node.value.loc.source(),
+                 "op": node.op.loc.source()[:-1]},
+                node.loc)
+            diag = diagnostic.Diagnostic("error",
+                "values cannot be mutated in-place", {},
+                node.op.loc, [node.target.loc],
+                notes=[note])
+            self.engine.process(diag)
+
+        self.visit_assignment(node.target, node.value)
 
     def visit_Return(self, node):
         region = self._region_of(node.value)

artiq/coredevice/analyzer.py

@@ -263,7 +263,7 @@ def _extract_log_chars(data):
         n = data >> 24
         data = (data << 8) & 0xffffffff
         if not n:
-            return r
+            continue
         r += chr(n)
     return r
 

artiq/coredevice/comm_generic.py

@@ -233,8 +233,7 @@ class CommGeneric:
             raise UnsupportedDevice("Unsupported runtime ID: {}"
                                     .format(runtime_id))
         gateware_version = self._read_chunk(self._read_length).decode("utf-8")
-        if gateware_version != software_version and \
-                gateware_version + ".dirty" != software_version:
+        if gateware_version != software_version:
             logger.warning("Mismatch between gateware (%s) "
                            "and software (%s) versions",
                            gateware_version, software_version)
@@ -396,11 +395,13 @@ class CommGeneric:
                   lambda: "bool")
             self._write_int8(value)
         elif tag == "i":
-            check(isinstance(value, int) and (-2**31 < value < 2**31-1),
+            check(isinstance(value, (int, numpy.int32)) and
+                  (-2**31 < value < 2**31-1),
                   lambda: "32-bit int")
             self._write_int32(value)
         elif tag == "I":
-            check(isinstance(value, int) and (-2**63 < value < 2**63-1),
+            check(isinstance(value, (int, numpy.int32, numpy.int64)) and
+                  (-2**63 < value < 2**63-1),
                   lambda: "64-bit int")
             self._write_int64(value)
         elif tag == "f":

artiq/coredevice/core.py

@@ -81,15 +81,19 @@ class Core:
         self.core = self
         self.comm.core = self
 
-    def compile(self, function, args, kwargs, set_result=None, with_attr_writeback=True):
+    def compile(self, function, args, kwargs, set_result=None,
+                attribute_writeback=True, print_as_rpc=True):
         try:
             engine = _DiagnosticEngine(all_errors_are_fatal=True)
 
-            stitcher = Stitcher(engine=engine, core=self, dmgr=self.dmgr)
+            stitcher = Stitcher(engine=engine, core=self, dmgr=self.dmgr,
+                                print_as_rpc=print_as_rpc)
             stitcher.stitch_call(function, args, kwargs, set_result)
             stitcher.finalize()
 
-            module = Module(stitcher, ref_period=self.ref_period)
+            module = Module(stitcher,
+                ref_period=self.ref_period,
+                attribute_writeback=attribute_writeback)
             target = OR1KTarget()
 
             library = target.compile_and_link([module])

artiq/coredevice/dds.py

@@ -1,6 +1,7 @@
 from artiq.language.core import *
 from artiq.language.types import *
 from artiq.language.units import *
+from numpy import int64
 
 
 _PHASE_MODE_DEFAULT = -1
@@ -111,20 +112,20 @@ class _DDSGeneric:
         """Returns the frequency tuning word corresponding to the given
         frequency.
         """
-        return round(int(2, width=64)**32*frequency/self.core_dds.sysclk)
+        return round(float(int64(2)**32*frequency/self.core_dds.sysclk))
 
     @portable(flags=["fast-math"])
     def ftw_to_frequency(self, ftw):
         """Returns the frequency corresponding to the given frequency tuning
         word.
         """
-        return ftw*self.core_dds.sysclk/int(2, width=64)**32
+        return ftw*self.core_dds.sysclk/int64(2)**32
 
     @portable(flags=["fast-math"])
     def turns_to_pow(self, turns):
         """Returns the phase offset word corresponding to the given phase
         in turns."""
-        return round(turns*2**self.pow_width)
+        return round(float(turns*2**self.pow_width))
 
     @portable(flags=["fast-math"])
     def pow_to_turns(self, pow):
@@ -135,7 +136,7 @@ class _DDSGeneric:
     @portable(flags=["fast-math"])
     def amplitude_to_asf(self, amplitude):
         """Returns amplitude scale factor corresponding to given amplitude."""
-        return round(amplitude*0x0fff)
+        return round(float(amplitude*0x0fff))
 
     @portable(flags=["fast-math"])
     def asf_to_amplitude(self, asf):

artiq/coredevice/spi.py

@@ -74,7 +74,7 @@ class SPIMaster:
     def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
         """Set the configuration register.
 
-        * If ``config.cs_polarity`` == 0 (```cs`` active low, the default),
+        * If ``config.cs_polarity`` == 0 (``cs`` active low, the default),
           "``cs_n`` all deasserted" means "all ``cs_n`` bits high".
         * ``cs_n`` is not mandatory in the pads supplied to the gateware core.
           Framing and chip selection can also be handled independently

artiq/dashboard/datasets.py

@@ -7,6 +7,7 @@ from PyQt5 import QtCore, QtWidgets
 from artiq.tools import short_format
 from artiq.gui.tools import LayoutWidget, QRecursiveFilterProxyModel
 from artiq.gui.models import DictSyncTreeSepModel
+from artiq.gui.scientific_spinbox import ScientificSpinBox
 
 
 logger = logging.getLogger(__name__)
@@ -50,10 +51,10 @@ class Editor(QtWidgets.QDialog):
 
 class NumberEditor(Editor):
     def get_edit_widget(self, initial_value):
-        self.edit_widget = QtWidgets.QDoubleSpinBox()
-        self.edit_widget.setMinimum(float("-inf"))
-        self.edit_widget.setMaximum(float("+inf"))
-        self.edit_widget.setDecimals(8)
+        self.edit_widget = ScientificSpinBox()
+        self.edit_widget.setDecimals(13)
+        self.edit_widget.setPrecision()
+        self.edit_widget.setRelativeStep()
         self.edit_widget.setValue(float(initial_value))
         return self.edit_widget
 

artiq/dashboard/experiments.py

@@ -8,7 +8,7 @@ from PyQt5 import QtCore, QtGui, QtWidgets
 import h5py
 
 from artiq.gui.tools import LayoutWidget, log_level_to_name, get_open_file_name
-from artiq.gui.entries import argty_to_entry, ScanEntry
+from artiq.gui.entries import procdesc_to_entry, ScanEntry
 from artiq.protocols import pyon
 
 
@@ -56,7 +56,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
         self.viewport().installEventFilter(_WheelFilter(self.viewport()))
 
         self._groups = dict()
-        self._arg_to_entry_widgetitem = dict()
+        self._arg_to_widgets = dict()
 
         arguments = self.manager.get_submission_arguments(self.expurl)
 
@@ -68,9 +68,13 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
         gradient.setColorAt(0, self.palette().base().color())
         gradient.setColorAt(1, self.palette().midlight().color())
         for name, argument in arguments.items():
-            entry = argty_to_entry[argument["desc"]["ty"]](argument)
+            widgets = dict()
+            self._arg_to_widgets[name] = widgets
+
+            entry = procdesc_to_entry(argument["desc"])(argument)
             widget_item = QtWidgets.QTreeWidgetItem([name])
-            self._arg_to_entry_widgetitem[name] = entry, widget_item
+            widgets["entry"] = entry
+            widgets["widget_item"] = widget_item
 
             for col in range(3):
                 widget_item.setBackground(col, gradient)
@@ -83,6 +87,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
             else:
                 self._get_group(argument["group"]).addChild(widget_item)
             fix_layout = LayoutWidget()
+            widgets["fix_layout"] = fix_layout
             fix_layout.addWidget(entry)
             self.setItemWidget(widget_item, 1, fix_layout)
             recompute_argument = QtWidgets.QToolButton()
@@ -97,8 +102,8 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
             tool_buttons = LayoutWidget()
             tool_buttons.addWidget(recompute_argument, 1)
 
-            if isinstance(entry, ScanEntry):
             disable_other_scans = QtWidgets.QToolButton()
+            widgets["disable_other_scans"] = disable_other_scans
             disable_other_scans.setIcon(
                 QtWidgets.QApplication.style().standardIcon(
                     QtWidgets.QStyle.SP_DialogResetButton))
@@ -109,6 +114,8 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
             tool_buttons.layout.setRowStretch(0, 1)
             tool_buttons.layout.setRowStretch(3, 1)
             tool_buttons.addWidget(disable_other_scans, 2)
+            if not isinstance(entry, ScanEntry):
+                disable_other_scans.setVisible(False)
 
             self.setItemWidget(widget_item, 2, tool_buttons)
 
@@ -161,28 +168,41 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
         argument = self.manager.get_submission_arguments(self.expurl)[name]
 
         procdesc = arginfo[name][0]
-        state = argty_to_entry[procdesc["ty"]].default_state(procdesc)
+        state = procdesc_to_entry(procdesc).default_state(procdesc)
         argument["desc"] = procdesc
         argument["state"] = state
 
-        old_entry, widget_item = self._arg_to_entry_widgetitem[name]
-        old_entry.deleteLater()
+        # Qt needs a setItemWidget() to handle layout correctly,
+        # simply replacing the entry inside the LayoutWidget
+        # results in a bug.
 
-        entry = argty_to_entry[procdesc["ty"]](argument)
-        self._arg_to_entry_widgetitem[name] = entry, widget_item
-        self.setItemWidget(widget_item, 1, entry)
+        widgets = self._arg_to_widgets[name]
+
+        widgets["entry"].deleteLater()
+        widgets["entry"] = procdesc_to_entry(procdesc)(argument)
+        widgets["disable_other_scans"].setVisible(
+            isinstance(widgets["entry"], ScanEntry))
+        widgets["fix_layout"].deleteLater()
+        widgets["fix_layout"] = LayoutWidget()
+        widgets["fix_layout"].addWidget(widgets["entry"])
+        self.setItemWidget(widgets["widget_item"], 1, widgets["fix_layout"])
+        self.updateGeometries()
 
     def _disable_other_scans(self, current_name):
-        for name, (entry, _) in self._arg_to_entry_widgetitem.items():
-            if name != current_name and isinstance(entry, ScanEntry):
-                entry.disable()
+        for name, widgets in self._arg_to_widgets.items():
+            if (name != current_name
+                    and isinstance(widgets["entry"], ScanEntry)):
+                widgets["entry"].disable()
 
     def save_state(self):
         expanded = []
         for k, v in self._groups.items():
             if v.isExpanded():
                 expanded.append(k)
-        return {"expanded": expanded}
+        return {
+            "expanded": expanded,
+            "scroll": self.verticalScrollBar().value()
+        }
 
     def restore_state(self, state):
         for e in state["expanded"]:
@@ -190,6 +210,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
                 self._groups[e].setExpanded(True)
             except KeyError:
                 pass
+        self.verticalScrollBar().setValue(state["scroll"])
 
 
 log_levels = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"]
@@ -445,6 +466,7 @@ class ExperimentManager:
         self.schedule_ctl = schedule_ctl
         self.experiment_db_ctl = experiment_db_ctl
 
+        self.dock_states = dict()
         self.submission_scheduling = dict()
         self.submission_options = dict()
         self.submission_arguments = dict()
@@ -502,7 +524,7 @@ class ExperimentManager:
     def initialize_submission_arguments(self, expurl, arginfo):
         arguments = OrderedDict()
         for name, (procdesc, group) in arginfo.items():
-            state = argty_to_entry[procdesc["ty"]].default_state(procdesc)
+            state = procdesc_to_entry(procdesc).default_state(procdesc)
             arguments[name] = {
                 "desc": procdesc,
                 "group": group,
@@ -536,12 +558,22 @@ class ExperimentManager:
             del self.submission_arguments[expurl]
             dock = _ExperimentDock(self, expurl)
         self.open_experiments[expurl] = dock
+        dock.setAttribute(QtCore.Qt.WA_DeleteOnClose)
         self.main_window.centralWidget().addSubWindow(dock)
         dock.show()
         dock.sigClosed.connect(partial(self.on_dock_closed, expurl))
+        if expurl in self.dock_states:
+            try:
+                dock.restore_state(self.dock_states[expurl])
+            except:
+                logger.warning("Failed to restore dock state when opening "
+                               "experiment %s", expurl,
+                               exc_info=True)
         return dock
 
     def on_dock_closed(self, expurl):
+        dock = self.open_experiments[expurl]
+        self.dock_states[expurl] = dock.save_state()
         del self.open_experiments[expurl]
 
     async def _submit_task(self, expurl, *args):
@@ -556,7 +588,7 @@ class ExperimentManager:
 
         argument_values = dict()
         for name, argument in arguments.items():
-            entry_cls = argty_to_entry[argument["desc"]["ty"]]
+            entry_cls = procdesc_to_entry(argument["desc"])
             argument_values[name] = entry_cls.state_to_value(argument["state"])
 
         expid = {
@@ -606,6 +638,8 @@ class ExperimentManager:
         file, class_name, use_repository = self.resolve_expurl(expurl)
         if use_repository:
             revision = self.get_submission_options(expurl)["repo_rev"]
+        else:
+            revision = None
         description = await self.experiment_db_ctl.examine(
             file, use_repository, revision)
         return description[class_name]["arginfo"]
@@ -620,21 +654,22 @@ class ExperimentManager:
             self.open_experiment(expurl)
 
     def save_state(self):
-        docks = {expurl: dock.save_state()
-                 for expurl, dock in self.open_experiments.items()}
+        for expurl, dock in self.open_experiments.items():
+            self.dock_states[expurl] = dock.save_state()
         return {
             "scheduling": self.submission_scheduling,
             "options": self.submission_options,
             "arguments": self.submission_arguments,
-            "docks": docks
+            "docks": self.dock_states,
+            "open_docks": set(self.open_experiments.keys())
         }
 
     def restore_state(self, state):
         if self.open_experiments:
             raise NotImplementedError
+        self.dock_states = state["docks"]
         self.submission_scheduling = state["scheduling"]
         self.submission_options = state["options"]
         self.submission_arguments = state["arguments"]
-        for expurl, dock_state in state["docks"].items():
-            dock = self.open_experiment(expurl)
-            dock.restore_state(dock_state)
+        for expurl in state["open_docks"]:
+            self.open_experiment(expurl)

artiq/dashboard/moninj.py

@@ -207,6 +207,10 @@ class _DeviceManager:
                 widget = None
                 if v["module"] == "artiq.coredevice.ttl":
                     channel = v["arguments"]["channel"]
+                    if channel > 63:
+                        # The moninj protocol is limited to 64 channels; ignore
+                        # any beyond that for now to avoid confusion.
+                        return
                     force_out = v["class"] == "TTLOut"
                     widget = _TTLWidget(
                         channel, self.send_to_device, force_out, k)

artiq/devices/novatech409b/driver.py

@@ -177,7 +177,8 @@ class Novatech409B:
                     "00989680 2000 01F5 0000 00000000 00000000 000301",
                     "80 BC0000 0000 0102 21"]
         else:
-            self.port.reset_input_buffer()
+            self.port.ser.reset_input_buffer()
+            result = []
             await self.port.write(("QUE" + "\r\n").encode())
             for i in range(5):
                 m = (await self._ser_readline()).rstrip().decode()

artiq/frontend/artiq_client.py

@@ -13,6 +13,7 @@ from prettytable import PrettyTable
 
 from artiq.protocols.pc_rpc import Client
 from artiq.protocols.sync_struct import Subscriber
+from artiq.protocols.broadcast import Receiver
 from artiq.protocols import pyon
 from artiq.tools import short_format
 
@@ -236,8 +237,6 @@ def _show_datasets(datasets):
 
 
 def _run_subscriber(host, port, subscriber):
-    if port is None:
-        port = 3250
     loop = asyncio.get_event_loop()
     try:
         loop.run_until_complete(subscriber.connect(host, port))
@@ -259,7 +258,8 @@ def _show_dict(args, notifier_name, display_fun):
         return d
     subscriber = Subscriber(notifier_name, init_d,
                             lambda mod: display_fun(d))
-    _run_subscriber(args.server, args.port, subscriber)
+    port = 3250 if args.port is None else args.port
+    _run_subscriber(args.server, port, subscriber)
 
 
 def _print_log_record(record):
@@ -268,30 +268,10 @@ def _print_log_record(record):
     print(level, source, t, message)
 
 
-class _LogPrinter:
-    def __init__(self, init):
-        for record in init:
-            _print_log_record(record)
-
-    def append(self, record):
-        _print_log_record(record)
-
-    def insert(self, i, record):
-        _print_log_record(record)
-
-    def pop(self, i=-1):
-        pass
-
-    def __delitem__(self, x):
-        pass
-
-    def __setitem__(self, k, v):
-        pass
-
-
 def _show_log(args):
-    subscriber = Subscriber("log", _LogPrinter)
-    _run_subscriber(args.server, args.port, subscriber)
+    subscriber = Receiver("log", [_print_log_record])
+    port = 1067 if args.port is None else args.port
+    _run_subscriber(args.server, port, subscriber)
 
 
 def main():

artiq/frontend/artiq_compile.py

@@ -55,7 +55,7 @@ def main():
 
         object_map, kernel_library, _, _ = \
             core.compile(exp.run, [exp_inst], {},
-                         with_attr_writeback=False)
+                         attribute_writeback=False, print_as_rpc=False)
     except CompileError as error:
         return
     finally:

artiq/frontend/artiq_flash.py

@@ -11,12 +11,14 @@ from artiq import __artiq_dir__ as artiq_dir
 from artiq.frontend.bit2bin import bit2bin
 
 
-scripts_path = ["share", "openocd", "scripts"]
-if os.name == "nt":
-    scripts_path.insert(0, "Library")
-scripts_path = os.path.abspath(os.path.join(
+def scripts_path():
+    p = ["share", "openocd", "scripts"]
+    if os.name == "nt":
+        p.insert(0, "Library")
+    p = os.path.abspath(os.path.join(
         os.path.dirname(shutil.which("openocd")),
-    "..", *scripts_path))
+        "..", *p))
+    return p
 
 
 def get_argparser():
@@ -139,7 +141,7 @@ def main():
             target_file = opts.target_file
         subprocess.check_call([
             "openocd",
-            "-s", scripts_path,
+            "-s", scripts_path(),
             "-f", target_file,
             "-c", "; ".join(prog),
         ])

artiq/frontend/bit2bin.py

@@ -1,22 +1,7 @@
 #!/usr/bin/env python3.5
-# Copyright 2014-2015 Robert Jordens <jordens@gmail.com>
+# Copyright 2014-2017 Robert Jordens <jordens@gmail.com>
 # after
 # https://github.com/mfischer/fpgadev-zynq/blob/master/top/python/bit_to_zynq_bin.py
-#
-# This file is part of redpid.
-#
-# redpid is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# redpid is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with redpid.  If not, see <http://www.gnu.org/licenses/>.
 
 import struct
 

artiq/frontend/novatech409b_controller.py

@@ -5,6 +5,7 @@
 import argparse
 import logging
 import sys
+import os
 import asyncio
 
 from artiq.devices.novatech409b.driver import Novatech409B
@@ -33,6 +34,9 @@ def main():
     args = get_argparser().parse_args()
     init_logger(args)
 
+    if os.name == "nt":
+        asyncio.set_event_loop(asyncio.ProactorEventLoop())
+
     if not args.simulation and args.device is None:
         print("You need to specify either --simulation or -d/--device "
               "argument. Use --help for more information.")

artiq/frontend/pdq2_client.py

@@ -1,73 +0,0 @@
-#!/usr/bin/python
-# Copyright (C) 2012-2015 Robert Jordens <jordens@gmail.com>
-
-import argparse
-
-from scipy import interpolate
-import numpy as np
-
-from artiq.protocols.pc_rpc import Client
-from artiq.tools import verbosity_args, init_logger
-
-
-def get_argparser():
-    parser = argparse.ArgumentParser(description="""PDQ2 client.
-        Evaluates times and voltages, interpolates and uploads
-        them to the controller.""")
-    parser.add_argument("-s", "--server", default="::1",
-                        help="hostname or IP of the controller to connect to")
-    parser.add_argument("--port", default=3252, type=int,
-                        help="TCP port to use to connect to the controller")
-    parser.add_argument("-c", "--channel", default=0, type=int,
-                        help="channel: 3*board_num+dac_num [%(default)s]")
-    parser.add_argument("-f", "--frame", default=0, type=int,
-                        help="frame [%(default)s]")
-    parser.add_argument("-t", "--times", default="np.arange(5)*1e-6",
-                        help="sample times (s) [%(default)s]")
-    parser.add_argument("-u", "--voltages",
-                        default="(1-np.cos(t/t[-1]*2*np.pi))/2",
-                        help="sample voltages (V) [%(default)s]")
-    parser.add_argument("-o", "--order", default=3, type=int,
-                        help="interpolation (0: const, 1: lin, 2: quad,"
-                        " 3: cubic) [%(default)s]")
-    parser.add_argument("-e", "--free", default=False, action="store_true",
-                        help="software trigger [%(default)s]")
-    verbosity_args(parser)
-    return parser
-
-
-def main():
-    args = get_argparser().parse_args()
-    init_logger(args)
-    dev = Client(args.server, args.port, "pdq2")
-
-    freq = dev.get_freq()
-    times = np.around(eval(args.times, globals(), {})*freq)
-    voltages = eval(args.voltages, globals(), dict(t=times/freq))
-
-    dt = np.diff(times.astype(np.int))
-    if args.order:
-        tck = interpolate.splrep(times, voltages, k=args.order, s=0)
-        u = interpolate.spalde(times, tck)
-    else:
-        u = voltages[:, None]
-    segment = []
-    for dti, ui in zip(dt, u):
-        segment.append({
-            "duration": int(dti),
-            "channel_data": [{
-                "bias": {
-                    "amplitude": [float(uij) for uij in ui]
-                }
-            }]
-        })
-    program = [[] for i in range(args.frame)]
-    program.append(segment)
-    dev.park()
-    dev.program(program, [args.channel])
-    dev.unpark()
-    dev.cmd("TRIGGER", args.free)
-
-
-if __name__ == "__main__":
-    main()

artiq/frontend/thorlabs_tcube_controller.py

@@ -2,6 +2,8 @@
 
 import argparse
 import sys
+import os
+import asyncio
 
 from artiq.devices.thorlabs_tcube.driver import Tdc, Tpz, TdcSim, TpzSim
 from artiq.protocols.pc_rpc import simple_server_loop
@@ -28,6 +30,9 @@ def main():
     args = get_argparser().parse_args()
     init_logger(args)
 
+    if os.name == "nt":
+        asyncio.set_event_loop(asyncio.ProactorEventLoop())
+
     if not args.simulation and args.device is None:
         print("You need to specify either --simulation or -d/--device "
               "argument. Use --help for more information.")

artiq/gateware/rtio/core.py

@@ -167,6 +167,9 @@ class _OutputManager(Module):
                     (self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
                     & ((self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
                        |different_addresses))
+            else:
+                self.sync.rsys += collision.eq(
+                    (self.ev.timestamp == buf.timestamp) & different_addresses)
         else:
             self.sync.rsys += collision.eq(
                 self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])

artiq/gateware/spi.py

@@ -1,163 +1,8 @@
 from itertools import product
 
 from migen import *
-from migen.genlib.fsm import FSM, NextState
 from misoc.interconnect import wishbone
-
-
-class SPIClockGen(Module):
-    def __init__(self, width):
-        self.load = Signal(width)
-        self.bias = Signal()  # bias this clock phase to longer times
-        self.edge = Signal()
-        self.clk = Signal(reset=1)
-
-        cnt = Signal.like(self.load)
-        bias = Signal()
-        zero = Signal()
-        self.comb += [
-            zero.eq(cnt == 0),
-            self.edge.eq(zero & ~bias),
-        ]
-        self.sync += [
-            If(zero,
-                bias.eq(0),
-            ).Else(
-                cnt.eq(cnt - 1),
-            ),
-            If(self.edge,
-                cnt.eq(self.load[1:]),
-                bias.eq(self.load[0] & (self.clk ^ self.bias)),
-                self.clk.eq(~self.clk),
-            )
-        ]
-
-
-class SPIRegister(Module):
-    def __init__(self, width):
-        self.data = Signal(width)
-        self.o = Signal()
-        self.i = Signal()
-        self.lsb = Signal()
-        self.shift = Signal()
-        self.sample = Signal()
-
-        self.comb += [
-            self.o.eq(Mux(self.lsb, self.data[0], self.data[-1])),
-        ]
-        self.sync += [
-            If(self.shift,
-                If(self.lsb,
-                    self.data[:-1].eq(self.data[1:]),
-                ).Else(
-                    self.data[1:].eq(self.data[:-1]),
-                )
-            ),
-            If(self.sample,
-                If(self.lsb,
-                    self.data[-1].eq(self.i),
-                ).Else(
-                    self.data[0].eq(self.i),
-                )
-            )
-        ]
-
-
-class SPIBitCounter(Module):
-    def __init__(self, width):
-        self.n_read = Signal(width)
-        self.n_write = Signal(width)
-        self.read = Signal()
-        self.write = Signal()
-        self.done = Signal()
-
-        self.comb += [
-            self.write.eq(self.n_write != 0),
-            self.read.eq(self.n_read != 0),
-            self.done.eq(~(self.write | self.read)),
-        ]
-        self.sync += [
-            If(self.write,
-                self.n_write.eq(self.n_write - 1),
-            ).Elif(self.read,
-                self.n_read.eq(self.n_read - 1),
-            )
-        ]
-
-
-class SPIMachine(Module):
-    def __init__(self, data_width, clock_width, bits_width):
-        ce = CEInserter()
-        self.submodules.cg = ce(SPIClockGen(clock_width))
-        self.submodules.reg = ce(SPIRegister(data_width))
-        self.submodules.bits = ce(SPIBitCounter(bits_width))
-        self.div_write = Signal.like(self.cg.load)
-        self.div_read = Signal.like(self.cg.load)
-        self.clk_phase = Signal()
-        self.start = Signal()
-        self.cs = Signal()
-        self.oe = Signal()
-        self.done = Signal()
-
-        # # #
-
-        fsm = CEInserter()(FSM("IDLE"))
-        self.submodules += fsm
-
-        fsm.act("IDLE",
-            If(self.start,
-                If(self.clk_phase,
-                    NextState("WAIT"),
-                ).Else(
-                    NextState("SETUP"),
-                )
-            )
-        )
-        fsm.act("SETUP",
-            self.reg.sample.eq(1),
-            NextState("HOLD"),
-        )
-        fsm.act("HOLD",
-            If(self.bits.done & ~self.start,
-                If(self.clk_phase,
-                    NextState("IDLE"),
-                ).Else(
-                    NextState("WAIT"),
-                )
-            ).Else(
-                self.reg.shift.eq(~self.start),
-                NextState("SETUP"),
-            )
-        )
-        fsm.act("WAIT",
-            If(self.bits.done,
-                NextState("IDLE"),
-            ).Else(
-                NextState("SETUP"),
-            )
-        )
-
-        write0 = Signal()
-        self.sync += [
-            If(self.cg.edge & self.reg.shift,
-                write0.eq(self.bits.write),
-            )
-        ]
-        self.comb += [
-            self.cg.ce.eq(self.start | self.cs | ~self.cg.edge),
-            If(self.bits.write | ~self.bits.read,
-                self.cg.load.eq(self.div_write),
-            ).Else(
-                self.cg.load.eq(self.div_read),
-            ),
-            self.cg.bias.eq(self.clk_phase),
-            fsm.ce.eq(self.cg.edge),
-            self.cs.eq(~fsm.ongoing("IDLE")),
-            self.reg.ce.eq(self.cg.edge),
-            self.bits.ce.eq(self.cg.edge & self.reg.sample),
-            self.done.eq(self.cg.edge & self.bits.done & fsm.ongoing("HOLD")),
-            self.oe.eq(write0 | self.bits.write),
-        ]
+from misoc.cores.spi.core import SPIMachine
 
 
 class SPIMaster(Module):
@@ -293,7 +138,7 @@ class SPIMaster(Module):
         assert len(xfer) <= len(bus.dat_w)
 
         self.submodules.spi = spi = SPIMachine(
-            data_width=len(bus.dat_w),
+            data_width=len(bus.dat_w) + 1,
             clock_width=len(config.div_read),
             bits_width=len(xfer.read_length))
 
@@ -311,13 +156,18 @@ class SPIMaster(Module):
         ]
         self.sync += [
             If(spi.done,
-                data_read.eq(spi.reg.data),
+                data_read.eq(
+                    Mux(spi.reg.lsb, spi.reg.data[1:], spi.reg.data[:-1])),
             ),
             If(spi.start,
                 cs.eq(xfer.cs),
                 spi.bits.n_write.eq(xfer.write_length),
                 spi.bits.n_read.eq(xfer.read_length),
-                spi.reg.data.eq(data_write),
+                If(spi.reg.lsb,
+                    spi.reg.data[:-1].eq(data_write),
+                ).Else(
+                    spi.reg.data[1:].eq(data_write),
+                ),
                 pending.eq(0),
             ),
             # wb.ack a transaction if any of the following:

artiq/gateware/targets/kc705.py

@@ -248,16 +248,16 @@ class NIST_CLOCK(_NIST_Ions):
             if i % 4 == 3:
                 phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
                 self.submodules += phy
-                rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
+                rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=1024))
             else:
                 phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
                 self.submodules += phy
-                rtio_channels.append(rtio.Channel.from_phy(phy))
+                rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=1024))
 
         for i in range(2):
             phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i))
             self.submodules += phy
-            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
+            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16384))
 
         phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
         self.submodules += phy
@@ -297,7 +297,7 @@ class NIST_CLOCK(_NIST_Ions):
         phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy,
-                                                   ofifo_depth=512,
+                                                   ofifo_depth=16384,
                                                    ififo_depth=4))
 
         self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)

artiq/gateware/targets/pipistrello.py

@@ -176,7 +176,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
             phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
                                                self.rtio_crg.rtiox4_stb)
             self.submodules += phy
-            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256,
+            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128,
                                                        ofifo_depth=4))
 
         # the last TTL is used for ClockGen
@@ -223,7 +223,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         phy = dds.AD9858(dds_pins, 8)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy,
-                                                   ofifo_depth=256,
+                                                   ofifo_depth=128,
                                                    ififo_depth=4))
 
         self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)

artiq/gui/applets.py

@@ -81,11 +81,12 @@ class AppletIPCServer(AsyncioParentComm):
         finally:
             self.datasets_sub.notify_cbs.remove(self._on_mod)
 
-    def start(self, embed_cb, fix_initial_size_cb):
+    def start_server(self, embed_cb, fix_initial_size_cb):
         self.server_task = asyncio.ensure_future(
             self.serve(embed_cb, fix_initial_size_cb))
 
-    async def stop(self):
+    async def stop_server(self):
+        if hasattr(self, "server_task"):
             self.server_task.cancel()
             await asyncio.wait([self.server_task])
 
@@ -137,13 +138,14 @@ class _AppletDock(QDockWidgetCloseDetect):
             except:
                 logger.warning("Applet %s failed to start", self.applet_name,
                                exc_info=True)
+                return
             asyncio.ensure_future(
                 LogParser(self._get_log_source).stream_task(
                     self.ipc.process.stdout))
             asyncio.ensure_future(
                 LogParser(self._get_log_source).stream_task(
                     self.ipc.process.stderr))
-            self.ipc.start(self.embed, self.fix_initial_size)
+            self.ipc.start_server(self.embed, self.fix_initial_size)
         finally:
             self.starting_stopping = False
 
@@ -165,7 +167,8 @@ class _AppletDock(QDockWidgetCloseDetect):
         self.starting_stopping = True
 
         if hasattr(self, "ipc"):
-            await self.ipc.stop()
+            await self.ipc.stop_server()
+            if hasattr(self.ipc, "process"):
                 self.ipc.write_pyon({"action": "terminate"})
                 try:
                     await asyncio.wait_for(self.ipc.process.wait(), 2.0)

artiq/gui/entries.py

@@ -69,7 +69,41 @@ class EnumerationEntry(QtWidgets.QComboBox):
             return procdesc["choices"][0]
 
 
-class NumberEntry(ScientificSpinBox):
+class NumberEntryInt(QtWidgets.QSpinBox):
+    def __init__(self, argument):
+        QtWidgets.QSpinBox.__init__(self)
+        disable_scroll_wheel(self)
+        procdesc = argument["desc"]
+        self.setSingleStep(procdesc["step"])
+        if procdesc["min"] is not None:
+            self.setMinimum(procdesc["min"])
+        else:
+            self.setMinimum(-((1 << 31) - 1))
+        if procdesc["max"] is not None:
+            self.setMaximum(procdesc["max"])
+        else:
+            self.setMaximum((1 << 31) - 1)
+        if procdesc["unit"]:
+            self.setSuffix(" " + procdesc["unit"])
+
+        self.setValue(argument["state"])
+        def update(value):
+            argument["state"] = value
+        self.valueChanged.connect(update)
+
+    @staticmethod
+    def state_to_value(state):
+        return state
+
+    @staticmethod
+    def default_state(procdesc):
+        if "default" in procdesc:
+            return procdesc["default"]
+        else:
+            return 0
+
+
+class NumberEntryFloat(ScientificSpinBox):
     def __init__(self, argument):
         ScientificSpinBox.__init__(self)
         disable_scroll_wheel(self)
@@ -136,6 +170,19 @@ class _NoScan(LayoutWidget):
             state["value"] = value*scale
         self.value.valueChanged.connect(update)
 
+        self.repetitions = QtWidgets.QSpinBox()
+        self.repetitions.setMinimum(1)
+        self.repetitions.setMaximum((1 << 31) - 1)
+        disable_scroll_wheel(self.repetitions)
+        self.addWidget(QtWidgets.QLabel("Repetitions:"), 1, 0)
+        self.addWidget(self.repetitions, 1, 1)
+
+        self.repetitions.setValue(state["repetitions"])
+
+        def update_repetitions(value):
+            state["repetitions"] = value
+        self.repetitions.valueChanged.connect(update_repetitions)
+
 
 class _RangeScan(LayoutWidget):
     def __init__(self, procdesc, state):
@@ -272,6 +319,7 @@ class ScanEntry(LayoutWidget):
 
     def disable(self):
         self.radiobuttons["NoScan"].setChecked(True)
+        self.widgets["NoScan"].repetitions.setValue(1)
 
     @staticmethod
     def state_to_value(state):
@@ -285,7 +333,7 @@ class ScanEntry(LayoutWidget):
         scale = procdesc["scale"]
         state = {
             "selected": "NoScan",
-            "NoScan": {"value": 0.0},
+            "NoScan": {"value": 0.0, "repetitions": 1},
             "LinearScan": {"start": 0.0, "stop": 100.0*scale, "npoints": 10},
             "RandomScan": {"start": 0.0, "stop": 100.0*scale, "npoints": 10},
             "ExplicitScan": {"sequence": []}
@@ -299,6 +347,7 @@ class ScanEntry(LayoutWidget):
                 ty = default["ty"]
                 if ty == "NoScan":
                     state[ty]["value"] = default["value"]
+                    state[ty]["repetitions"] = default["repetitions"]
                 elif ty == "LinearScan" or ty == "RandomScan":
                     state[ty]["start"] = default["start"]
                     state[ty]["stop"] = default["stop"]
@@ -317,11 +366,21 @@ class ScanEntry(LayoutWidget):
                 break
 
 
-argty_to_entry = {
+def procdesc_to_entry(procdesc):
+    ty = procdesc["ty"]
+    if ty == "NumberValue":
+        is_int = (procdesc["ndecimals"] == 0
+                  and int(procdesc["step"]) == procdesc["step"]
+                  and procdesc["scale"] == 1)
+        if is_int:
+            return NumberEntryInt
+        else:
+            return NumberEntryFloat
+    else:
+        return {
             "PYONValue": StringEntry,
             "BooleanValue": BooleanEntry,
             "EnumerationValue": EnumerationEntry,
-    "NumberValue": NumberEntry,
             "StringValue": StringEntry,
             "Scannable": ScanEntry
-}
+        }[ty]

artiq/gui/logo20.svg

@@ -2,7 +2,6 @@
 <!-- Generator: Adobe Illustrator 16.0.3, SVG Export Plug-In . SVG Version: 6.00 Build 0)  -->
 
 <svg
-   xmlns:i="&amp;ns_ai;"
    xmlns:dc="http://purl.org/dc/elements/1.1/"
    xmlns:cc="http://creativecommons.org/ns#"
    xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
@@ -13,14 +12,14 @@
    version="1.1"
    x="0px"
    y="0px"
-   width="360.147"
+   width="324.483"
    height="432.04401"
-   viewBox="0 0 360.147 432.04401"
+   viewBox="0 0 324.483 432.04401"
    enable-background="new 0 0 800 800"
    xml:space="preserve"
    id="svg2"
    inkscape:version="0.91 r13725"
-   sodipodi:docname="Artiq_logo_final_cleaned.svg"><metadata
+   sodipodi:docname="logo20.svg"><metadata
      id="metadata548"><rdf:RDF><cc:Work
          rdf:about=""><dc:format>image/svg+xml</dc:format><dc:type
            rdf:resource="http://purl.org/dc/dcmitype/StillImage" /><dc:title></dc:title></cc:Work></rdf:RDF></metadata><defs
@@ -34,20 +33,20 @@
      inkscape:pageopacity="0"
      inkscape:pageshadow="2"
      inkscape:window-width="1920"
-     inkscape:window-height="1156"
+     inkscape:window-height="1162"
      id="namedview544"
      showgrid="false"
      fit-margin-top="0"
      fit-margin-left="0"
      fit-margin-right="0"
      fit-margin-bottom="0"
-     inkscape:zoom="0.417193"
-     inkscape:cx="-963.25369"
-     inkscape:cy="-371.05578"
+     inkscape:zoom="0.834386"
+     inkscape:cx="43.474611"
+     inkscape:cy="345.52987"
      inkscape:window-x="0"
-     inkscape:window-y="44"
+     inkscape:window-y="38"
      inkscape:window-maximized="1"
-     inkscape:current-layer="svg2" /><path
+     inkscape:current-layer="g423" /><path
      inkscape:connector-curvature="0"
      style="fill:#ffffff"
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@@ -121,29 +120,21 @@
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        style="fill:#ffffff"
        id="polygon417"
-       points="432.151,554.577 387.202,554.577 387.202,567.019 402.733,567.019 402.733,615.779 416.71,615.779 416.71,567.019 432.151,567.019 " /><polygon
+       points="402.733,567.019 402.733,615.779 416.71,615.779 416.71,567.019 432.151,567.019 432.151,554.577 387.202,554.577 387.202,567.019 " /><polygon
        style="fill:#ffffff"
        id="polygon419"
-       points="464.571,566.657 471.976,566.657 471.976,554.577 443.19,554.577 443.19,566.657 450.595,566.657 450.595,603.608 442.558,603.608 442.558,615.779 472.606,615.779 472.606,603.608 464.571,603.608 " /><path
+       points="443.19,554.577 443.19,566.657 450.595,566.657 450.595,603.608 442.558,603.608 442.558,615.779 472.606,615.779 472.606,603.608 464.571,603.608 464.571,566.657 471.976,566.657 471.976,554.577 " /><path
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-     style="fill:#ffffff"
+     style="fill:#000000"
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      transform="translate(-250.847,-184.784)"><path
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        style="fill:#ffffff"
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artiq/language/environment.py

@@ -48,6 +48,12 @@ class _SimpleArgProcessor:
 
 class PYONValue(_SimpleArgProcessor):
     """An argument that can be any PYON-serializable value."""
+    def __init__(self, default=NoDefault):
+        # Override the _SimpleArgProcessor init, as list defaults are valid
+        # PYON values
+        if default is not NoDefault:
+            self.default_value = default
+
     def process(self, x):
         return pyon.decode(x)
 

artiq/language/scan.py

@@ -36,12 +36,15 @@ class ScanObject:
 
 
 class NoScan(ScanObject):
-    """A scan object that yields a single value."""
-    def __init__(self, value):
+    """A scan object that yields a single value for a specified number
+    of repetitions."""
+    def __init__(self, value, repetitions=1):
         self.value = value
+        self.repetitions = repetitions
 
     @portable
     def _gen(self):
+        for i in range(self.repetitions):
             yield self.value
 
     @portable
@@ -49,10 +52,11 @@ class NoScan(ScanObject):
         return self._gen()
 
     def __len__(self):
-        return 1
+        return self.repetitions
 
     def describe(self):
-        return {"ty": "NoScan", "value": self.value}
+        return {"ty": "NoScan", "value": self.value,
+                "repetitions": self.repetitions}
 
 
 class LinearScan(ScanObject):
@@ -99,7 +103,7 @@ class RandomScan(ScanObject):
         if seed is None:
             rf = random.random
         else:
-            rf = Random(seed).random
+            rf = random.Random(seed).random
         random.shuffle(self.sequence, rf)
 
     @portable

artiq/master/experiments.py

@@ -2,6 +2,7 @@ import asyncio
 import os
 import tempfile
 import shutil
+import time
 import logging
 
 from artiq.protocols.sync_struct import Notifier
@@ -13,16 +14,19 @@ from artiq.tools import get_windows_drives, exc_to_warning
 logger = logging.getLogger(__name__)
 
 
-async def _get_repository_entries(entry_dict,
-                                  root, filename, worker_handlers):
-    worker = Worker(worker_handlers)
+class _RepoScanner:
+    def __init__(self, worker_handlers):
+        self.worker_handlers = worker_handlers
+        self.worker = None
+
+    async def process_file(self, entry_dict, root, filename):
+        logger.debug("processing file %s %s", root, filename)
         try:
-        description = await worker.examine("scan", os.path.join(root, filename))
+            description = await self.worker.examine(
+                "scan", os.path.join(root, filename))
         except:
             log_worker_exception()
             raise
-    finally:
-        await worker.close()
         for class_name, class_desc in description.items():
             name = class_desc["name"]
             arginfo = class_desc["arginfo"]
@@ -46,8 +50,7 @@ async def _get_repository_entries(entry_dict,
             }
             entry_dict[name] = entry
 
-
-async def _scan_experiments(root, worker_handlers, subdir=""):
+    async def _scan(self, root, subdir=""):
         entry_dict = dict()
         for de in os.scandir(os.path.join(root, subdir)):
             if de.name.startswith("."):
@@ -55,19 +58,28 @@ async def _scan_experiments(root, worker_handlers, subdir=""):
             if de.is_file() and de.name.endswith(".py"):
                 filename = os.path.join(subdir, de.name)
                 try:
-                await _get_repository_entries(
-                    entry_dict, root, filename, worker_handlers)
+                    await self.process_file(entry_dict, root, filename)
                 except Exception as exc:
                     logger.warning("Skipping file '%s'", filename,
                         exc_info=not isinstance(exc, WorkerInternalException))
+                    # restart worker
+                    await self.worker.close()
+                    self.worker = Worker(self.worker_handlers)
             if de.is_dir():
-            subentries = await _scan_experiments(
-                root, worker_handlers,
-                os.path.join(subdir, de.name))
+                subentries = await self._scan(
+                    root, os.path.join(subdir, de.name))
                 entries = {de.name + "/" + k: v for k, v in subentries.items()}
                 entry_dict.update(entries)
         return entry_dict
 
+    async def scan(self, root):
+        self.worker = Worker(self.worker_handlers)
+        try:
+            r = await self._scan(root)
+        finally:
+            await self.worker.close()
+        return r
+
 
 def _sync_explist(target, source):
     for k in list(target.read.keys()):
@@ -109,7 +121,9 @@ class ExperimentDB:
             self.repo_backend.release_rev(self.cur_rev)
             self.cur_rev = new_cur_rev
             self.status["cur_rev"] = new_cur_rev
-            new_explist = await _scan_experiments(wd, self.worker_handlers)
+            t1 = time.monotonic()
+            new_explist = await _RepoScanner(self.worker_handlers).scan(wd)
+            logger.info("repository scan took %d seconds", time.monotonic()-t1)
 
             _sync_explist(self.explist, new_explist)
         finally:

artiq/master/scheduler.py

@@ -446,6 +446,9 @@ class Scheduler:
         whether returning control to the host and pausing would have an effect,
         in order to avoid the cost of switching kernels in the common case
         where ``pause`` does nothing.
+
+        This function does not have side effects, and does not have to be
+        followed by a call to ``pause``.
         """
         for pipeline in self._pipelines.values():
             if rid in pipeline.pool.runs:

artiq/master/worker.py

@@ -76,6 +76,8 @@ class Worker:
         return "worker({},{})".format(self.rid, self.filename)
 
     async def _create_process(self, log_level):
+        if self.ipc is not None:
+            return  # process already exists, recycle
         await self.io_lock.acquire()
         try:
             if self.closed.is_set():

artiq/master/worker_db.py

@@ -190,14 +190,20 @@ class DatasetManager:
             broadcast = True
         if broadcast:
             self.broadcast[key] = persist, value
+        elif key in self.broadcast.read:
+            del self.broadcast[key]
         if save:
             self.local[key] = value
+        elif key in self.local:
+            del self.local[key]
 
     def mutate(self, key, index, value):
         target = None
         if key in self.local:
             target = self.local[key]
         if key in self.broadcast.read:
+            if target is not None:
+                assert target is self.broadcast.read[key][1]
             target = self.broadcast[key][1]
         if target is None:
             raise KeyError("Cannot mutate non-existing dataset")

artiq/monkey_patches.py

@@ -4,7 +4,7 @@ import sys
 __all__ = []
 
 
-if sys.version_info[:3] == (3, 5, 2):
+if sys.version_info[:3] >= (3, 5, 2):
     import asyncio
 
     # See https://github.com/m-labs/artiq/issues/506

artiq/protocols/broadcast.py

@@ -17,7 +17,7 @@ class Receiver:
 
     async def connect(self, host, port):
         self.reader, self.writer = \
-            await asyncio.open_connection(host, port, limit=4*1024*1024)
+            await asyncio.open_connection(host, port, limit=100*1024*1024)
         try:
             self.writer.write(_init_string)
             self.writer.write((self.name + "\n").encode())

artiq/protocols/pc_rpc.py

@@ -201,7 +201,7 @@ class AsyncioClient:
         this method is a coroutine. See ``Client`` for a description of the
         parameters."""
         self.__reader, self.__writer = \
-            await asyncio.open_connection(host, port, limit=4*1024*1024)
+            await asyncio.open_connection(host, port, limit=100*1024*1024)
         try:
             self.__writer.write(_init_string)
             server_identification = await self.__recv()

artiq/protocols/pipe_ipc.py

@@ -22,7 +22,7 @@ class _BaseIO:
 
 if os.name != "nt":
     async def _fds_to_asyncio(rfd, wfd, loop):
-        reader = asyncio.StreamReader(loop=loop, limit=4*1024*1024)
+        reader = asyncio.StreamReader(loop=loop, limit=100*1024*1024)
         reader_protocol = asyncio.StreamReaderProtocol(reader, loop=loop)
         rf = open(rfd, "rb", 0)
         rt, _ = await loop.connect_read_pipe(lambda: reader_protocol, rf)
@@ -128,7 +128,7 @@ else:  # windows
             loop = asyncio.get_event_loop()
 
             def factory():
-                reader = asyncio.StreamReader(loop=loop, limit=4*1024*1024)
+                reader = asyncio.StreamReader(loop=loop, limit=100*1024*1024)
                 protocol = asyncio.StreamReaderProtocol(reader,
                                                 self._child_connected,
                                                 loop=loop)
@@ -189,7 +189,7 @@ else:  # windows
 
         async def connect(self):
             loop = asyncio.get_event_loop()
-            self.reader = asyncio.StreamReader(loop=loop, limit=4*1024*1024)
+            self.reader = asyncio.StreamReader(loop=loop, limit=100*1024*1024)
             reader_protocol = asyncio.StreamReaderProtocol(
                 self.reader, loop=loop)
             transport, _ = await loop.create_pipe_connection(

artiq/protocols/sync_struct.py

@@ -64,7 +64,7 @@ class Subscriber:
 
     async def connect(self, host, port, before_receive_cb=None):
         self.reader, self.writer = \
-            await asyncio.open_connection(host, port, limit=4*1024*1024)
+            await asyncio.open_connection(host, port, limit=100*1024*1024)
         try:
             if before_receive_cb is not None:
                 before_receive_cb()

artiq/runtime/Makefile

@@ -49,10 +49,11 @@ ksupport.elf: $(OBJECTS_KSUPPORT)
 		../libbase/crt0-$(CPU).o \
 		$^ \
 		-L../libbase \
+		-L../libm \
 		-L../libcompiler-rt \
 		-L../libunwind \
 		-L../libdyld \
-		-lbase-nofloat -lcompiler-rt -ldyld -lunwind
+		-lbase-nofloat -lm -lcompiler-rt -ldyld -lunwind
 	@chmod -x $@
 
 ksupport_data.o: ksupport.elf

artiq/runtime/ksupport.c

@@ -18,8 +18,9 @@
 #include "dds.h"
 #include "i2c.h"
 
-double round(double x);
 double sqrt(double x);
+double round(double x);
+double floor(double x);
 
 void ksupport_abort(void);
 static void attribute_writeback(void *);
@@ -88,8 +89,9 @@ static const struct symbol runtime_exports[] = {
     {"__powidf2", &__powidf2},
 
     /* libm */
-    {"round", &round},
     {"sqrt", &sqrt},
+    {"round", &round},
+    {"floor", &floor},
 
     /* exceptions */
     {"_Unwind_Resume", &_Unwind_Resume},
@@ -97,6 +99,7 @@ static const struct symbol runtime_exports[] = {
     {"__artiq_raise", &__artiq_raise},
     {"__artiq_reraise", &__artiq_reraise},
     {"strcmp", &strcmp},
+    {"strlen", &strlen},
     {"abort", &ksupport_abort},
 
     /* proxified syscalls */

artiq/runtime/moninj.c

@@ -12,6 +12,8 @@
 #include "log.h"
 #include "moninj.h"
 
+#define min(a, b) (a>b?b:a)
+
 enum {
     MONINJ_REQ_MONITOR = 1,
     MONINJ_REQ_TTLSET = 2
@@ -52,7 +54,8 @@ static void moninj_monitor(const ip_addr_t *addr, u16_t port)
     reply.ttl_levels = 0;
     reply.ttl_oes = 0;
     reply.ttl_overrides = 0;
-    for(i=0;i<CONFIG_RTIO_REGULAR_TTL_COUNT;i++) {
+    /* send at most 64 channels, the protocol doesn't support more */
+    for(i=0;i<min(CONFIG_RTIO_REGULAR_TTL_COUNT, 64);i++) {
         rtio_moninj_mon_chan_sel_write(i);
         rtio_moninj_mon_probe_sel_write(0);
         rtio_moninj_mon_value_update_write(1);

artiq/test/coredevice/test_rtio.py

@@ -249,6 +249,19 @@ class Handover(EnvExperiment):
         self.k("t2")
 
 
+class Rounding(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        t1 = now_mu()
+        delay(8*us)
+        t2 = now_mu()
+        self.set_dataset("delta", t2 - t1)
+
+
 class DummyException(Exception):
     pass
 
@@ -353,6 +366,11 @@ class CoredeviceTest(ExperimentCase):
         self.assertEqual(self.dataset_mgr.get("t1") + 1234,
                          self.dataset_mgr.get("t2"))
 
+    def test_rounding(self):
+        self.execute(Rounding)
+        dt = self.dataset_mgr.get("delta")
+        self.assertEqual(dt, 8000)
+
 
 
 class RPCTiming(EnvExperiment):

artiq/test/lit/codegen/error_illegal_return.py

@@ -0,0 +1,9 @@
+# RUN: %python -m artiq.compiler.testbench.signature +diag %s >%t
+# RUN: OutputCheck %s --file-to-check=%t
+
+# CHECK-L: ${LINE:+1}: error: this function must return a value of type numpy.int32 explicitly
+def foo(x):
+    if x:
+        return 1
+
+foo(True)

artiq/test/lit/codegen/noop_coercion.py

@@ -0,0 +1,4 @@
+# RUN: %python -m artiq.compiler.testbench.llvmgen %s
+
+def f():
+    return float(1.0)

artiq/test/lit/codegen/unreachable_implicit_return.py

@@ -0,0 +1,9 @@
+# RUN: %python -m artiq.compiler.testbench.signature %s
+
+def foo(x):
+    if x:
+        return 1
+    else:
+        return 2
+
+foo(True)

artiq/test/lit/embedding/method_on_instance.py

@@ -0,0 +1,22 @@
+# RUN: %python -m artiq.compiler.testbench.embedding %s
+
+from artiq.language.core import *
+from artiq.language.types import *
+
+class a:
+    def foo(self, x):
+        print(x)
+
+class b:
+    def __init__(self):
+        self.obj = a()
+        self.meth = self.obj.foo
+
+    @kernel
+    def run(self):
+        self.meth(1)
+
+bi = b()
+@kernel
+def entrypoint():
+    bi.run()

artiq/test/lit/embedding/warning_invariant_missing.py

@@ -0,0 +1,20 @@
+# RUN: %python -m artiq.compiler.testbench.embedding +diag %s 2>%t
+# RUN: OutputCheck %s --file-to-check=%t
+
+from artiq.language.core import *
+from artiq.language.types import *
+
+class c:
+    kernel_invariants = {"a", "b"}
+    a = 0
+
+    def __repr__(self):
+        return "<testbench.c object>"
+
+i = c()
+
+@kernel
+def entrypoint():
+    # CHECK-L: <synthesized>:1: warning: object <testbench.c object> of type <instance testbench.c> declares attribute 'b' as kernel invariant, but the instance referenced here does not have this attribute
+    # CHECK-L: ${LINE:+1}: note: expanded from here
+    i

artiq/test/lit/escape/error_mutable_aug_asgn.py

@@ -0,0 +1,12 @@
+# RUN: %python -m artiq.compiler.testbench.embedding +diag %s 2>%t
+# RUN: OutputCheck %s --file-to-check=%t
+
+from artiq.experiment import *
+
+@kernel
+def entrypoint():
+    a = [1,2]
+    # CHECK-L: ${LINE:+2}: error: values cannot be mutated in-place
+    # CHECK-L: ${LINE:+1}: note: try using `a = a + [3,4]`
+    a += [3,4]
+

artiq/test/lit/inferencer/builtin_calls.py

@@ -13,8 +13,8 @@ int()
 # CHECK-L: int:<constructor int>(1.0:float):numpy.int?
 int(1.0)
 
-# CHECK-L: int:<constructor int>(1.0:float, width=64:numpy.int?):numpy.int64
-int(1.0, width=64)
+# CHECK-L: int64:<function int64>(1.0:float):numpy.int64
+int64(1.0)
 
 # CHECK-L: float:<constructor float {}>():float
 float()

artiq/test/lit/inferencer/cast.py

@@ -0,0 +1,5 @@
+# RUN: %python -m artiq.compiler.testbench.inferencer +mono %s >%t
+# RUN: OutputCheck %s --file-to-check=%t
+
+# CHECK-L: numpy.int64
+int64(2)**32

artiq/test/lit/inferencer/error_builtin_calls.py

@@ -1,10 +1,6 @@
 # RUN: %python -m artiq.compiler.testbench.inferencer +diag %s >%t
 # RUN: OutputCheck %s --file-to-check=%t
 
-a = 1
-# CHECK-L: ${LINE:+1}: error: the width argument of int() must be an integer literal
-int(1.0, width=a)
-
 # CHECK-L: ${LINE:+1}: error: the argument of len() must be of an iterable type
 len(1)
 

artiq/test/lit/inferencer/error_coerce.py

@@ -28,10 +28,10 @@
 # CHECK-L: ${LINE:+1}: error: cannot coerce list(elt='a) to a numeric type
 [] - 1.0
 
-# CHECK-L: ${LINE:+2}: error: expression of type numpy.int? has to be coerced to float, which makes assignment invalid
+# CHECK-L: ${LINE:+2}: error: the result of this operation has type float, which cannot be assigned to a left-hand side of type numpy.int?
 # CHECK-L: ${LINE:+1}: note: expression of type float
 a = 1; a += 1.0
 
-# CHECK-L: ${LINE:+2}: error: the result of this operation has type (numpy.int?, float), which makes assignment to a slot of type (numpy.int?,) invalid
+# CHECK-L: ${LINE:+2}: error: the result of this operation has type (numpy.int?, float), which cannot be assigned to a left-hand side of type (numpy.int?,)
 # CHECK-L: ${LINE:+1}: note: expression of type (float,)
 b = (1,); b += (1.0,)

artiq/test/lit/integration/arithmetics.py

@@ -1,5 +1,5 @@
-# RUN: %python -m artiq.compiler.testbench.jit %s
 # RUN: %python %s
+# RUN: %python -m artiq.compiler.testbench.jit %s
 # REQUIRES: exceptions
 
 assert -(-1) == 1
@@ -20,6 +20,12 @@ assert 3 % 2 == 1
 assert -3 % 2 == 1
 assert 3 % -2 == -1
 assert -3 % -2 == -1
+assert -1 % 8 == 7
+#ARTIQ#assert int64(3) % 2 == 1
+#ARTIQ#assert int64(-3) % 2 == 1
+#ARTIQ#assert int64(3) % -2 == -1
+#ARTIQ#assert int64(-3) % -2 == -1
+assert -1 % 8 == 7
 assert 3.0 % 2.0 == 1.0
 assert -3.0 % 2.0 == 1.0
 assert 3.0 % -2.0 == -1.0
@@ -35,6 +41,24 @@ assert -1 >> 32 == -1
 assert 0x18 & 0x0f == 0x08
 assert 0x18 | 0x0f == 0x1f
 assert 0x18 ^ 0x0f == 0x17
+#ARTIQ#assert ~0x18 == -25
+#ARTIQ#assert ~int64(0x18) == -25
 
-assert [1] + [2] == [1, 2]
-assert [1] * 3 == [1, 1, 1]
+try:
+    1 / 0
+except ZeroDivisionError:
+    pass
+else:
+    assert False
+try:
+    1 // 0
+except ZeroDivisionError:
+    pass
+else:
+    assert False
+try:
+    1 % 0
+except ZeroDivisionError:
+    pass
+else:
+    assert False

artiq/test/lit/integration/array.py

@@ -3,3 +3,6 @@
 
 ary = array([1, 2, 3])
 assert [x*x for x in ary] == [1, 4, 9]
+
+assert [1] + [2] == [1, 2]
+assert [1] * 3 == [1, 1, 1]

artiq/test/lit/integration/builtin.py

@@ -7,7 +7,7 @@ assert bool() is False
 
 assert int() is 0
 assert int(1.0) is 1
-#ARTIQ#assert int(1, width=64) << 40 is 1099511627776
+#ARTIQ#assert int64(1) << 40 is 1099511627776
 
 #ARTIQ#assert float() is 0.0
 #ARTIQ#assert float(1) is 1.0

artiq/test/lit/integration/for.py

@@ -27,3 +27,27 @@ for x in range(10):
     assert False
 else:
     assert False
+
+# Verify continue target is reset in else block.
+cond = False
+while True:
+    if cond:
+        break
+    cond = True
+    for _ in range(1):
+        pass
+    else:
+        continue
+    assert False
+else:
+    assert False
+
+# Verify for target is reset in else block.
+while True:
+    for _ in range(1):
+        pass
+    else:
+        break
+    assert False
+else:
+    assert False

artiq/test/lit/integration/if.py

@@ -19,3 +19,9 @@ else:
 
 assert (0 if True else 1) == 0
 assert (0 if False else 1) == 1
+
+if 0:
+    assert True
+
+if 1:
+    assert True

artiq/test/lit/integration/while.py

@@ -29,3 +29,34 @@ while cond:
     cond = False
     continue
     assert False
+
+# Verify continue target is reset in else block.
+cond = False
+while True:
+    if cond:
+        break
+    cond = True
+    while False:
+        assert False
+    else:
+        continue
+    assert False
+else:
+    assert False
+
+# Verify break target is reset in else block.
+while True:
+    while False:
+        assert False
+    else:
+        break
+    assert False
+else:
+    assert False
+
+while 0:
+    assert False
+
+while 1:
+    assert True
+    break

artiq/test/lit/monomorphism/coercion.py

@@ -0,0 +1,10 @@
+# RUN: %python -m artiq.compiler.testbench.signature %s >%t
+# RUN: OutputCheck %s --file-to-check=%t
+
+def f(x):
+    x = int64(0)
+    return x
+
+# CHECK-L: g: ()->numpy.int64
+def g():
+    return f(1 + 0)

artiq/test/lit/regression/bug_659.py

@@ -0,0 +1,17 @@
+# RUN: %python -m artiq.compiler.testbench.embedding %s
+
+from artiq.language.core import *
+from artiq.language.types import *
+import numpy as np
+
+@kernel
+def rotate(array):
+    '''Rotates an array, deleting the oldest value'''
+    length = len(array)
+    for i in range(np.int64(len(array)) - 1):
+        array[length - i - 1] = array[length - i - 2]
+    array[0] = 0
+
+@kernel
+def entrypoint():
+    rotate([1,2,3,4])

artiq/test/lit/regression/device_db.pyon

@@ -0,0 +1,14 @@
+{
+    "comm": {
+        "type": "local",
+        "module": "artiq.coredevice.comm_dummy",
+        "class": "Comm",
+        "arguments": {}
+    },
+    "core": {
+        "type": "local",
+        "module": "artiq.coredevice.core",
+        "class": "Core",
+        "arguments": {"ref_period": 1e-9}
+    }
+}

conda/artiq-dev/meta.yaml

@@ -0,0 +1,47 @@
+package:
+  name: artiq-dev
+  version: {{ environ.get("GIT_DESCRIBE_TAG", "") }}
+
+source:
+  git_url: ../..
+
+build:
+  noarch: python
+  number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
+  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:8] }}
+
+requirements:
+  run:
+    - python >=3.5.3,<3.6
+    - setuptools 33.1.1
+    - migen 0.4
+    - misoc 0.3
+    - binutils-or1k-linux
+    - llvm-or1k
+    - llvmlite-artiq 0.10.0.dev py35_24
+    - openocd 0.10.0 1
+    - lit
+    - outputcheck
+    - coverage
+    - scipy
+    - numpy
+    - prettytable
+    - asyncserial
+    - sphinx 1.4.8
+    - sphinx-argparse
+    - sphinxcontrib-wavedrom
+    - sphinx_rtd_theme
+    - h5py
+    - dateutil
+    - pyqt >=5.5
+    - quamash
+    - pyqtgraph
+    - pygit2
+    - aiohttp
+    - pythonparser 1.0
+    - levenshtein
+
+about:
+  home: https://m-labs.hk/artiq
+  license: LGPL
+  summary: 'ARTIQ development metapackage'

conda/artiq-kc705-nist_clock/build.sh

@@ -11,4 +11,4 @@ cp misoc_nist_clock_kc705/gateware/top.bit $SOC_PREFIX
 cp misoc_nist_clock_kc705/software/bios/bios.bin $SOC_PREFIX
 cp misoc_nist_clock_kc705/software/runtime/runtime.fbi $SOC_PREFIX
 
-wget -P $SOC_PREFIX https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/master/bscan_spi_xc7k325t.bit
+wget -P $SOC_PREFIX https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/single-tap/bscan_spi_xc7k325t.bit

conda/artiq-kc705-nist_clock/meta.yaml

@@ -6,20 +6,18 @@ source:
   git_url: ../..
 
 build:
-  noarch_python: true
+  noarch: generic
+  ignore_prefix_files: True
   number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
-  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
+  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:8] }}
 
 requirements:
   build:
-    - migen 0.2
-    - misoc 0.2
-    - llvm-or1k
-    - binutils-or1k-linux
+    - artiq-dev {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:8]) if "GIT_DESCRIBE_TAG" in environ else "" }}
   run:
-    - artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_DESCRIBE_HASH")[1:]) if "GIT_DESCRIBE_TAG" in environ else "" }}
+    - artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:8]) if "GIT_DESCRIBE_TAG" in environ else "" }}
 
 about:
   home: https://m-labs.hk/artiq
-  license: GPL
-  summary: 'Bitstream, BIOS and runtime for NIST_QC2 on the KC705 board'
+  license: LGPL
+  summary: 'Bitstream, BIOS and runtime for NIST_CLOCK on the KC705 board'

conda/artiq-kc705-nist_qc1/build.sh

@@ -1,14 +0,0 @@
-#!/bin/bash
-
-BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
-[ -f $BUILD_SETTINGS_FILE ] && . $BUILD_SETTINGS_FILE
-
-SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-nist_qc1
-mkdir -p $SOC_PREFIX
-
-$PYTHON -m artiq.gateware.targets.kc705 -H nist_qc1 --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
-cp misoc_nist_qc1_kc705/gateware/top.bit $SOC_PREFIX
-cp misoc_nist_qc1_kc705/software/bios/bios.bin $SOC_PREFIX
-cp misoc_nist_qc1_kc705/software/runtime/runtime.fbi $SOC_PREFIX
-
-wget -P $SOC_PREFIX https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/master/bscan_spi_xc7k325t.bit

conda/artiq-kc705-nist_qc1/meta.yaml

@@ -1,25 +0,0 @@
-package:
-  name: artiq-kc705-nist_qc1
-  version: {{ environ.get("GIT_DESCRIBE_TAG", "") }}
-
-source:
-  git_url: ../..
-
-build:
-  noarch_python: true
-  number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
-  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
-
-requirements:
-  build:
-    - migen 0.2
-    - misoc 0.2
-    - llvm-or1k
-    - binutils-or1k-linux
-  run:
-    - artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_DESCRIBE_HASH")[1:]) if "GIT_DESCRIBE_TAG" in environ else "" }}
-
-about:
-  home: https://m-labs.hk/artiq
-  license: GPL
-  summary: 'Bitstream, BIOS and runtime for NIST_QC1 on the KC705 board'

conda/artiq-kc705-nist_qc2/build.sh

@@ -11,4 +11,4 @@ cp misoc_nist_qc2_kc705/gateware/top.bit $SOC_PREFIX
 cp misoc_nist_qc2_kc705/software/bios/bios.bin $SOC_PREFIX
 cp misoc_nist_qc2_kc705/software/runtime/runtime.fbi $SOC_PREFIX
 
-wget -P $SOC_PREFIX https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/master/bscan_spi_xc7k325t.bit
+wget -P $SOC_PREFIX https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/single-tap/bscan_spi_xc7k325t.bit

conda/artiq-kc705-nist_qc2/meta.yaml

@@ -6,20 +6,18 @@ source:
   git_url: ../..
 
 build:
-  noarch_python: true
+  noarch: generic
+  ignore_prefix_files: True
   number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
-  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
+  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:8] }}
 
 requirements:
   build:
-    - migen 0.2
-    - misoc 0.2
-    - llvm-or1k
-    - binutils-or1k-linux
+    - artiq-dev {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:8]) if "GIT_DESCRIBE_TAG" in environ else "" }}
   run:
-    - artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_DESCRIBE_HASH")[1:]) if "GIT_DESCRIBE_TAG" in environ else "" }}
+    - artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:8]) if "GIT_DESCRIBE_TAG" in environ else "" }}
 
 about:
   home: https://m-labs.hk/artiq
-  license: GPL
+  license: LGPL
   summary: 'Bitstream, BIOS and runtime for NIST_QC2 on the KC705 board'

conda/artiq-pipistrello-nist_qc1/meta.yaml

@@ -6,20 +6,18 @@ source:
   git_url: ../..
 
 build:
-  noarch_python: true
+  noarch: generic
+  ignore_prefix_files: True
   number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
-  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
+  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:8] }}
 
 requirements:
   build:
-    - migen 0.2
-    - misoc 0.2
-    - llvm-or1k
-    - binutils-or1k-linux
+    - artiq-dev {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:8]) if "GIT_DESCRIBE_TAG" in environ else "" }}
   run:
-    - artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_DESCRIBE_HASH")[1:]) if "GIT_DESCRIBE_TAG" in environ else "" }}
+    - artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:8]) if "GIT_DESCRIBE_TAG" in environ else "" }}
 
 about:
   home: http://m-labs.hk/artiq
-  license: GPL
+  license: LGPL
   summary: 'Bitstream, BIOS and runtime for NIST_QC1 on the Pipistrello board'

conda/artiq/build.sh

@@ -1,5 +0,0 @@
-#!/bin/bash
-
-ARTIQ_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq
-
-$PYTHON setup.py install --single-version-externally-managed --record=record.txt

conda/artiq/meta.yaml

@@ -5,37 +5,44 @@ package:
 source:
   git_url: ../..
 
+{% set data = load_setup_py_data() %}
+
 build:
-  noarch_python: true
+  noarch: python
   number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
-  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
+  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:8] }}
+  entry_points:
+    # NOTE: conda-build cannot distinguish between console and gui scripts
+    {% for entry_point_type, entry_points in data.get("entry_points", dict()).items() -%}
+    {% for entry_point in entry_points -%}
+    - {{ entry_point }}
+    {% endfor %}
+    {% endfor %}
+  script: $PYTHON setup.py install --single-version-externally-managed --record=record.txt
 
 requirements:
   build:
-    - python >=3.5.2
-    - setuptools
-    - numpy
-    - binutils-or1k-linux
+    - python >=3.5.3,<3.6
+    - setuptools 33.1.1
   run:
-    - python >=3.5.2
+    - python >=3.5.3,<3.6
     - llvmlite-artiq 0.10.0.dev py35_24
+    - binutils-or1k-linux
+    - pythonparser 1.0
+    - openocd 0.10.0 1
     - lit
     - outputcheck
     - scipy
     - numpy
     - prettytable
     - asyncserial
-    - sphinx
-    - sphinx-argparse
     - h5py
     - dateutil
-    - pyqt5
+    - pyqt >=5.5
     - quamash
-    - pyqtgraph
+    - pyqtgraph 0.10.0
     - pygit2
     - aiohttp
-    - binutils-or1k-linux
-    - pythonparser
     - levenshtein
 
 test:
@@ -44,5 +51,5 @@ test:
 
 about:
   home: https://m-labs.hk/artiq
-  license: GPL
+  license: LGPL
   summary: 'ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) is a next-generation control system for quantum information experiments. It is being developed in partnership with the Ion Storage Group at NIST, and its applicability reaches beyond ion trapping.'

doc/manual/_templates/layout.html

@@ -0,0 +1,18 @@
+{% extends "!layout.html" %}
+
+{# since sphinx_rtd_theme moves scripts to the end, hook up WaveDrom again #}
+{%- block footer %}
+{{ super() }}
+<script>(function(){
+	window.addEventListener(
+			"load",
+			(function(){ try {
+				WaveDrom.ProcessAll();
+			} catch(e) {} }),
+			false);
+})();</script>
+
+<div style="background-color: #FFBABA; color: #6A0E0E; position: fixed; min-width: 768px; top: 0; width: 100%; padding: 8px 20px 8px; font-size: 14px; line-height: 1.6; text-align: center; z-index: 300">
+WARNING: This document is for an old version of ARTIQ. For the most recent release go to <a href="https://m-labs.hk/artiq/manual/">https://m-labs.hk/artiq/manual/</a>.
+</div>
+{% endblock %}

doc/manual/compiler.rst

@@ -10,9 +10,10 @@ A number of Python features can be used inside a kernel for compilation and exec
 
 * Booleans
 * 32-bit signed integers (default size)
-* 64-bit signed integers (use ``int(n, width=64)`` to convert)
+* 64-bit signed integers (use ``numpy.int64`` to convert)
 * Double-precision floating point numbers
 * Lists of any supported types
+* String constants
 * User-defined classes, with attributes of any supported types (attributes that are not used anywhere in the kernel are ignored)
 
 For a demonstration of some of these features, see the ``mandelbrot.py`` example.
@@ -29,23 +30,50 @@ Kernel code can call host functions without any additional ceremony. However, su
 
 The Python types correspond to ARTIQ type annotations as follows:
 
-+-------------+-------------------------+
++---------------+-------------------------+
 | Python        | ARTIQ                   |
-+=============+=========================+
++===============+=========================+
 | NoneType      | TNone                   |
-+-------------+-------------------------+
++---------------+-------------------------+
 | bool          | TBool                   |
-+-------------+-------------------------+
-| int         | TInt32, TInt64          |
-+-------------+-------------------------+
++---------------+-------------------------+
+| int           | TInt32 or TInt64        |
++---------------+-------------------------+
 | float         | TFloat                  |
-+-------------+-------------------------+
++---------------+-------------------------+
 | str           | TStr                    |
-+-------------+-------------------------+
++---------------+-------------------------+
 | list of T     | TList(T)                |
-+-------------+-------------------------+
++---------------+-------------------------+
 | range         | TRange32, TRange64      |
-+-------------+-------------------------+
++---------------+-------------------------+
+| numpy.int32   | TInt32                  |
++---------------+-------------------------+
+| numpy.int64   | TInt64                  |
++---------------+-------------------------+
+| numpy.float64 | TFloat                  |
++---------------+-------------------------+
+
+Pitfalls
+--------
+
+The ARTIQ compiler accepts *nearly* a strict subset of Python 3. However, by necessity there
+is a number of differences that can lead to bugs.
+
+Arbitrary-length integers are not supported at all on the core device; all integers are
+either 32-bit or 64-bit. This especially affects calculations that result in a 32-bit signed
+overflow; if the compiler detects a constant that doesn't fit into 32 bits, the entire expression
+will be upgraded to 64-bit arithmetics, however if all constants are small, 32-bit arithmetics
+will be used even if the result will overflow. Overflows are not detected.
+
+The result of calling the builtin ``round`` function is different when used with
+the builtin ``float`` type and the ``numpy.float64`` type on the host interpreter; ``round(1.0)``
+returns an integer value 1, whereas ``round(numpy.float64(1.0))`` returns a floating point value
+``numpy.float64(1.0)``. Since both ``float`` and ``numpy.float64`` are mapped to
+the builtin ``float`` type on the core device, this can lead to problems in functions marked
+``@portable``; the workaround is to explicitly cast the argument of ``round`` to ``float``:
+``round(float(numpy.float64(1.0)))`` returns an integer on the core device as well as on the host
+interpreter.
 
 Additional optimizations
 ------------------------

doc/manual/conf.py

@@ -16,6 +16,7 @@
 import sys
 import os
 
+import sphinx_rtd_theme
 from unittest.mock import MagicMock
 
 
@@ -27,7 +28,13 @@ class Mock(MagicMock):
         return Mock()
 
 
-mock_modules = ["artiq.gui.moninj", "quamash", "pyqtgraph", "matplotlib"]
+mock_modules = ["artiq.gui.moninj",
+                "artiq.gui.waitingspinnerwidget",
+                "artiq.gui.flowlayout",
+                "quamash", "pyqtgraph", "matplotlib",
+                "numpy", "dateutil", "dateutil.parser", "prettytable", "PyQt5",
+                "h5py", "serial", "scipy", "scipy.interpolate", "asyncserial",
+                "llvmlite_artiq", "Levenshtein", "aiohttp"]
 
 for module in mock_modules:
     sys.modules[module] = Mock()
@@ -36,7 +43,7 @@ for module in mock_modules:
 # If extensions (or modules to document with autodoc) are in another directory,
 # add these directories to sys.path here. If the directory is relative to the
 # documentation root, use os.path.abspath to make it absolute, like shown here.
-sys.path.insert(0, os.path.abspath('..'))
+sys.path.insert(0, os.path.abspath('../..'))
 
 from artiq import __version__ as artiq_version
 
@@ -52,7 +59,9 @@ extensions = [
     'sphinx.ext.autodoc',
     'sphinx.ext.mathjax',
     'sphinx.ext.viewcode',
+    'sphinx.ext.napoleon',
     'sphinxarg.ext',
+    'sphinxcontrib.wavedrom',  # see also below for config
 ]
 
 # Add any paths that contain templates here, relative to this directory.
@@ -69,7 +78,7 @@ master_doc = 'index'
 
 # General information about the project.
 project = 'ARTIQ'
-copyright = '2014-2016, M-Labs Limited'
+copyright = '2014-2017, M-Labs Limited'
 
 # The version info for the project you're documenting, acts as replacement for
 # |version| and |release|, also used in various other places throughout the
@@ -123,24 +132,16 @@ pygments_style = 'sphinx'
 
 # The theme to use for HTML and HTML Help pages.  See the documentation for
 # a list of builtin themes.
-html_theme = 'classic'
+html_theme = 'sphinx_rtd_theme'
 
 # Theme options are theme-specific and customize the look and feel of a theme
 # further.  For a list of options available for each theme, see the
 # documentation.
-html_theme_options = {
-	'sidebarbgcolor': '#171814',
-	'sidebarlinkcolor': '#7389ae',
-	'sidebartextcolor': '#b3b3bb',
-	'footerbgcolor': '#171814',
-	'footertextcolor': '#b3b3bb',
-	'relbarbgcolor': '#171814',
-	'relbarlinkcolor': '#7389ae',
-	'relbartextcolor': '#b3b3bb',
-}
+html_theme_options = {}
 
 # Add any paths that contain custom themes here, relative to this directory.
 #html_theme_path = []
+html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
 
 # The name for this set of Sphinx documents.  If None, it defaults to
 # "<project> v<release> documentation".
@@ -151,7 +152,7 @@ html_theme_options = {
 
 # The name of an image file (relative to this directory) to place at the top
 # of the sidebar.
-html_logo = "../logo/artiq_white.png"
+html_logo = '../logo/artiq_white.png'
 
 # The name of an image file (within the static path) to use as favicon of the
 # docs.  This file should be a Windows icon file (.ico) being 16x16 or 32x32
@@ -290,3 +291,7 @@ texinfo_documents = [
 
 # If true, do not generate a @detailmenu in the "Top" node's menu.
 #texinfo_no_detailmenu = False
+
+# -- Options for sphinxcontrib-wavedrom -----------------------------------
+offline_skin_js_path = '_static/default.js'
+offline_wavedrom_js_path = '_static/WaveDrom.js'

doc/manual/core_device.rst

@@ -38,6 +38,12 @@ Common problems
 * When connected, QC1 and CLOCK adapters break the JTAG chain due to TDI not being connect to TDO on the FMC mezzanine.
 * On some boards, the JTAG USB connector is not correctly soldered.
 
+VADJ
+++++
+
+With the NIST CLOCK and QC2 adapters, for safe operation of the DDS buses (to prevent damage to the IO banks of the FPGA), the FMC VADJ rail of the KC705 should be changed to 3.3V. Plug the Texas Instruments USB-TO-GPIO PMBus adapter into the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software to configure (requires Windows). Write to chip number U55 (address 52), channel 4, which is the VADJ rail, to make it 3.3V instead of 2.5V.  Power cycle the KC705 board to check that the startup voltage on the VADJ rail is now 3.3V.
+
+
 NIST QC1
 ++++++++
 
@@ -149,8 +155,6 @@ To avoid I/O contention, the startup kernel should first program the TCA6424A ex
 
 See :mod:`artiq.coredevice.i2c` for more details.
 
-For safe operation of the DDS buses (to prevent damage to the IO banks of the FPGA), the FMC VADJ rail of the KC705 should be changed to 3.3V. Plug the Texas Instruments USB-TO-GPIO PMBus adapter into the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software to configure (requires Windows). Write to chip number U55 (address 52), channel 4, which is the VADJ rail, to make it 3.3V instead of 2.5V.  Power cycle the KC705 board to check that the startup voltage on the VADJ rail is now 3.3V.
-
 Pipistrello
 -----------
 

doc/manual/getting_started_core.rst

@@ -21,15 +21,9 @@ As a very first step, we will turn on a LED on the core device. Create a file ``
             self.core.reset()
             self.led.on()
 
-The central part of our code is our ``LED`` class, that derives from :class:`artiq.language.environment.EnvExperiment`. Among other features, ``EnvExperiment`` calls our ``build`` method and provides the ``setattr_device`` method that interfaces to the device database to create the appropriate device drivers and make those drivers accessible as ``self.core`` and ``self.led``. The ``@kernel`` decorator tells the system that the ``run`` method must be executed on the core device (instead of the host). The decorator uses ``self.core`` internally, which is why we request the core device using ``setattr_device`` like any other.
+The central part of our code is our ``LED`` class, that derives from :class:`artiq.language.environment.EnvExperiment`. Among other features, ``EnvExperiment`` calls our ``build`` method and provides the ``setattr_device`` method that interfaces to the device database to create the appropriate device drivers and make those drivers accessible as ``self.core`` and ``self.led``. The ``@kernel`` decorator tells the system that the ``run`` method must be compiled for and executed on the core device (instead of being interpreted and executed as regular Python code on the host). The decorator uses ``self.core`` internally, which is why we request the core device using ``setattr_device`` like any other.
 
-Copy the file ``device_db.pyon`` (containing the device database) from the ``examples/master`` folder of ARTIQ into the same directory as ``led.py`` (alternatively, you can use the ``--device-db`` option of ``artiq_run``). You can open PYON database files using a text editor - their contents are in a human-readable format. You will probably want to set the IP address of the core device in ``device_db.pyon`` so that the computer can connect to it (it is the ``host`` parameter of the ``comm`` entry). See :ref:`device-db` for more information. The example device database is designed for the NIST QC1 hardware on the KC705; see :ref:`board-ports` for RTIO channel assignments if you need to adapt the device database to a different hardware platform.
-
-.. note::
-    If the ``led`` device is a bidirectional TTL (i.e. ``TTLInOut`` instead of ``TTLOut``), you need to put it in output (driving) mode. Add the following at the beginning of ``run``: ::
-
-        self.led.output()
-        delay(0.1*us)
+Copy the file ``device_db.pyon`` (containing the device database) from the ``examples/master`` folder of ARTIQ into the same directory as ``led.py`` (alternatively, you can use the ``--device-db`` option of ``artiq_run``). You can open PYON database files using a text editor - their contents are in a human-readable format. You will probably want to set the IP address of the core device in ``device_db.pyon`` so that the computer can connect to it (it is the ``host`` parameter of the ``comm`` entry). See :ref:`device-db` for more information. The example device database is designed for the ``nist_clock`` hardware adapter on the KC705; see :ref:`board-ports` for RTIO channel assignments if you need to adapt the device database to a different hardware platform.
 
 .. note::
     To obtain the examples, you can find where the ARTIQ package is installed on your machine with: ::
@@ -42,8 +36,8 @@ Run your code using ``artiq_run``, which is part of the ARTIQ front-end tools: :
 
 The process should terminate quietly and the LED of the device should turn on. Congratulations! You have a basic ARTIQ system up and running.
 
-Host/core device interaction
-----------------------------
+Host/core device interaction (RPC)
+----------------------------------
 
 A method or function running on the core device (which we call a "kernel") may communicate with the host by calling non-kernel functions that may accept parameters and may return a value. The "remote procedure call" (RPC) mechanisms handle automatically the communication between the host and the device of which function to call, with which parameters, and what the returned value is.
 
@@ -77,12 +71,16 @@ You can then turn the LED off and on by entering 0 or 1 at the prompt that appea
 
 What happens is the ARTIQ compiler notices that the ``input_led_state`` function does not have a ``@kernel`` decorator and thus must be executed on the host. When the core device calls it, it sends a request to the host to execute it. The host displays the prompt, collects user input, and sends the result back to the core device, which sets the LED state accordingly.
 
-RPC functions must always return a value of the same type. When they return a non-``None`` value, the compiler should be informed in advance of the type of the value, which is what the ``-> TBool`` annotation is for.
+RPC functions must always return a value of the same type. When they return a value that is not ``None``, the compiler should be informed in advance of the type of the value, which is what the ``-> TBool`` annotation is for.
 
-The ``break_realtime`` call is necessary to waive the real-time requirements of the LED state change (as the ``input_led_state`` function can take an arbitrarily long time). This will become clearer later as we explain timing control.
+Without the ``break_realtime()`` call, the RTIO events emitted by ``self.led.on()`` or ``self.led.off()`` would be scheduled at a fixed and very short delay after entering ``run()``.
+These events would fail because the RPC to ``input_led_state()`` can take an arbitrary amount of time and therefore the deadline for submission of RTIO events would have long passed when ``self.led.on()`` or ``self.led.off()`` are called.
+The ``break_realtime()`` call is necessary to waive the real-time requirements of the LED state change.
+It advances the timeline far enough to ensure that events can meet the submission deadline.
 
-Real-time I/O
--------------
+
+Real-time I/O (RTIO)
+--------------------
 
 The point of running code on the core device is the ability to meet demanding real-time constraints. In particular, the core device can respond to an incoming stimulus or the result of a measurement with a low and predictable latency. We will see how to use inputs later; first, we must familiarize ourselves with how time is managed in kernels.
 
@@ -99,18 +97,28 @@ Create a new file ``rtio.py`` containing the following: ::
         @kernel
         def run(self):
             self.core.reset()
+            self.ttl0.output()
             for i in range(1000000):
-                self.ttl0.pulse(2*us)
                 delay(2*us)
+                self.ttl0.pulse(2*us)
 
+In its ``build()`` method, the experiment obtains the core device and a TTL device called ``ttl0`` as defined in the device database.
+In ARTIQ, TTL is used roughly synonymous with "a single generic digital signal" and does not refer to a specific signaling standard or voltage/current levels.
 
-.. note::
-    If ``ttl0`` is a bidirectional channel (``TTLInOut``), it is in input (non-driving) mode by default. You need to call ``self.ttl0.output()`` as explained above for the LED.
+When ``run()``, the experiment first ensures that ``ttl0`` is in output mode and actively driving the device it is connected to.
+Bidirectional TTL channels (i.e. ``TTLInOut``) are in input (high impedance) mode by default, output-only TTL channels (``TTLOut``) are always in output mode.
+There are no input-only TTL channels.
 
+The experiment then drives one million 2 µs long pulses separated by 2 µs each.
+Connect an oscilloscope or logic analyzer to TTL0 and run ``artiq_run.py rtio.py``.
+Notice that the generated signal's period is precisely 4 µs, and that it has a duty cycle of precisely 50%.
+This is not what you would expect if the delay and the pulse were implemented with register-based general purpose input output (GPIO) that is CPU-controlled.
+The signal's period would depend on CPU speed, and overhead from the loop, memory management, function calls, etc, all of which are hard to predict and variable.
+Any asymmetry in the overhead would manifest itself in a distorted and variable duty cycle.
 
-Connect an oscilloscope or logic analyzer to TTL0 and run ``artiq_run.py led.py``. Notice that the generated signal's period is precisely 4 microseconds, and that it has a duty cycle of precisely 50%. This is not what you would expect if the delay and the pulse were implemented with CPU-controlled GPIO: overhead from the loop management, function calls, etc. would increase the signal's period, and asymmetry in the overhead would cause duty cycle distortion.
+Instead, inside the core device, output timing is generated by the gateware and the CPU only programs switching commands with certain timestamps that the CPU computes.
 
-Instead, inside the core device, output timing is generated by the gateware and the CPU only programs switching commands with certain timestamps that the CPU computes. This guarantees precise timing as long as the CPU can keep generating timestamps that are increasing fast enough. In case it fails to do that (and attempts to program an event with a timestamp in the past), the :class:`artiq.coredevice.exceptions.RTIOUnderflow` exception is raised. The kernel causing it may catch it (using a regular ``try... except...`` construct), or it will be propagated to the host.
+This guarantees precise timing as long as the CPU can keep generating timestamps that are increasing fast enough. In case it fails to do that (and attempts to program an event with a timestamp smaller than the current RTIO clock timestamp), a :class:`artiq.coredevice.exceptions.RTIOUnderflow` exception is raised. The kernel causing it may catch it (using a regular ``try... except...`` construct), or it will be propagated to the host.
 
 Try reducing the period of the generated waveform until the CPU cannot keep up with the generation of switching events and the underflow exception is raised. Then try catching it: ::
 
@@ -135,6 +143,38 @@ Try reducing the period of the generated waveform until the CPU cannot keep up w
             except RTIOUnderflow:
                 print_underflow()
 
+
+Parallel and sequential blocks
+------------------------------
+
+It is often necessary that several pulses overlap one another. This can be expressed through the use of ``with parallel`` constructs, in which the events generated by the individual statements are executed at the same time. The duration of the ``parallel`` block is the duration of its longest statement.
+
+Try the following code and observe the generated pulses on a 2-channel oscilloscope or logic analyzer: ::
+
+    for i in range(1000000):
+        with parallel:
+            self.ttl0.pulse(2*us)
+            self.ttl1.pulse(4*us)
+        delay(4*us)
+
+ARTIQ can implement ``with parallel`` blocks without having to resort to any of the typical parallel processing approaches.
+It simply remembers the position on the timeline when entering the ``parallel`` block and then seeks back to that position after submitting the events generated by each statement.
+In other words, the statements in the ``parallel`` block are actually executed sequentially, only the RTIO events generated by them are scheduled to be executed in parallel.
+Note that if a statement takes a lot of CPU time to execute (this different from the events scheduled by a statement taking a long time), it may cause a subsequent statement to miss the deadline for timely submission of its events.
+This then causes a ``RTIOUnderflow`` exception to be raised.
+
+Within a parallel block, some statements can be made sequential again using a ``with sequential`` construct. Observe the pulses generated by this code: ::
+
+    for i in range(1000000):
+        with parallel:
+            with sequential:
+                self.ttl0.pulse(2*us)
+                delay(1*us)
+                self.ttl0.pulse(1*us)
+            self.ttl1.pulse(4*us)
+        delay(4*us)
+
+
 RTIO analyzer
 -------------
 
@@ -157,30 +197,3 @@ The core device records the real-time I/O waveforms into a circular buffer. It i
                 delay(...)
 
 Afterwards, the recorded data can be extracted and written to a VCD file using ``artiq_coreanalyzer -w rtio.vcd`` (see: :ref:`core-device-rtio-analyzer-tool`). VCD files can be viewed using third-party tools such as GtkWave.
-
-Parallel and sequential blocks
-------------------------------
-
-It is often necessary that several pulses overlap one another. This can be expressed through the use of ``with parallel`` constructs, in which all statements execute at the same time. The execution time of the ``parallel`` block is the execution time of its longest statement.
-
-Try the following code and observe the generated pulses on a 2-channel oscilloscope or logic analyzer: ::
-
-    for i in range(1000000):
-        with parallel:
-            self.ttl0.pulse(2*us)
-            self.ttl1.pulse(4*us)
-        delay(4*us)
-
-Within a parallel block, some statements can be made sequential again using a ``with sequential`` construct. Observe the pulses generated by this code: ::
-
-    for i in range(1000000):
-        with parallel:
-            with sequential:
-                self.ttl0.pulse(2*us)
-                delay(1*us)
-                self.ttl0.pulse(1*us)
-            self.ttl1.pulse(4*us)
-        delay(4*us)
-
-.. note::
-    Branches of a ``parallel`` block are executed one after another, with a reset of the internal RTIO time variable before moving to the next branch. If a branch takes a lot of CPU time, it may cause an underflow when the next branch begins its execution.

doc/manual/index.rst

@@ -10,6 +10,7 @@ Contents:
     installing
     installing_from_source
     release_notes
+    rtio
     getting_started_core
     compiler
     getting_started_mgmt

doc/manual/installing.rst

@@ -31,7 +31,11 @@ Executing just ``conda`` should print the help of the ``conda`` command [1]_.
 Installing the ARTIQ packages
 -----------------------------
 
-Add the M-Labs ``main`` Anaconda package repository containing stable releases and release candidates to your conda configuration::
+First add the conda-forge repository containing ARTIQ dependencies to your conda configuration::
+
+    $ conda config --add channels http://conda.anaconda.org/conda-forge/label/main
+
+Then add the M-Labs ``main`` Anaconda package repository containing stable releases and release candidates::
 
     $ conda config --add channels http://conda.anaconda.org/m-labs/label/main
 

doc/manual/installing_from_source.rst

@@ -43,10 +43,9 @@ and the ARTIQ kernels.
 * Install LLVM and Clang: ::
 
         $ cd ~/artiq-dev
-        $ git clone https://github.com/openrisc/llvm-or1k
-        $ cd llvm-or1k/tools
-        $ git clone https://github.com/openrisc/clang-or1k clang
-        $ cd ..
+        $ git clone -b artiq-3.8 https://github.com/m-labs/llvm-or1k
+        $ cd llvm-or1k
+        $ git clone -b artiq-3.8 https://github.com/m-labs/clang-or1k tools/clang
 
         $ mkdir build
         $ cd build
@@ -89,8 +88,8 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
         ::
 
             $ cd ~/artiq-dev
-            $ wget https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/master/bscan_spi_xc7k325t.bit
-            $ wget https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/master/bscan_spi_xc6slx45.bit
+            $ wget https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/single-tap/bscan_spi_xc7k325t.bit
+            $ wget https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/single-tap/bscan_spi_xc6slx45.bit
 
         Then move both files ``~/artiq-dev/bscan_spi_xc6slx45.bit`` and ``~/artiq-dev/bscan_spi_xc7k325t.bit`` to ``~/.migen``, ``/usr/local/share/migen``, or ``/usr/share/migen``.
 
@@ -146,7 +145,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
 
         $ python3.5 -m artiq.gateware.targets.kc705 -H nist_qc1  # or nist_qc2
 
-    .. note:: Add ``--toolchain vivado`` if you wish to use Vivado instead of ISE.
+    .. note:: Add ``--toolchain ise`` if you wish to use ISE instead of Vivado.
 
 * Then, gather the binaries and flash them: ::