Commit Graph

1006 Commits

Author SHA1 Message Date
f79f7db3a2 dyld: handle rebind on symbols relocated by CALL_PLT 2022-06-01 12:44:33 +08:00
872f8f039f dyld: support additional RV32 reloc types
The support of LO12 type requires the runtime linker to find the corresponding HI20 symbol. resolve_rela needs the entire relocation section for that.
2022-06-01 12:44:33 +08:00
50495097e5 dyld: rename pltrel to jmprel
nac3ld will not generate PLT & its relocation section. There might not be a pltrel in that case.
On the other hand, rebinding will not be limited to the symbols in the PLT when linked with nac3ld.
Thus the renaming.
2022-06-01 12:44:33 +08:00
4bdb4c8e11 config: error instead of empty value if key not found 2022-05-19 16:48:59 +08:00
50dbda4f43 Use new ip_addr_storage module instead of net_settings
Necessary to avoid needing the alloc only trait impls in net_settings
when compiling the bootloader.
2022-04-24 10:10:43 +08:00
95378cf9c9 Centralise all uses of the IPv4 index in net_settings.rs 2022-04-24 10:10:43 +08:00
671453938b Require explicitly closing TcpStreams
Instead of automatically closing and draining the TcpStream in the Drop
implementation instead expect the user to call TcpStream::close.
Add close called to all users of TcpStream.
Document the requirement to call close on TcpListener::accept, this seems
to be the only way to get a new TcpStream at the moment.
2022-04-24 10:10:43 +08:00
1fe59d27dc Use an Ipv4AddrConfig enum instead of the USE_DHCP constant 2022-04-24 10:10:43 +08:00
73082d116f Ensure that pending data is sent when closing sockets
This is only necessary if close hasn't been called on the socket
but that's not always done. e.g. by the core analyzer server.
2022-04-24 10:10:43 +08:00
596b9a265c Prefer DHCP to the built-in static IPs
Signed-off-by: Michael Birtwell <michael.birtwell@oxionics.com>
2022-04-24 10:10:42 +08:00
6ffb1f83ee DHCP support for core device firmware
DHCP is enabled by setting the `ip` config entry to "use_dhcp". Reusing this
config field rather than creating a new one means that there is no ambiguity
over which config field takes precedence.

Adds a thread to configure the interface based on DHCP events
Adds a `Dhcpv4Socket` as a wrapper around smoltcp's version
Formalises the storage of the IP addresses so that we can update one in
another module.

There's also a workaround for the first DHCP discover packet frequently
going missing.

Signed-off-by: Michael Birtwell <michael.birtwell@oxionics.com>
2022-04-24 10:10:14 +08:00
c60de48a30 Upgrade smoltcp 0.6.0 -> 0.8.0
Main changes:
Deal with interfaces now being generic over mediums, update interface name
and initialisation.
Interfaces now own their sockets. So we store a reference to the Interface
instead of the SocketSet in Scheduler and IO.
Sockets are no longer reference counted. We never called the function to
increase the socket's reference count, so now we just remove it where it
was previously released. This will result in the socket being dropped at
a different time, but I think that should be fine.

Tested firmware upload to the bootloader and spamming artiq_coremgmt log
calls to download the log from the firmware.

Signed-off-by: Michael Birtwell <michael.birtwell@oxionics.com>
2022-04-24 10:09:27 +08:00
c82c358f3a runtime: provide/fix more libc mem functions 2022-03-28 13:33:57 +08:00
723f41c78b runtime: fix EXCEPTION_ID_LOOKUP 2022-03-26 20:10:24 +08:00
866a83796a firmware: add UnwrapNoneError exception 2022-03-26 15:28:13 +08:00
65d2dd0173 fix compilation warning 2022-03-20 16:15:01 +08:00
922d2b1619 drop support for big-endian moninj 2022-03-19 22:58:31 +08:00
aff569b2c3 firmware: support 64-bit moninj probes 2022-03-17 19:56:07 +08:00
a159ef642d drtio: demote default routing table message to info 2022-03-16 21:22:35 +08:00
ebfeb1869f firmware: use &CSlice for lists 2022-03-10 16:30:22 +08:00
8415151866 update copyright year 2022-03-10 11:56:16 +08:00
232f28c0e8 kern_hw: fix return type 2022-03-04 15:16:14 +08:00
51fa1b5e5e drtio: fix i2c switch 2022-03-04 15:16:14 +08:00
a85b4d5f5e
I2C API for PCA9547 support (#1860) 2022-03-01 15:07:53 +08:00
0da7b83176 runtime: add nac3 exception symbols 2022-02-23 11:04:53 +08:00
David Nadlinger
e45cb217be firmware: Explicitly use wrapping integer math in PRNGs
Patch by Hannah McLaughlin; apparently, the overflow actually
doesn't get checked/reported without `opt-level = 2` and
`lto = "thin"`.
2022-02-03 23:57:17 +00:00
Steve Fan
34008b7a21
Backport of "fixes alignment and size problem" from artiq-zynq (#1841) 2022-01-28 20:49:55 +08:00
4132c450a5 firmware: runtime changes for exception
Ported from:
M-Labs/artiq-zynq#162

This includes new API for exception handling, some refactoring to avoid
code duplication for exception structures, and modified protocols to
send nested exceptions and avoid string allocation.
2022-01-26 07:16:54 +08:00
4e3e0d129c firmware: fix compilation warning 2022-01-11 09:31:26 +08:00
12ee326fb4 firmware: fixed personality function 2022-01-11 09:30:19 +08:00
Steve Fan
4a6bea479a
Host report for async error upon kernel termination (#1791)
Closes #1644
2021-12-04 13:33:24 +08:00
f281112779 satman: add 100mhz si5324 settings
siphaser: add calculated vco for 100mhz comment
2021-12-03 17:19:11 +08:00
9423428bb0 drtio: fix crc32 offset address 2021-11-24 12:00:56 +08:00
db3e5e83e6 bump misoc 2021-11-08 16:59:08 +08:00
531670d6c5 dyld: check ABI 2021-11-08 16:59:08 +08:00
03b803e764 firmware: adjust csr separation 2021-11-08 16:59:08 +08:00
b3e315e24a rust: find json file using CARGO_TRIPLE 2021-11-08 16:59:08 +08:00
0898e101e2 board_misoc: reuse riscv dir for comm & kernel 2021-11-08 16:59:08 +08:00
69cddc6b86
rtio_clocking: add warnings for unsupported rtio_clock settings (#1773) 2021-10-28 16:34:22 +08:00
9b1d7e297d
runtime: clock input specification improvements
closes #1735
2021-10-28 16:21:51 +08:00
d5fa3d131a cargo.lock: update libc version for libfringe 2021-10-16 17:42:24 +08:00
6d3164a912 riscv: print mtval on panic 2021-10-16 17:42:24 +08:00
46326716fd runtime: bump libfringe, impl ecall abi
See libfringe PR: M-Labs/libfringe#1
2021-10-16 17:42:24 +08:00
0a59c889de satman/kern: init locked PMP on startup 2021-10-16 17:42:24 +08:00
27a7a96626 runtime: setup pmp + transfer to user 2021-10-16 17:42:24 +08:00
a0bf11b465 riscv: impl pmp 2021-10-16 17:42:24 +08:00
790a20edf6 linker: generate stack guard + symbol 2021-10-16 17:42:24 +08:00
35d21c98d3 Revert "runtime: expose rint from libm"
Consistency with NAR3/Zynq where rint is not available.

This reverts commit f5100702f6.
2021-10-11 08:12:04 +08:00
f5100702f6 runtime: expose rint from libm 2021-10-10 20:40:17 +08:00
59065c4663 alloc_list: support alloc w/ large align
Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
2021-10-07 12:38:03 +08:00
2d79d824f9 firmware: remove minor or1k leftovers 2021-09-12 20:03:37 +08:00
a573dcf3f9 board_misoc/build: use rv32 as target arg
The original rv64 argument was only to match the misoc counterpart.
2021-09-10 14:11:23 +08:00
448974fe11 runtime/main: cleanup 2021-09-10 13:59:53 +08:00
b091d8cb66 kernel: flush cache before mod_init
This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
2021-09-10 13:25:12 +08:00
b8ed5a0d91 alloc: fix alignment for riscv32 arch 2021-09-10 13:25:12 +08:00
2213e7ffac ksupp/rtio/exception: fix timestamp 2021-09-10 13:25:12 +08:00
09ffd9de1e dma: fix timestamp fetch 2021-09-10 13:25:12 +08:00
c6ba0f3cf4 ksupport: fix dma cslice (ffi) 2021-09-10 13:25:12 +08:00
c812a837ab runtime: enlarge stack size 2021-09-10 13:25:12 +08:00
a596db404d satman: fix cargo xbuild sysroot 2021-09-10 13:25:12 +08:00
4fab267593 cargo: std dependency hack 2021-09-10 13:25:12 +08:00
dcbd9f905c cargo: use cargo xbuild 2021-09-10 13:25:12 +08:00
9f6b3f6014 firmware: clarify target triple
The lack of compressed instruction support can be inferred from the target triple, literally.
2021-09-10 13:25:12 +08:00
6db7280b09 flake: board package WIP 2021-09-10 13:25:12 +08:00
d8ac429059 dyld: streamline lib.rs
Only riscv32 is supported anyway, no need to have excessive architecture check.
2021-09-10 13:25:12 +08:00
798774192d slave_fpga/bootloader: read in little endian 2021-09-10 13:25:12 +08:00
eecd825d23 firmware: suppress warning 2021-09-10 13:25:12 +08:00
1da0554a49 pcr: purge 2021-09-10 13:25:12 +08:00
70507e1b72 Cargo.lock: update 2021-09-10 13:25:12 +08:00
c113cd6bf5 libfringe: bump 2021-09-10 13:25:12 +08:00
61b0170a12 firmware: purge or1k 2021-09-10 13:25:12 +08:00
af263ffe1f ksupport: fix rpc, cache signature (FFI)
The reason of the borrow stuff is explained in M-Labs/artiq-zynq#76 (artiq-zyna repo).
As for `cache_get()`, compiler will perform stack allocation to pre-allocate the returned structure, and pass to cache_get alongside the `key`.
However, ksupport fails to recognize the passed memory, so it will always assume the passed memory as the key.
2021-09-10 13:25:12 +08:00
8fa47b8119 rpc: enforce alignment 2021-09-10 13:25:12 +08:00
de0f2d4a28 firmware: adopt endianness protocol in artiq-zynq
Related:
artiq-zynq: M-Labs/artiq-zynq#126
artiq: #1588
2021-09-10 13:25:12 +08:00
9afe63c08a ksupport: fix proto_artiq dependency 2021-09-10 13:25:12 +08:00
29a2f106d1 ksupport: replace asm with llvm_asm 2021-09-10 13:25:12 +08:00
279593f984 ksupport.ld: merge sbss with bss 2021-09-10 13:25:12 +08:00
1ba8c8dfee runtime: remove irq again 2021-09-10 13:25:12 +08:00
3d629006df makefiles: revert byte-swaps 2021-09-10 13:25:12 +08:00
7542105f0f board_misoc: remove pcr
VexRiscv seems to not support additional hardware performance counter, at least I have not seen any documentation on how to use it.
2021-09-10 13:25:12 +08:00
01ca114c66 runtime: remove irq dependency 2021-09-10 13:25:12 +08:00
36171f2c61 runtime: remove inaccurate sp on panic 2021-09-10 13:25:12 +08:00
01e357e5d3 ksupport.ld: reduce load section alignment 2021-09-10 13:25:12 +08:00
1293e0750e ld, makefiles: use ld.lld 2021-09-10 13:25:12 +08:00
5656e52581 remove profiler 2021-09-10 13:25:12 +08:00
1b8b4baf6a ksupport: fix panic, libc, unwind 2021-09-10 13:25:12 +08:00
905330b0f1 ksupport: handle riscv exceptions 2021-09-10 13:25:12 +08:00
50a62b3d42 liballoc: change align to 16 bytes 2021-09-10 13:25:12 +08:00
7f0bc9f7f0 runtime/makefile: specify emulation, flip endianness 2021-09-10 13:25:12 +08:00
c42adfe6fd runtime.ld: merge .sbss & .bss 2021-09-10 13:25:12 +08:00
f56152e72f rust: fix dependencies 2021-09-10 13:25:12 +08:00
c800b6c8d3 runtime: update rust alloc, managed 2021-09-10 13:25:09 +08:00
e99061b013 runtime: add riscv 2021-09-10 13:23:22 +08:00
ecedec577c runtime: impl riscv exception handling 2021-09-10 13:23:15 +08:00
252594a606 runtime: impl riscv panic handler 2021-09-10 13:20:31 +08:00
31bf17563c personality: update from rust/panic_unwind 2021-09-10 13:20:31 +08:00
bfddd8a30f libdyld: add riscv support 2021-09-10 13:20:31 +08:00
ad3037d0f6 libc: add minimal C types 2021-09-10 13:20:31 +08:00
daaf6c3401 libunwind: add rust interface 2021-09-10 13:20:31 +08:00
6d9cebfd42 satman: handle .sbss generation 2021-09-10 13:20:31 +08:00