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3749 Commits

Author SHA1 Message Date
whitequark 86c027e9c5 artiq_flash: don't require binaries to merely restart FPGA. 2017-07-04 18:55:38 +00:00
whitequark ee1d5dbccb runtime: allow a much larger log buffer and avoid hacks. 2017-07-04 18:18:31 +00:00
whitequark 7a5fbc1622 devtool: forward port 1383 (moninj). 2017-07-04 17:54:18 +00:00
whitequark 4e5ea1bbaf dashboard: fix a crash touching moninj without a connection. 2017-07-04 17:53:48 +00:00
Robert Jördens 2f1029c292 Revert "sawg: advance dds 1/2 by one sample group" 
This reverts commit 8e0a1cbdc8.

c.f. #772

The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
 2017-07-04 17:55:19 +02:00
Robert Jördens 8e0a1cbdc8 sawg: advance dds 1/2 by one sample group 
closes #772
 2017-07-04 16:51:58 +02:00
Robert Jördens 91ca9fbcad sawg: also give offset some headroom 
closes #771
 2017-07-04 16:50:06 +02:00
Robert Jördens 78d1f0fdf6 sawg: fix PhasedAccu resets 2017-07-04 11:56:21 +02:00
Florent Kermarrec 2910b1be5e artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect 2017-07-04 10:48:06 +02:00
Sebastien Bourdeauducq 838127d914 rtio: break DMA timing path 2017-07-02 10:24:01 +08:00
whitequark ea7549cfa4 compiler: coerce `while` condition to bool. 
Fixes #768.
 2017-07-01 18:59:07 +00:00
Robert Jördens 911ee4a959 rtio: make pipelined logic reset_less 
* latency-corrected counters
* registered error logic
 2017-06-29 12:55:32 +02:00
Robert Jördens 600a48ac61 dsp.fir: cleanup 2017-06-29 12:18:48 +02:00
Robert Jördens dca662a743 dsp.fir: pipeline final systolic adder 2017-06-29 11:33:19 +02:00
Robert Jördens 32a33500c8 dsp.fir: actively cull zero delays 2017-06-29 11:24:56 +02:00
Robert Jördens f520d4a768 rtio: undo _RelaxedAsyncResetSynchronizer 2017-06-28 22:08:15 +02:00
Robert Jördens 3cbbcdfe96 sawg: don't enable_replace for Config 
closes #762
 2017-06-28 20:31:40 +02:00
Robert Jördens f2632e0fd1 sawg: adapt latency to fir changes 
closes #748
 2017-06-28 20:12:30 +02:00
Robert Jördens e7db2c6578 dsp.accu: reset_less outputs 2017-06-28 20:04:58 +02:00
Robert Jördens 6bb994228f dsp.fir: drop x shift 2017-06-28 19:55:15 +02:00
Robert Jördens 01847271c5 rtio: use reset_less signal for reset fanout 2017-06-28 19:43:55 +02:00
Robert Jördens b9859cc0c3 dsp.fir: remove old/wrong comment 2017-06-28 19:21:57 +02:00
Robert Jördens 55b5b87490 fir: simplify latency compensation 
Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
 2017-06-28 19:13:43 +02:00
Robert Jördens d1e5dd334f sawg: use pipeline reset 2017-06-28 19:09:39 +02:00
Robert Jördens 6418205906 dsp.fir: use pipelin-reset 2017-06-28 19:09:21 +02:00
whitequark 6a49c114c8 runtime: update smoltcp. 2017-06-28 00:27:22 +00:00
whitequark 370f22541c runtime: update smoltcp. 2017-06-27 21:06:45 +00:00
whitequark f36f00a83d artiq_devtool: do not chop up the TCP stream into 1024 byte chunks. 
This makes the smoltcp behavior quite different than without
the TCP forwarding (and can mask smoltcp issues).
 2017-06-26 08:39:16 +00:00
whitequark 282f4256e0 artiq_pcap: atomically replace pcap file. 
Otherwise this segfaults Wireshark (?!).
 2017-06-26 03:22:14 +00:00
whitequark d6f4f1f3bc artiq_devtool, artiq_pcap: better option naming. 2017-06-26 00:00:05 +00:00
whitequark 6061393bd0 tools: lazily import paramiko. 2017-06-25 07:17:03 +00:00
whitequark 816ec6c52f artiq_pcap: implement. 2017-06-25 07:04:29 +00:00
whitequark 69fa9b38e0 test: actually run test_embedding.AsyncTest. 2017-06-25 05:28:32 +00:00
whitequark 31b52ff1b3 coredevice: do not desync kernel TCP stream on RPCReturnValueError. 
And propagate the error upwards instead of trying to squeeze it
through the core device in futility.
 2017-06-25 04:47:32 +00:00
whitequark fdb24ef139 coredevice: truncate overlong exception messages. 
If we have a really long one (megabytes) then this may exhaust
the heap of the core device and crash it.
 2017-06-25 04:39:08 +00:00
whitequark 1fa8be3835 artiq_devtool: don't loop forever if core device dies. 2017-06-25 04:18:45 +00:00
whitequark f17a6616b2 runtime: ensure management interface buffer can hold log buffer. 
Otherwise we get weird edge cases where the network stack could try
to append to log buffer while management interface is holding
the log buffer and trying to push it out, and it's just no good.

The serialized log buffer at its maximum length is slightly longer
than 32 KiB, so we just allocate the largest possible TCP buffer
to the management interface to keep it simple.
 2017-06-24 17:09:28 +00:00
whitequark d0f72632e1 language: export TBytes and TByteArray. 2017-06-24 17:03:35 +00:00
whitequark 12357d884e runtime: update smoltcp. 2017-06-24 16:55:59 +00:00
Robert Jördens 07f5e99140 dsp/sat_add: works after previous changes 2017-06-22 18:24:22 +02:00
Robert Jördens f78d5a87e9 dsp/test: skip and fix sat_add 2017-06-22 18:01:31 +02:00
Robert Jördens 47928a2c0d sawg: disable limiter 
temporary workaround to permit testing other aspects
 2017-06-22 17:31:04 +02:00
Robert Jördens cd2ac53bc5 dsp/sat_add: make width mandatory 2017-06-22 17:28:39 +02:00
Robert Jördens 9b940aa876 dsp/sat_add: spell out logic more 2017-06-22 16:55:13 +02:00
Robert Jördens d0cf0f2b87 sawg/limiter: make signed signals explicitly 2017-06-22 13:44:36 +02:00
Robert Jördens 53be34a25f sawg: clear phase accu in reset 2017-06-22 13:27:49 +02:00
Robert Jördens 694f8d784c dsp/tools: unittest sat_add 2017-06-22 11:29:56 +02:00
Robert Jördens bd1438d28e sawg: wrap limits init values 2017-06-22 10:26:29 +02:00
Robert Jördens cccd01e81e sawg: cleanup sat_add logic 2017-06-22 10:26:29 +02:00
Robert Jördens 5f6e665158 test/sawg: patch delay_mu 2017-06-22 10:26:29 +02:00
Robert Jördens 570f2cc1ff dsp/tools/SatAdd: fix reuse of clipped signal 2017-06-22 10:26:29 +02:00
Robert Jördens 4b3aad2563 sawg: clean up Config 
* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
 2017-06-22 10:26:29 +02:00
Robert Jördens f4c6879c76 sawg: special case Config RTIO address 2017-06-22 10:26:29 +02:00
Robert Jördens ff0da2c9fc sawg: stage code for y-data exchange on channels 2017-06-22 10:26:29 +02:00
Robert Jördens b6569df02f dsp/tools: clean up SatAddMixin logic 2017-06-22 10:26:29 +02:00
Robert Jördens f369cb97f7 sawg/examples: add a bit more slack 2017-06-22 10:26:29 +02:00
Chris Ballance 05b57f5110 protocols: increase another asyncio line limit (#671) 2017-06-22 09:43:52 +08:00
Sebastien Bourdeauducq c2cc29142d drtio: remove misleading comment from device_db 2017-06-21 18:34:53 +08:00
Sebastien Bourdeauducq 6262969d46 test: relax test_dma_record_time 2017-06-21 18:33:58 +08:00
Sebastien Bourdeauducq 64ce85445c drtio: add remote converter SPI example (#740) 2017-06-21 17:08:12 +08:00
Sebastien Bourdeauducq 74cf074538 drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times 2017-06-21 17:01:52 +08:00
Sebastien Bourdeauducq 66dee9d1ad drtio: send/process I2C and SPI aux packets (#740) 2017-06-21 16:50:51 +08:00
Sebastien Bourdeauducq f58f16ccd4 drtioaux: add default timeout 2017-06-21 16:23:11 +08:00
Sebastien Bourdeauducq 7675dd063b drtioaux: add I2C and SPI packets (#740) 2017-06-21 14:07:16 +08:00
Sebastien Bourdeauducq c74de6ae96 phaser: reintroduce test_ad9154_status 2017-06-20 00:49:57 +08:00
Sebastien Bourdeauducq 8c56a95fa2 spi: add default busno 2017-06-20 00:49:38 +08:00
Sebastien Bourdeauducq 39ddb66f0f phaser: add AD9154 SPI access driver to example ddb 2017-06-20 00:49:21 +08:00
Sebastien Bourdeauducq 470bce6214 coredevice: add AD9154 SPI access driver 2017-06-20 00:48:50 +08:00
Sebastien Bourdeauducq a6d06824e7 fix indentation 2017-06-20 00:12:11 +08:00
Sebastien Bourdeauducq 8f2d85fc5b add back ad9154_reg.py 2017-06-19 23:45:32 +08:00
Sebastien Bourdeauducq c86029bca2 i2c: expose restart as syscall, add structure for I2C-over-DRTIO 2017-06-19 23:44:51 +08:00
Sebastien Bourdeauducq 268b7d8aaf typo 2017-06-19 15:42:10 +08:00
Sebastien Bourdeauducq 09d198c7a1 test: add test for exception on non-existent I2C bus 2017-06-19 15:32:09 +08:00
Sebastien Bourdeauducq d08bd58dff versioneer: cut git hashes consistently (#753) 2017-06-19 15:31:48 +08:00
Sebastien Bourdeauducq 6c6bb67618 libboard: fix compiler warning on not(has_i2c) 2017-06-19 14:57:15 +08:00
Sebastien Bourdeauducq 5d63489080 i2c,spi: add busno error detection 2017-06-19 14:27:30 +08:00
Robert Jördens 0d8067256b rtio: refactor RelaxedAsyncResetSynchronizer 2017-06-18 14:37:08 +02:00
Sebastien Bourdeauducq 8399f8893d add kernel access to non-realtime SPI buses (#740) 2017-06-18 12:45:07 +08:00
Robert Jördens 424b2bfbd8 rtio: describe rio and rio_phy domains a bit more 2017-06-17 12:21:07 +02:00
Robert Jördens 219dfd8984 rtio: add one register level for rio and rio_phy resets 
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
 2017-06-17 12:17:48 +02:00
Sebastien Bourdeauducq 8fea361412 firmware: always use 8 characters to abbreviate git commit hashes 2017-06-17 14:43:50 +08:00
Robert Jördens e19bfd4781 test_sawg_fe: add ref_multiplier to simulated core 2017-06-16 19:45:24 +02:00
Robert Jördens b5772f478a sawg: add channel reset (closes #751) 2017-06-16 19:31:57 +02:00
Robert Jördens 2a76034fbc cri: add note about clearing of o_data 2017-06-16 19:06:00 +02:00
Robert Jördens fecc42fd0c sawg/phaser: expand documentation (closes #750) 2017-06-14 11:49:52 +02:00
Robert Jördens 858c1be381 sawg: expand documentation 2017-06-13 18:51:48 +02:00
Robert Jördens 3f37870e25 sawg: register pre-hbf adder 2017-06-13 18:15:44 +02:00
Robert Jördens e229edd5d5 sawg: add register after hbf for timing 2017-06-12 23:08:27 +02:00
Robert Jördens 315338fca9 test/sawg: test HBF overshoot, fix sim patching 2017-06-12 20:35:47 +02:00
Robert Jördens 9a8a7b9102 sawg: handle clipping interpolator 
* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC

This leaves a factor of two headroom for the sum of the following
effects:

  * HBF overshoot (~15 % of the step)
  * A1/A2 DDS sum

While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?

closes #743
 2017-06-12 20:33:54 +02:00
Robert Jördens 1fb3995ffc Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)" 
This reverts commit 6ac9d0c41e.

Overshooting behavior must to be handled outside the FIR.
 2017-06-12 20:07:25 +02:00
Robert Jördens 332bcc7f3b fir: check widths 2017-06-12 20:07:23 +02:00
Robert Jördens 39a1dcbb3d test/fir: look at overshoot behavior 2017-06-12 20:06:07 +02:00
Robert Jördens 6ac9d0c41e fir/ParallelHBFUpsampler: add headroom (gain=2) 
This addresses part of #743
 2017-06-12 18:59:45 +02:00
Robert Jördens 566ff73dff pdq: unify spi-PDQ and usb-PDQ protocols 2017-06-10 15:03:25 +02:00
Robert Jördens 6c54c0f834 sawg: update example 2017-06-10 11:52:48 +02:00
Robert Jördens d8aee931ba sawg: extend phase mode docs 2017-06-09 12:26:49 +02:00
whitequark f7254dd3ce compiler.validators.constness: take AugAssign into account. 2017-06-09 07:31:08 +00:00
whitequark ad2ee714c2 compiler: do not permit iterating str values. 
This currently breaks badly on UTF-8, and doesn't even return
a value of a correct type.
 2017-06-09 07:29:31 +00:00
whitequark 4e7493843a compiler: Constness is a validator, not analysis. 2017-06-09 07:29:31 +00:00