1bc7743e03
sayma: fix hmc7043 output settings for v2 hardware
2019-10-06 21:50:29 +08:00
a421820a32
sayma: initialize DACs over DRTIO
2019-10-06 21:42:45 +08:00
f62dc7e1d4
sayma: refactor JESD DAC channel groups
2019-10-06 20:15:09 +08:00
c4c884b8ce
ad9154: simplify, focus on AD9154 config and do not include JESD
2019-10-06 20:07:02 +08:00
ad63908aff
hmc830_7043: enable_fpga_ibuf -> unmute
2019-10-06 18:13:59 +08:00
5ad65b9d30
hmc830_7043: remove clock_mux
2019-10-06 18:13:27 +08:00
e9b81f6e33
remove serwb
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DRTIO is a better solution
2019-10-06 18:10:23 +08:00
71b3c66af9
firmware: conditionally compile has_si5324
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avoids unused warnings where this module is not used.
2019-08-29 09:04:54 +08:00
afe162ceca
firmware: don't unwrap() but propagate pca9548 errors
2019-08-17 09:15:26 +08:00
a8aabd3815
firwmare: turn i2c errors into &str
2019-08-17 09:15:26 +08:00
8fc5ce902f
firmware: let kasli obtain default hardware_addr from i2c_eeprom
2019-08-17 09:15:26 +08:00
d666f3d573
firmware: factor out mod pca9548 from si5324
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orepares for further i2c devices.
2019-08-17 09:15:26 +08:00
43e58c939c
sayma: drop MasterDAC
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This seemed like a good idea then, but it introduces complexity, corner cases, and additional testing difficulties.
Now Sayma works fine with Kasli as a master, which is simpler.
2019-06-14 14:06:16 +08:00
c7205ad82f
sayma_rtm: preliminary v2 support
2019-03-23 12:37:03 +08:00
ec230d6560
sayma: move SYSREF DDMTD to the RTM
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Put RTM Si5324 into bypass mode before running.
Needs rework to cut RTM Si5324 reset trace.
Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315.
Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic).
2019-01-31 20:39:33 +08:00
82106dcd95
si5324: add bypass function
2019-01-31 19:38:55 +08:00
8bbd4207d8
si5324: use consistent bitmask
2019-01-31 19:35:56 +08:00
d3c608aaec
jesd204sync: reset and check lock status of DDMTD helper PLL in firmware
2019-01-31 15:11:16 +08:00
fa3b40141d
hmc830_7043: document sayma clock muxes
2019-01-31 15:10:11 +08:00
ec8560911f
siphaser: bugfixes
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* Fix integer overflow in degree computation
* Add some phase slips after the first transition to get out of the jitter zone and avoid intermittent short windows
2019-01-30 16:56:38 +08:00
c591009220
sayma: report TSC phase of SYSREF (TSC LSBs on SYSREF rising edge) in SYSREF sampler
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Better visibility, better diagnostics, allows some changing of SYSREF frequency while keeping the same gateware.
2019-01-29 23:30:01 +08:00
9d0d02a561
jesd204sync: increase tolerance for coarse->final target in calibrate_sysref_target
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There is plenty of slack (it only needs to meet timing at the RTIO frequency).
2019-01-29 16:48:55 +08:00
ed6aa29897
jesd204sync: print more information on test_slip_ddmtd error
2019-01-29 16:47:29 +08:00
7a5d28b73d
jesd204sync: test SYSREF period
2019-01-28 19:11:38 +08:00
1a42e23fb4
jesd204sync: print DDMTD SYSREF final alignment delta
2019-01-28 18:39:16 +08:00
eebff6d77f
jesd204sync: fix max_phase_deviation
2019-01-28 18:38:18 +08:00
b9e3fab49c
jesd204sync: improve messaging
2019-01-28 18:37:46 +08:00
145f08f3fe
jesd204sync: update SYSREF S/H limit deviation tolerance
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Follows the increased DDMTD resolution.
2019-01-28 18:21:31 +08:00
ba21dc8498
jesd204sync: improve messaging
2019-01-28 18:08:20 +08:00
3acee87df2
firmware: improve DDMTD resolution using dithering/averaging
2019-01-28 16:04:04 +08:00
cfe66549ff
jesd204sync: cleanup DDMTD averaging code
2019-01-28 14:14:50 +08:00
2b0d63db23
hmc830_7043: support 125MHz RTIO
2019-01-28 13:44:08 +08:00
bdd4e52a53
ad9154: support 125MHz RTIO
2019-01-28 13:43:52 +08:00
3b6f47886e
firmware: print more info on DDMTD stability error
2019-01-27 23:06:11 +08:00
74fdd04622
firmware: test DDMTD stability
2019-01-27 20:39:12 +08:00
8254560577
sayma: properly determine SYSREF coarse calibration target
2019-01-27 16:00:36 +08:00
214394e3b0
sayma: reimplement DAC SYSREF autocalibration
2019-01-27 15:28:39 +08:00
fdbf1cc2b2
sayma: rework DAC SYSREF margin validation
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Previous code did not work when delay range was not enough for two rotations.
This removes autocalibration, to be done later. Uses hardcoded value for now.
2019-01-27 14:17:54 +08:00
7e5c062c2c
firmware: bypass channel divider for HMC7043 DCLK
2019-01-27 11:49:34 +08:00
f73ffe44f9
firmware: implement DDMTD-based SYSREF/RTIO alignment (draft)
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Mostly works and usually gets the DAC synchronized at 2.4GHz with Urukul across DRTIO.
Needs cleanup and optimization/characterization.
2019-01-27 09:51:24 +08:00
cb04230f86
sayma: SYSREF setup/hold validation demonstration
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This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
2019-01-25 16:58:58 +08:00
3356717316
sayma: DDMTD SYSREF measurement demonstration
2019-01-25 16:00:31 +08:00
4941fb3300
sayma: 2.4GHz DAC clocking (4X interpolation)
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* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
2019-01-25 13:47:04 +08:00
cc9420d2c8
hmc7043: fix divider programming
2019-01-25 11:48:50 +08:00
bbac92442f
sayma: check hmc7043 slip period
2019-01-24 20:13:43 +08:00
f8b39b0b9a
sayma: enable 2X DAC interpolation
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Seems to work just fine and gets one clock divider out of the way.
2019-01-24 18:28:01 +08:00
2e3555de85
firmware: fix compilation error with more than 1 Grabber
2019-01-22 19:35:46 +08:00
62599c5f91
firmware: use consistent terminology
2019-01-09 13:46:18 +08:00
887cb110a7
firmware: fix default DRTIO routing table
2019-01-08 20:46:53 +08:00
b5501aaf00
firmware: program I2C switch on Sayma RTM
2019-01-06 14:54:52 +08:00
a93fdb8c9d
drtio: disable all destinations in gateware at startup
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Otherwise, kernels fail to get a RTIODestinationUnreachable exception when attempting
to reach a DRTIO destination that has never been up.
2019-01-04 23:42:12 +08:00
cc58318500
siphaser: autocalibrate skew using RX synchronizer
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* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
2019-01-02 22:29:27 +08:00
969a305c5a
Merge branch 'master' into switching125
2018-10-04 10:08:42 +08:00
3d965910f7
Revert "drtio: implement per-destination underflow margins"
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This reverts commit 142c952e3d
2018-09-19 17:05:48 +08:00
142c952e3d
drtio: implement per-destination underflow margins
2018-09-19 17:03:15 +08:00
f7ad7a99e3
firmware: set DEST_COUNT to 0 without routing
2018-09-15 19:10:52 +08:00
d38755feff
drtio: implement destination state checks on operations
2018-09-15 15:55:45 +08:00
65da1fee4a
firmware: fix build without DRTIO
2018-09-14 20:38:41 +08:00
d19550daf8
firmware: simplify drtioaux function names
2018-09-14 20:32:09 +08:00
ae72e3a51e
firmware: add support for moninj and kern_hwreq over DRTIO switching
2018-09-14 20:26:39 +08:00
fa872c3341
firmware: implement DRTIO destination survey
2018-09-13 12:00:29 +08:00
420e1cb1d0
cri: fix firmware routing table access
2018-09-12 18:08:16 +08:00
36e3fedfc6
runtime: print routing table at boot
2018-09-11 20:10:33 +08:00
f5b386c0d8
firmware: fix routing table formatting
2018-09-11 18:22:45 +08:00
b38c57d73b
firmware: send DRTIO routing table to satellite
2018-09-11 14:12:41 +08:00
3d29a7ed14
firmware: add fmt::Display to RoutingTable
2018-09-11 11:27:56 +08:00
31bef9918e
firmware: fix drtio_routing compatibility with master and satellite
2018-09-10 20:16:42 +08:00
7ae44f3417
firmware: add routing table (WIP)
2018-09-09 21:49:28 +08:00
312256a18d
grabber: fix frame size off-by-1
2018-09-07 16:55:43 +02:00
87e0384e97
drtio: separate aux controller
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This helps with managing CSR groups and heterogeneous (satellite/repeaters) DRTIO cores.
2018-09-05 17:56:58 +08:00
d1d26e2aa3
hmc7043: add explanation about HMC_SYSREF_DIV
2018-08-18 11:43:40 +08:00
f75a317446
hmc7043: automatically determine output groups
2018-08-18 11:43:23 +08:00
c498b28f88
hmc7043: disable FPGA_ADC_SYSREF
2018-08-18 11:42:57 +08:00
167e97efd2
sayma: support external RTM clocking
2018-08-17 22:57:54 +08:00
5c3e834c4d
ad9154: retry DAC initialization on STPL or PRBS failure
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Works around #1127
2018-08-17 20:52:55 +08:00
738d2c6bcb
hmc7043: REFSYNCIN → RFSYNCIN
2018-08-11 12:07:17 +08:00
f7678cc24a
grabber: refactor state machine
2018-08-07 18:07:46 +02:00
6cd2432e30
grabber: log all resolution changes
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close #1120
2018-08-07 16:21:21 +02:00
99a15ca0c6
grabber: rationalize derived traits
2018-08-07 16:21:21 +02:00
49f7a1610f
sayma: use GTP_CLK1 only for all variants ( #1080 )
2018-08-07 20:53:14 +08:00
bbe36b94f7
ad9154: enable sync in init
2018-08-06 19:02:27 +08:00
7f0b2ff594
jesd204sync: work around HMC7043 poor behavior with combined delays
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The HMC7043 outputs poorly controlled signals when adjusting
two delays at once. This commit puts the DAC in one-shot SYSREF mode,
and only triggers synchronizations when SYSREF is stable.
2018-08-06 17:43:17 +08:00
f32f0126e2
Revert "ad9154: use continuous sync mode"
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The HMC7043 is not really glitchless.
This reverts commit bd968211de
2018-08-06 16:59:53 +08:00
bd968211de
ad9154: use continuous sync mode
2018-08-06 00:27:10 +08:00
e83ee3a07a
hmc7043: disable GTP_CLK1 when not in use
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Termination and biasing are not active at the FPGA when IBUFDS_GTE3 is
not instantiated, and driving a clock then leads to overvoltage.
2018-08-03 10:03:52 +08:00
446f791180
firmware: simplify SYSREF DRTIO alignment
2018-07-26 19:37:59 +08:00
32c95ac034
sayma: automated DAC SYSREF phase calibration
2018-07-26 16:23:55 +08:00
dbcf2fe9b4
firmware: remove 'chip found' messages on Sayma
2018-07-26 16:07:37 +08:00
d523d03f71
sayma: automated FPGA SYSREF phase offset calibration
2018-07-26 14:53:28 +08:00
19c51c644e
grabber: cleanup GRABBER_STATE
2018-07-24 19:08:51 +08:00
b27fa8964b
add variant in identifier string
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Also add without-sawg suffixes on Sayma.
Closes #1060
Closes #1059
2018-07-15 17:21:17 +08:00
46fb5adac3
grabber: fix frequency counter formula
2018-07-12 20:14:38 +08:00
82def6b535
grabber: add frequency counter
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Cameras are a bit obscure about what they output, this can help with troubleshooting.
2018-07-12 17:05:18 +08:00
29c35ee553
hmc7043: fix dumb mistake in previous commit
2018-07-12 13:01:41 +08:00
8802b930de
hmc7043: add delay after init
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Delay required at step 9 of the "Typical Programming Sequence" (page 24 of the datasheet)
2018-07-12 12:37:12 +08:00
c66f9483f8
hmc7043: wait after changing delays
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Allows for the SPI transaction to finish, and for the delay to stabilize.
2018-07-12 12:33:53 +08:00
773240bef4
hmc7043: test GPO before using
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Based on code by David.
2018-07-12 11:30:24 +08:00
4843832329
hmc7043: check phase status on init. Closes #1055
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Troubleshooting by David.
2018-07-11 19:45:24 +08:00
9397fa7f5a
hmc7043: unstick SYSREF FSM ( #1055 )
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Troubleshooting by David.
Additionally, register 7D is broken.
Checking phase init state has to be done through another means.
2018-07-11 19:11:01 +08:00
4f56710e4b
grabber: add parser, report detected frame size in core device log
2018-07-10 02:06:37 +08:00
