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a159ef642d
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drtio: demote default routing table message to info
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2022-03-16 21:22:35 +08:00 |
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a85b4d5f5e
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I2C API for PCA9547 support (#1860)
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2022-03-01 15:07:53 +08:00 |
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9423428bb0
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drtio: fix crc32 offset address
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2021-11-24 12:00:56 +08:00 |
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03b803e764
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firmware: adjust csr separation
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2021-11-08 16:59:08 +08:00 |
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eecd825d23
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firmware: suppress warning
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2021-09-10 13:25:12 +08:00 |
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1da0554a49
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pcr: purge
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2021-09-10 13:25:12 +08:00 |
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7542105f0f
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board_misoc: remove pcr
VexRiscv seems to not support additional hardware performance counter, at least I have not seen any documentation on how to use it.
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2021-09-10 13:25:12 +08:00 |
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92fd705990
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increase memory allocated to comms CPU
See discussion in #1612.
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2021-02-21 19:06:12 +08:00 |
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ea95d91428
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wrpll: separate collector reset
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2020-11-09 17:57:13 +08:00 |
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hartytp
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e6ff2ddc32
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wrpll: add more diagnostics in firmware and adapt to recent gateware changes
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2020-10-08 15:32:27 +08:00 |
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4e9a529e5a
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kasli: integrate WRPLL
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2020-05-07 21:34:02 +08:00 |
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ffd3172e02
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sayma: move SYSREF DDMTD to RTM (#795)
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2020-04-06 00:01:28 +08:00 |
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52ec849008
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sayma: fix sysref_delay_dac
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2020-02-05 19:04:01 +08:00 |
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bf9f4e380a
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si5324: program I2C mux on Metlino
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2020-02-03 18:07:59 +08:00 |
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ec03767dcf
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sayma: improve DAC status report
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2020-01-20 18:22:06 +08:00 |
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3242e9ec6c
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wrpll: loop test
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2020-01-13 22:31:57 +08:00 |
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d5895b8999
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wrpll: adpll -> set_adpll
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2020-01-13 20:46:36 +08:00 |
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e7ef23d30c
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wrpll: use CONFIG_CLOCK_FREQUENCY and rtio_frequency in trim_dcxos
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2020-01-13 20:44:15 +08:00 |
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ea3bce6fe3
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wrpll: wait for settling time after setting ADPLL
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2020-01-13 20:43:34 +08:00 |
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e87d864063
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wrpll: print ADPLL offsets
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2020-01-13 19:32:30 +08:00 |
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8edbc33d0e
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wrpll: calculate initial ADPLL offsets
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2020-01-13 19:29:10 +08:00 |
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3f32d78c0e
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wrpll: simple ADPLL test
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2019-12-31 12:12:29 +08:00 |
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bb04b082a7
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wrpll: clarify comment
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2019-12-31 12:12:29 +08:00 |
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642a305c6a
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wrpll: remove unnecessary delay
Counting now happens in the sys domain with no CDC between counter and CPU.
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2019-12-30 20:01:06 +08:00 |
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f57f235dca
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wrpll: new frequency meter
As per Mattermost discussion with Tom.
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2019-12-30 19:47:57 +08:00 |
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c5137eeb62
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firmware: remove legacy hmc542 code
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2019-12-20 15:25:55 +08:00 |
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6f52540569
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wrpll: fix previous commit
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2019-12-09 20:13:55 +08:00 |
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13486f3acf
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wrpll: swap helper/main si549 frequencies
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2019-12-09 19:49:34 +08:00 |
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4919fb8765
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wrpll: print DDMTD helper tags
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2019-12-09 17:39:22 +08:00 |
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0d4eccc1a5
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wrpll: improve debug output
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2019-12-09 17:23:09 +08:00 |
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f633c62e8d
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wrpll: speed up si549 i2c access
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2019-12-09 17:22:58 +08:00 |
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14e09582b6
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wrpll: work around si549 not working when lsdiv=2
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2019-12-09 16:20:08 +08:00 |
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439576f59d
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wrpll: fix Si549 initialization delays
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2019-12-09 16:13:57 +08:00 |
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0499f83580
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wrpll: helper clock sanity check
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2019-12-08 23:46:33 +08:00 |
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Paweł Kulik
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14e250c78f
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Enabled internal pullup for CML SYSREF outputs, otherwise there is no signal on them.
Signed-off-by: Paweł Kulik <pawel.kulik@creotech.pl>
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2019-12-07 09:30:24 +08:00 |
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eb271f383b
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wrpll: add DDMTD cores
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2019-11-28 22:03:50 +08:00 |
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39d5ca11f4
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si549: increase I2C frequency
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2019-11-28 22:03:26 +08:00 |
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87894102e5
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si549: use recommended i2c read sequence
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2019-11-28 17:49:02 +08:00 |
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354d82cfe3
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wrpll: drive helper clock domain
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2019-11-28 17:40:00 +08:00 |
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68cab5be8c
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si549: cleanups
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2019-11-28 16:36:59 +08:00 |
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bcd2383c9d
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wrpll: si549 initialization
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2019-11-27 22:58:08 +08:00 |
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4832bfb08c
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wrpll: i2c functions, select_recovered_clock placeholder
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2019-11-27 21:21:00 +08:00 |
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a78e493b72
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firmware: load slave FPGA in bootloader
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2019-10-31 12:42:40 +08:00 |
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389a8f587a
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slave_fpga: modularize
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2019-10-31 11:50:53 +08:00 |
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f2f7170d20
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hmc7043: use recommend I/O standards
https://github.com/sinara-hw/Sayma_RTM/issues/116#issuecomment-544187952
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2019-10-21 22:56:10 +08:00 |
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8f76a3218e
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firmware: move i2c to libboard_misoc, enable IPv6 in bootloader, share network settings
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2019-10-21 12:58:52 +08:00 |
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05e8f24c24
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sayma2: JESD204 synchronization
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2019-10-18 23:28:47 +08:00 |
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4df2c5d1fb
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sayma: prepare for SYSREF align
We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
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2019-10-08 12:30:47 +08:00 |
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4b3baf4825
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firmware: run PRBS and STPL JESD204 tests
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2019-10-08 00:10:36 +08:00 |
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90e3b83e80
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hmc7043: turn on AMC_FPGA_SYSREF1
Florent's JESD core won't work at all without.
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2019-10-06 22:49:00 +08:00 |
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