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979 Commits

Author SHA1 Message Date
Robert Jördens b0282fa855 spi2: reset configuration in rio_phy 2018-03-07 14:42:11 +00:00
Robert Jördens 4af7600b2d Revert "LaneDistributor: try equivalent spread logic" 
This reverts commit 8b70db5f17.

Just a shot into the dark.
 2018-03-07 11:34:51 +00:00
Robert Jördens a6d1b030c1 RTIO: use TS counter in the correct CD 
artiq/m-labs#938
 2018-03-07 11:34:42 +00:00
Robert Jördens 8b70db5f17 LaneDistributor: try equivalent spread logic 2018-03-07 11:34:42 +00:00
Robert Jördens 2cbd597416 LaneDistributor: style and signal consolidation [NFC] 2018-03-07 11:34:42 +00:00
Sebastien Bourdeauducq 916197c4d7 siphaser: cleanup 2018-03-07 11:15:44 +08:00
Sebastien Bourdeauducq f7aba6b570 siphaser: fix phase_shift_done CSR 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq acfd9db185 siphaser: minor cleanup 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq 7d98864b31 sayma: enable siphaser 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq a6e29462a8 sayma: enable multilink DRTIO 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq c34d00cbc9 drtio: implement Si5324 phaser gateware and partial firmware support 2018-03-07 10:57:30 +08:00
Robert Jördens 994ceca9ff sayma_amc: disable slave fpga gateware loading 2018-03-06 17:27:43 +01:00
Robert Jördens 62af7fe2ac Revert "kasli/opticlock: use plain ttls for channels 8-23" 
This reverts commit bd5c222569eb68d624a5ac1e9f2542f6ee553f83.

No decrease in power consumption or improvement in timing.
 2018-03-06 14:27:19 +01:00
Robert Jördens fd3cdce59a kasli/opticlock: use plain ttls for channels 8-23 2018-03-06 14:27:19 +01:00
Robert Jördens 50298a6104 ttl_serdes_7series: suppress diff_term in outputs 2018-03-06 14:27:19 +01:00
Robert Jördens e356150ac4 ttl_simple: support differential io 2018-03-06 14:27:19 +01:00
Robert Jördens 956098c213 kasli: add second urukul, make clk_sel drive optional 2018-03-06 14:26:27 +01:00
Robert Jördens 07de7af86a kasli: make second eem optional in urukul 2018-03-06 14:26:26 +01:00
Sebastien Bourdeauducq c25560baec sed: more LaneDistributor comments 2018-03-06 20:56:35 +08:00
Sebastien Bourdeauducq f40255c968 sed: add comments about key points in LaneDistributor 2018-03-06 20:51:09 +08:00
Florent Kermarrec 5b3d6d57e2 drtio/gth: power down rx on restart (seems to make link initialization reliable) 2018-03-06 11:49:28 +01:00
Florent Kermarrec 64b05f07bb drtio/gth: use parameters from Xilinx transceiver wizard 2018-03-06 11:02:15 +01:00
Florent Kermarrec 45f1e5a70e drtio/gth: cleanup import 2018-03-06 10:56:07 +01:00
Sebastien Bourdeauducq 6aaa8bf9d9 drtio: fix link error generation 2018-03-04 23:20:13 +08:00
Sebastien Bourdeauducq d747d74cb3 test: fix test_dma 2018-03-04 23:19:06 +08:00
Sebastien Bourdeauducq 928d5dc9b3 drtio: raise RTIOLinkError if operation fails due to link lost (#942) 2018-03-04 01:02:53 +08:00
Robert Jördens ddcc68cff9 sayma_amc: move bitstream options to migen 
close #930
 2018-03-02 18:13:03 +08:00
Sebastien Bourdeauducq a9daaad77b kasli: add SYSU variant and device_db 2018-03-02 14:44:31 +08:00
Robert Jördens cc70578f1f remove old spi RTIO Phy 2018-03-01 11:19:18 +01:00
Robert Jördens ec5b81da55 kc705: switch backplane spi to spi2 2018-03-01 11:19:18 +01:00
Robert Jördens a7720d05cd firmware, sayma: port converter_spi to spi2 
* ksupport/nrt_bus
* port ad9154, hmc830, hmc7043
* port local_spi and drtio_spi
* port kernel_proto libdrtioaux, satman
* change sayma_rtm gateware over
* add spi2 NRTSPIMaster
* remove spi NRTSPIMaster
* change sayma device_db
* change HMC830 to open mode and explicitly sequence open mode
 2018-03-01 11:19:18 +01:00
Robert Jördens 54984f080b artiq_flash: flash RTM firmware 
based on whitequark's work in f95fb27

m-labs/artiq#813
 2018-02-28 19:29:01 +01:00
Robert Jördens 1f999c7f5f sayma_amc: expose RTM fpga load pins as GPIOs 2018-02-28 18:44:36 +01:00
Florent Kermarrec 2896dc619b drtio/transceiver/gth: fix multilane 2018-02-28 14:15:40 +01:00
Sebastien Bourdeauducq 386aa75aaa kasli: control SFP1 and SFP2 LEDs in DRTIO satellite to match master 2018-02-27 23:18:18 +08:00
Sebastien Bourdeauducq 5d81877b34 kasli: implement multi-link DRTIO on SFP1 and SFP2 of master 2018-02-27 23:15:20 +08:00
Florent Kermarrec 1f0d955ce4 drtio/transceiver/gtp: implement tx multi lane phase alignment sequence 2018-02-27 12:32:25 +01:00
Sebastien Bourdeauducq e565d3fa59 kasli: add analyzer and RTIO log to DRTIO master target 2018-02-27 18:09:07 +08:00
Florent Kermarrec 5b0f9cc6fd drtio/transceiver/gth: fix single transceiver case 2018-02-23 12:15:47 +01:00
Florent Kermarrec b4ba71c7a4 drtio/transceiver/gth: implement tx multi lane phase alignment sequence (fix merge issue...) 2018-02-23 08:37:05 +01:00
Florent Kermarrec 820c834251 drtio/transceiver/gth: implement tx multi lane phase alignment sequence 2018-02-22 22:14:15 +01:00
Robert Jördens 1452cd7447 novogorny: add coredevice driver and test with Kasli 
m-labs/artiq#687
 2018-02-22 17:19:51 +01:00
Robert Jördens 3b7971d15d kasli: spelling 2018-02-22 17:19:51 +01:00
Robert Jördens 771bf87b56 kc705: port amc101_dac/spi0 and sma_spi to spi2 2018-02-22 17:19:51 +01:00
Robert Jördens f8e6b4f4e3 ad5360: port to spi2 
* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db

This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1

m-labs/artiq#926
 2018-02-22 10:25:46 +01:00
Sebastien Bourdeauducq fa0d929b4d drtio: reorganize RX synchronizers 2018-02-22 15:21:23 +08:00
Sebastien Bourdeauducq e5de5ef473 kasli: use deterministic RX synchronizer 
Could not reproduce the "fully broken bitstream" bug.
 2018-02-22 15:18:09 +08:00
Robert Jördens a5ad1dc266 kc705: fix sdcard miso pullup 2018-02-21 19:41:05 +01:00
Robert Jördens 0d8145084d test_spi: move to new spi2 core 2018-02-21 19:41:05 +01:00
Robert Jördens a63fd306af urukul: use spi2 
* switch kc705 and kasli targets to spi2 gateware on urukul
* rewrite urukul, ad9912, ad9910
* update example experiments, device_dbs
 2018-02-21 15:00:28 +00:00
Robert Jördens 37a0d6580b spi2: add RTIO gateware and coredevice driver 
1006218997
 2018-02-21 13:37:36 +00:00
Robert Jördens 91a4a7b0ee kasli: free run si5324 on opticlock for now 2018-02-21 13:37:29 +00:00
Robert Jördens 7a1d71502a ttl_serdes_7series: drive IBUF and INTERM disables from serdes 2018-02-21 13:37:29 +00:00
Robert Jördens 476e4fdd56 ttl_serdes_7series: disable IBUF and INTERM when output 2018-02-21 13:37:29 +00:00
Sebastien Bourdeauducq f060d6e1b3 drtio: increase A7 clock aligner check period 2018-02-20 18:50:35 +08:00
Sebastien Bourdeauducq f15b4bdde7 style 2018-02-20 18:47:59 +08:00
Sebastien Bourdeauducq 7d9c7ada71 drtio: fix test infinite loop 2018-02-20 17:42:00 +08:00
Sebastien Bourdeauducq ad2c9590d0 drtio: rewrite/fix reset and link bringup/teardown 2018-02-20 17:26:43 +08:00
Robert Jördens 7e02d8245c kasli: false paths 
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
  ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
 2018-02-19 13:05:11 +00:00
Sebastien Bourdeauducq 0f4549655b sayma: use Xilinx RX synchronizer 
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
 2018-02-19 17:49:53 +08:00
Sebastien Bourdeauducq 52049cf36a drtio: add Xilinx RX synchronizer 2018-02-19 17:49:43 +08:00
Sebastien Bourdeauducq 3bc575bee7 drtio: add missing define for Sayma master 2018-02-19 17:11:21 +08:00
Sebastien Bourdeauducq 7376ab0ff8 drtio: fix Sayma after 83abdd28 2018-02-19 17:10:55 +08:00
Florent Kermarrec f5831af535 drtio/transceiver/gtp_7series_init: don't reset gtp rx on power down 2018-02-19 10:03:19 +01:00
Florent Kermarrec 89a158c0c9 drtio/transceiver/gtp_7series_init: remove dead code 2018-02-19 10:02:23 +01:00
Florent Kermarrec 782051f474 drtio/transceiver/gtp_7series_init: add no retiming on gtp resets 2018-02-19 09:59:50 +01:00
Sebastien Bourdeauducq c329c83676 kasli: fix disable_si5324_ibuf no_retiming 2018-02-19 12:19:05 +08:00
Sebastien Bourdeauducq a93decdef2 kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized 2018-02-19 00:48:37 +08:00
Sebastien Bourdeauducq 94c20dfd4d drtio: fix misleading GenericRXSynchronizer comment 2018-02-19 00:47:54 +08:00
Sebastien Bourdeauducq 83abdd283a drtio: signal stable clock input to transceiver 2018-02-18 22:29:30 +08:00
Sebastien Bourdeauducq 287d533437 Revert "sayma_amc: remove RTM bitstream upload core. Closes #908" 
This reverts commit 2d4a1340ea.
 2018-02-17 17:38:48 +08:00
Sebastien Bourdeauducq 73985a9215 sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed) 2018-02-17 17:38:17 +08:00
Sebastien Bourdeauducq 039dee4c8e si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER 
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
 2018-02-17 13:54:50 +08:00
Sebastien Bourdeauducq cfb21ca126 si5324: fix usage of external CLKIN2 reference 2018-02-17 13:52:01 +08:00
Robert Jördens e41f49cc75 kasli: opticlock 125 MHz, mark external reference case broken 2018-02-16 17:23:15 +00:00
Sebastien Bourdeauducq 4d42df2a7c kasli: set up Si5324 in standalone operation 2018-02-15 20:32:58 +08:00
Sebastien Bourdeauducq d7387611c0 sayma: print RTM gateware version 2018-02-15 19:31:58 +08:00
Robert Jördens be693bc8a9 opticlock: examples 2018-02-13 22:13:40 +01:00
Robert Jördens a3d136d30d opticlock: wire urukul and novogorny 2018-02-13 22:13:40 +01:00
Sebastien Bourdeauducq ab5f397fea sed/fifos: use AsyncFIFOBuffered 
(D)RTIO now passes timing at 150MHz on Kasli.
 2018-02-13 20:02:51 +08:00
Sebastien Bourdeauducq 00f42f912b rename 'RTM identifier' to 'RTM magic number' 
Avoids confusion with the MiSoC identifier (containing the ARTIQ version).
 2018-02-13 20:02:51 +08:00
Sebastien Bourdeauducq 96b948f57f remote_csr: add sanity check of CSR CSV type column 2018-02-13 20:02:51 +08:00
Florent Kermarrec bfdda340fd drtio/transceiver/gtp_7series: use parameters from xilinx wizard 2018-02-13 00:23:59 +01:00
Florent Kermarrec 180c28551d drtio/gateware/transceiver/gtp_7series: add power down state before reset on rx (seems to make restart reliable) 2018-02-09 20:17:02 +01:00
Sebastien Bourdeauducq 2d4a1340ea sayma_amc: remove RTM bitstream upload core. Closes #908 2018-02-07 12:27:35 +08:00
whitequark 61c64a76be gateware: use a per-variant subfolder in --output-dir. (fixes #912) 
This commit also adds support for --variant and --args
to artiq-devtool.
 2018-02-06 08:19:01 +00:00
whitequark 885ab40946 conda: split RTM and AMC packages back. 
This avoids multiplying the RTM compilation time by the number
of AMC packages.
 2018-01-28 14:27:55 +00:00
whitequark 11a8b84355 Merge the build trees of sayma_amc and sayma_rtm targets. 
This also makes them a single artiq_flash target, and a single
conda package.
 2018-01-27 19:54:31 +00:00
Sebastien Bourdeauducq 440e19b8f9 kasli: use SFP2 for DRTIO mastering 
SFP1 PCB routing has some issues.

Also use SFP1 LED for DRTIO in both master and satellite.
 2018-01-26 19:02:54 +08:00
Robert Jördens e0e795f11c sayma_amc: constrain pin, remove keep 2018-01-23 15:42:47 +00:00
Robert Jördens b5c035bb52 sayma_rtm: constrain serwb clock input 2018-01-23 13:54:53 +00:00
Robert Jördens aada38f508 kasli, kc705: remove vivado "keep", cleanup a constraint 2018-01-23 13:15:26 +00:00
Robert Jördens 85102e191e sayma_rtm: derive clocks automatically 
* also don't add false paths unless necessary
 2018-01-23 11:00:55 +00:00
Robert Jördens 7d1b3f37c9 sayma_rtm: set CFGBVS/CONFIG_VOLTAGE, compress 2018-01-23 10:56:42 +00:00
Sebastien Bourdeauducq 649deccd9b kasli: fix DRTIO satellite QPLL refclksel 2018-01-23 12:27:19 +08:00
Sebastien Bourdeauducq 4b4374f76a sayma: register_jref for JESD204. Closes #904 2018-01-23 12:19:15 +08:00
Sebastien Bourdeauducq 763aefacff kasli: fix typo 2018-01-23 12:10:54 +08:00
Sebastien Bourdeauducq c7b148a704 kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1 2018-01-23 12:08:10 +08:00
Sebastien Bourdeauducq d6157514c7 gtp_7series: flexible QPLL channel selection 2018-01-23 12:03:09 +08:00
Sebastien Bourdeauducq 9f87c34a94 kasli: fix QPLL instantiation 2018-01-23 10:39:31 +08:00
Sebastien Bourdeauducq 98a5607634 gtp_7series: set clock muxes correctly for second QPLL channel 2018-01-23 10:39:20 +08:00
Sebastien Bourdeauducq 25fee1a0bb gtp_7series: use QPLL second channel 2018-01-23 10:15:49 +08:00
Sebastien Bourdeauducq 031d7ff020 kasli: keep using second QPLL channel for DRTIO satellite 2018-01-23 10:13:10 +08:00
Sebastien Bourdeauducq 626075cbc1 gtp_7series: simplify TX clocking 2018-01-23 09:49:23 +08:00
Sebastien Bourdeauducq 401e57d41c gtp_7series: fix nchannels assert 2018-01-23 01:28:01 +08:00
Sebastien Bourdeauducq aa62e91487 kasli: add DRTIO targets (no firmware) 2018-01-23 01:27:40 +08:00
Sebastien Bourdeauducq 296ac35f5d sayma_amc: SFP TX disable is active-high 2018-01-23 00:32:09 +08:00
Sebastien Bourdeauducq 77192256ea kc705: style 2018-01-23 00:02:35 +08:00
Sebastien Bourdeauducq ab7c49d6d0 sayma_amc: raise error on invalid variant 2018-01-23 00:02:16 +08:00
Sebastien Bourdeauducq c1ac3b66b1 sayma_rtm: fix 8fe463d4a 2018-01-23 00:01:45 +08:00
Sebastien Bourdeauducq 53facfef13 sayma: build fixes 2018-01-22 18:33:22 +08:00
Sebastien Bourdeauducq 25f3feeda8 refactor targets 2018-01-22 18:25:10 +08:00
Sebastien Bourdeauducq 5198c224a2 sayma,kasli: use new pin names 2018-01-22 11:51:07 +08:00
Florent Kermarrec 8fe463d4a0 sayma_rtm: add UART loopback to easily know if rtm fpga is alive 2018-01-20 06:04:34 +01:00
Florent Kermarrec 74ce7319d3 sayma: reduce serwb linerate to 625Mbps (make it work on saymas with 1.8v issue, related?) 2018-01-20 06:04:18 +01:00
Florent Kermarrec d27727968c add artix7 gtp (3gbps), share clock aligner with gth_ultrascale 2018-01-19 12:17:54 +01:00
Sebastien Bourdeauducq cdbf95d46a kasli: fix permissions 2018-01-19 18:31:20 +08:00
Robert Jördens 8ec33ae7bd kasli: feed EEM clock fan-out from SI5324 2018-01-17 17:27:59 +01:00
Robert Jördens ed3e3b2791 sayma_amc: clarify --with-sawg help 2018-01-17 12:10:30 +01:00
Florent Kermarrec f54b27b79c sayma_amc: prepare for jesd subclass 1 2018-01-17 11:49:36 +01:00
Florent Kermarrec f73c3e5944 gateware/test/serwb: update and cleanup test (v2...) 2018-01-16 20:06:43 +01:00
Robert Jördens 7405006668 sayma: rtio clock is jesd fabric clock 2018-01-16 18:19:04 +01:00
whitequark 247167d34a Revert "gateware/test/serwb: update and cleanup tests" 
This reverts commit 5b03cc2fae.
 2018-01-16 08:21:26 +00:00
whitequark 444b901dbe sayma: add RTM configuration port. 2018-01-16 07:28:00 +00:00
Florent Kermarrec 5b03cc2fae gateware/test/serwb: update and cleanup tests 2018-01-15 21:53:40 +01:00
whitequark 6891141fa6 artiq_flash: add sayma support. 2018-01-15 11:43:29 +00:00
Robert Jördens 529033e016 kernel_cpu: disable PCU 
* contributes to long timing paths on artix 7 (kasli)
* currently only used for testing and debugging
 2018-01-12 12:03:50 +00:00
Robert Jördens ac3c3871d0 kasli: s/extensions/variant/g 2018-01-12 12:29:42 +01:00
Sebastien Bourdeauducq 7c82fcf41a targets: avoid passing cpu_type around unnecessarily 2018-01-11 11:21:55 +08:00
Sebastien Bourdeauducq 6d58c4390b Merge branch 'sed-merge' 2018-01-10 13:14:39 +08:00
Sebastien Bourdeauducq 04b2fd3e13 sayma: fix AD9154NoSAWG ramp clock domain 2018-01-10 12:11:33 +08:00
Sebastien Bourdeauducq dc593ec0f0 Merge branch 'rtio-sed' into sed-merge 2018-01-10 12:04:54 +08:00
Florent Kermarrec 2009734b3c serwb/phy: get 625Mbps linerate working, increase timeout 2018-01-09 18:54:52 +01:00
Florent Kermarrec 9c6a7f7509 serwb/kusphy: use same serwb_serdes_5x reset than s7phy 2018-01-09 18:54:05 +01:00
Robert Jördens 8813aee6b1 targets: add kasli [wip, untested] 2018-01-04 16:12:12 +01:00
Florent Kermarrec 1e972034e8 gateware/targets: enable serwb scrambling on sayma amc & rtm 2018-01-03 17:34:46 +01:00
Florent Kermarrec 907af25a69 gateware/serwb: add scrambling, reduce cdc fifo depth 2018-01-03 17:34:03 +01:00
Florent Kermarrec 7f4756a869 gateware/serwb: cleanup packet 2018-01-03 17:30:12 +01:00
Robert Jördens c2be820e9a kc705_dds: make ext_clkout 100 MHz 2018-01-02 19:58:47 +01:00
Robert Jördens 43686f324b kc705_dds: fix HPC voltages 
* VADJ is 3.3 V due to the DDS card on LPC
* the LVDS standards need to be 2.5 V

* the direction control register on HPC (FMC-DIO to VHDCI)
  was LVCMOS33 but while all the LVDS pairs are at VCCIO=VADJ=3.3 V
  they were instantiated as LVDS_25 (ignoring the wrongly powered bank)
* we now use 2.5 V standards on HPC consistently despite VADJ=3.3 V
  and hope for the best.
 2018-01-02 13:41:07 +01:00
Robert Jördens 94b84ebe7c kc705_dds: add urukul spi/ttl channels 2018-01-02 13:20:48 +01:00
Robert Jördens 53969d3686 kc705_dds: add urukul on vhdci extension definition 2018-01-02 13:20:47 +01:00
Robert Jördens 2f8e6c7462 spi: add diff_term, save power on outputs 2018-01-02 13:20:47 +01:00
Robert Jördens 6d20b71dde ttl_serdes_7series: refactor IOSERDES 2018-01-02 13:20:47 +01:00
Robert Jördens 745e695b09 sayma: output a ramp in the absence of SAWG channels 2017-12-31 12:18:53 +01:00
whitequark a371b25525 bootloader: allow using without Ethernet. 2017-12-31 09:21:28 +00:00
Sebastien Bourdeauducq 6e0288e568 drtio: fix GTH CPLL reset 2017-12-30 12:14:36 +08:00
Robert Jördens 379d29561b sayma: plausibility assertion on sawg data stream 2017-12-29 19:15:40 +01:00
Robert Jördens 37f9c0b10c spi: register clk 
following m-labs/misoc#65
1dc68b0d0b
 2017-12-28 16:50:22 +01:00
whitequark acd13837ff firmware: implement the new bootloader. 2017-12-28 13:18:51 +00:00