668450db26
sayma_amc: add serwb
2017-08-21 18:11:29 -04:00
0459a70cf6
sayma_amc: cleanup, fix RTM UART forwarding
2017-08-21 16:49:42 -04:00
1f2b373d09
sayma_rtm: remove unnecessary serwb_control
2017-08-21 16:37:13 -04:00
bfea297279
targets: add Sayma RTM
2017-08-21 15:58:01 -04:00
53c7f92fdc
serwb: add __init__.py and expose submodules
2017-08-21 15:57:43 -04:00
dac3a78b75
serwb: style, use migen, fix imports
2017-08-21 12:35:59 -04:00
Florent Kermarrec
da90a0fa12
Add test for Etherbone
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Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ec62242659910ad1726beb00ff15b3f0a406615
2017-08-21 12:31:49 -04:00
Florent Kermarrec
44dc76e42e
Add serial Wishbone bridge
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Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ce2cba87896d056819dc2edc54f0453a86162c3
2017-08-21 12:22:05 -04:00
d6b624dfbe
sayma_amc: connect RTM serial and second serial
2017-08-20 19:01:55 -04:00
bee4902323
add Sayma AMC standalone target
2017-08-20 11:47:45 -04:00
1dab7df846
kc705_sma_spi: fix permissions
2017-08-20 10:54:24 -04:00
df4f38a1e4
kc705: add pullup on SD card MISO
2017-07-24 22:26:16 +08:00
a201a9abd9
drtio: multilink transceiver interface
2017-07-18 13:27:33 +08:00
9045b4cc19
drtio: initial firmware support for multi-link
2017-07-18 00:40:21 +08:00
4deb5f6a45
gateware: use new MiSoC Wishbone address system
2017-07-13 19:16:49 +08:00
mntng
40ca951750
kc705: add SPI bus for memory card
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This will be useful for SPI unit tests using a SD card as victim.
2017-07-12 00:27:44 +08:00
7b130a2c32
sawg: confirm smooth(order=3)
2017-07-07 11:36:03 +02:00
2f1029c292
Revert "sawg: advance dds 1/2 by one sample group"
...
This reverts commit 8e0a1cbdc8#772
The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
2017-07-04 17:55:19 +02:00
8e0a1cbdc8
sawg: advance dds 1/2 by one sample group
...
closes #772
2017-07-04 16:51:58 +02:00
91ca9fbcad
sawg: also give offset some headroom
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closes #771
2017-07-04 16:50:06 +02:00
78d1f0fdf6
sawg: fix PhasedAccu resets
2017-07-04 11:56:21 +02:00
Florent Kermarrec
2910b1be5e
artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect
2017-07-04 10:48:06 +02:00
838127d914
rtio: break DMA timing path
2017-07-02 10:24:01 +08:00
911ee4a959
rtio: make pipelined logic reset_less
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* latency-corrected counters
* registered error logic
2017-06-29 12:55:32 +02:00
600a48ac61
dsp.fir: cleanup
2017-06-29 12:18:48 +02:00
dca662a743
dsp.fir: pipeline final systolic adder
2017-06-29 11:33:19 +02:00
32a33500c8
dsp.fir: actively cull zero delays
2017-06-29 11:24:56 +02:00
f520d4a768
rtio: undo _RelaxedAsyncResetSynchronizer
2017-06-28 22:08:15 +02:00
3cbbcdfe96
sawg: don't enable_replace for Config
...
closes #762
2017-06-28 20:31:40 +02:00
f2632e0fd1
sawg: adapt latency to fir changes
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closes #748
2017-06-28 20:12:30 +02:00
e7db2c6578
dsp.accu: reset_less outputs
2017-06-28 20:04:58 +02:00
6bb994228f
dsp.fir: drop x shift
2017-06-28 19:55:15 +02:00
01847271c5
rtio: use reset_less signal for reset fanout
2017-06-28 19:43:55 +02:00
b9859cc0c3
dsp.fir: remove old/wrong comment
2017-06-28 19:21:57 +02:00
55b5b87490
fir: simplify latency compensation
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Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
2017-06-28 19:13:43 +02:00
d1e5dd334f
sawg: use pipeline reset
2017-06-28 19:09:39 +02:00
6418205906
dsp.fir: use pipelin-reset
2017-06-28 19:09:21 +02:00
07f5e99140
dsp/sat_add: works after previous changes
2017-06-22 18:24:22 +02:00
f78d5a87e9
dsp/test: skip and fix sat_add
2017-06-22 18:01:31 +02:00
47928a2c0d
sawg: disable limiter
...
temporary workaround to permit testing other aspects
2017-06-22 17:31:04 +02:00
cd2ac53bc5
dsp/sat_add: make width mandatory
2017-06-22 17:28:39 +02:00
9b940aa876
dsp/sat_add: spell out logic more
2017-06-22 16:55:13 +02:00
d0cf0f2b87
sawg/limiter: make signed signals explicitly
2017-06-22 13:44:36 +02:00
694f8d784c
dsp/tools: unittest sat_add
2017-06-22 11:29:56 +02:00
bd1438d28e
sawg: wrap limits init values
2017-06-22 10:26:29 +02:00
cccd01e81e
sawg: cleanup sat_add logic
2017-06-22 10:26:29 +02:00
5f6e665158
test/sawg: patch delay_mu
2017-06-22 10:26:29 +02:00
570f2cc1ff
dsp/tools/SatAdd: fix reuse of clipped signal
2017-06-22 10:26:29 +02:00
4b3aad2563
sawg: clean up Config
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* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
2017-06-22 10:26:29 +02:00
f4c6879c76
sawg: special case Config RTIO address
2017-06-22 10:26:29 +02:00
ff0da2c9fc
sawg: stage code for y-data exchange on channels
2017-06-22 10:26:29 +02:00
b6569df02f
dsp/tools: clean up SatAddMixin logic
2017-06-22 10:26:29 +02:00
74cf074538
drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times
2017-06-21 17:01:52 +08:00
0d8067256b
rtio: refactor RelaxedAsyncResetSynchronizer
2017-06-18 14:37:08 +02:00
424b2bfbd8
rtio: describe rio and rio_phy domains a bit more
2017-06-17 12:21:07 +02:00
219dfd8984
rtio: add one register level for rio and rio_phy resets
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* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
2017-06-17 12:17:48 +02:00
e19bfd4781
test_sawg_fe: add ref_multiplier to simulated core
2017-06-16 19:45:24 +02:00
2a76034fbc
cri: add note about clearing of o_data
2017-06-16 19:06:00 +02:00
3f37870e25
sawg: register pre-hbf adder
2017-06-13 18:15:44 +02:00
e229edd5d5
sawg: add register after hbf for timing
2017-06-12 23:08:27 +02:00
315338fca9
test/sawg: test HBF overshoot, fix sim patching
2017-06-12 20:35:47 +02:00
9a8a7b9102
sawg: handle clipping interpolator
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* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC
This leaves a factor of two headroom for the sum of the following
effects:
* HBF overshoot (~15 % of the step)
* A1/A2 DDS sum
While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?
closes #743
2017-06-12 20:33:54 +02:00
1fb3995ffc
Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)"
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This reverts commit 6ac9d0c41e
2017-06-12 20:07:25 +02:00
332bcc7f3b
fir: check widths
2017-06-12 20:07:23 +02:00
39a1dcbb3d
test/fir: look at overshoot behavior
2017-06-12 20:06:07 +02:00
6ac9d0c41e
fir/ParallelHBFUpsampler: add headroom (gain=2)
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This addresses part of #743
2017-06-12 18:59:45 +02:00
bfc224d4ba
phaser: adjust to new jesd
2017-05-22 19:59:53 +02:00
679060af1d
phaser: enable dma
2017-05-22 19:32:34 +02:00
4901cb9a8a
sawg: fix clr width
2017-05-22 17:46:55 +02:00
253ee950f6
sawg: fix config channel addr
2017-05-22 17:45:14 +02:00
9ab63920e0
Remove Pipistrello support
...
Closes #658
Closes #381
2017-05-15 17:17:44 +08:00
170d2886fd
Merge branch 'pdq'
...
* pdq:
pdq: documentation
pdq2 -> pdq
pdq2: use 16 bit data, buffered read_mem()
spi: style
pdq2: mem_read
pdq2: align subsequent writes to end
sma_spi: undo cri_con
pdq2: memory write, kernel_invariants
sma_spi: cri/cd changes
sma_spi: LVCMOS25
coredevice.spi: kernel invariants and style
sma_spi: free up user_sma pins
sma_spi: add demo target with SPI on four SMA
pdq2: memory write
pdq2: crc/frame register accessors
doc: pdq2 spi backend
pdq2: config writes
2017-05-12 11:46:45 +02:00
Florent Kermarrec
79c339d4ac
gateware/targets/phaser: jesd core now handles jsync completely
2017-04-26 22:25:08 +02:00
Florent Kermarrec
0546affd4c
gateware/target/phaser: jesd start signal renamed to jsync
2017-04-26 12:27:40 +02:00
ed8edf318d
sma_spi: undo cri_con
2017-04-08 17:19:35 +02:00
16b7f8f50c
sma_spi: cri/cd changes
2017-04-08 17:16:19 +02:00
1e6e81a19e
sma_spi: LVCMOS25
2017-04-08 17:16:19 +02:00
555b3c38c1
sma_spi: free up user_sma pins
2017-04-08 17:16:19 +02:00
2c7c6143ab
sma_spi: add demo target with SPI on four SMA
2017-04-08 17:16:19 +02:00
c2667debf8
drtio: test replace in RTL simulation
2017-04-06 16:33:59 +08:00
729e7b52f0
drtio: collision/replace fixes
2017-04-06 16:33:49 +08:00
83d87b5805
drtio: remove outdated comment
2017-04-06 12:45:10 +08:00
c0100ebc56
rtio: fix indentation
2017-04-06 12:08:13 +08:00
207453efcd
rtio: add a missing case for collision reporting
2017-04-06 11:28:16 +08:00
674bf82f3a
gateware: add cri_con CSRs to all DMA-capable targets
2017-04-06 01:14:09 +08:00
5e3aef45dc
drtio: support collision/replace + detect sequence errors at satellite
2017-04-06 01:06:56 +08:00
whitequark
17b5388259
gateware: remove one stray CRI arbiter remnant.
2017-04-05 16:38:56 +00:00
whitequark
464202d0aa
gateware: connect CRI switch to kernel CPU.
2017-04-05 16:10:53 +00:00
whitequark
47632f81b1
gateware: CRIArbiter -> CRISwitch.
2017-04-05 16:10:39 +00:00
whitequark
391660e545
gateware: simplify the CRI arbiter to use a plain mux.
2017-04-05 15:09:19 +00:00
12249dac57
rtio: do not clear asynchronous error flags on RTIO reset
2017-04-03 00:20:30 +08:00
db3118b916
drtio: use BlindTransfer for error reporting
2017-04-03 00:18:07 +08:00
8c414cebc7
drtio: report busy errors
2017-04-03 00:11:08 +08:00
008678b741
drtio: add infrastructure for reporting busy/collision errors
2017-04-02 23:45:55 +08:00
0a687b7902
drtio: report satellite errors through firmware
2017-04-01 12:18:00 +08:00
28211e0b32
gateware: reset RTIO DMA core when kernel CPU is reset
2017-03-31 15:35:28 +08:00
200c499114
test: change base address in DMA simulation testbench
2017-03-31 13:17:00 +08:00
ea3af1e20e
drtio: remove obsolete CSR accesses from test
2017-03-27 16:44:22 +08:00
b74d6fb9ba
make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads
2017-03-27 16:32:23 +08:00
whitequark
4de336fbe9
gateware: reverse bytes of SDRAM word, not bits.
2017-03-17 11:16:46 +00:00
