f2f7170d20
hmc7043: use recommend I/O standards
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https://github.com/sinara-hw/Sayma_RTM/issues/116#issuecomment-544187952
2019-10-21 22:56:10 +08:00
05e8f24c24
sayma2: JESD204 synchronization
2019-10-18 23:28:47 +08:00
4df2c5d1fb
sayma: prepare for SYSREF align
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We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
2019-10-08 12:30:47 +08:00
90e3b83e80
hmc7043: turn on AMC_FPGA_SYSREF1
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Florent's JESD core won't work at all without.
2019-10-06 22:49:00 +08:00
1bc7743e03
sayma: fix hmc7043 output settings for v2 hardware
2019-10-06 21:50:29 +08:00
ad63908aff
hmc830_7043: enable_fpga_ibuf -> unmute
2019-10-06 18:13:59 +08:00
5ad65b9d30
hmc830_7043: remove clock_mux
2019-10-06 18:13:27 +08:00
43e58c939c
sayma: drop MasterDAC
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This seemed like a good idea then, but it introduces complexity, corner cases, and additional testing difficulties.
Now Sayma works fine with Kasli as a master, which is simpler.
2019-06-14 14:06:16 +08:00
c7205ad82f
sayma_rtm: preliminary v2 support
2019-03-23 12:37:03 +08:00
ec230d6560
sayma: move SYSREF DDMTD to the RTM
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Put RTM Si5324 into bypass mode before running.
Needs rework to cut RTM Si5324 reset trace.
Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315.
Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic).
2019-01-31 20:39:33 +08:00
fa3b40141d
hmc830_7043: document sayma clock muxes
2019-01-31 15:10:11 +08:00
2b0d63db23
hmc830_7043: support 125MHz RTIO
2019-01-28 13:44:08 +08:00
fdbf1cc2b2
sayma: rework DAC SYSREF margin validation
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Previous code did not work when delay range was not enough for two rotations.
This removes autocalibration, to be done later. Uses hardcoded value for now.
2019-01-27 14:17:54 +08:00
7e5c062c2c
firmware: bypass channel divider for HMC7043 DCLK
2019-01-27 11:49:34 +08:00
3356717316
sayma: DDMTD SYSREF measurement demonstration
2019-01-25 16:00:31 +08:00
4941fb3300
sayma: 2.4GHz DAC clocking (4X interpolation)
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* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
2019-01-25 13:47:04 +08:00
cc9420d2c8
hmc7043: fix divider programming
2019-01-25 11:48:50 +08:00
bbac92442f
sayma: check hmc7043 slip period
2019-01-24 20:13:43 +08:00
f8b39b0b9a
sayma: enable 2X DAC interpolation
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Seems to work just fine and gets one clock divider out of the way.
2019-01-24 18:28:01 +08:00
d1d26e2aa3
hmc7043: add explanation about HMC_SYSREF_DIV
2018-08-18 11:43:40 +08:00
f75a317446
hmc7043: automatically determine output groups
2018-08-18 11:43:23 +08:00
c498b28f88
hmc7043: disable FPGA_ADC_SYSREF
2018-08-18 11:42:57 +08:00
167e97efd2
sayma: support external RTM clocking
2018-08-17 22:57:54 +08:00
738d2c6bcb
hmc7043: REFSYNCIN → RFSYNCIN
2018-08-11 12:07:17 +08:00
49f7a1610f
sayma: use GTP_CLK1 only for all variants ( #1080 )
2018-08-07 20:53:14 +08:00
e83ee3a07a
hmc7043: disable GTP_CLK1 when not in use
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Termination and biasing are not active at the FPGA when IBUFDS_GTE3 is
not instantiated, and driving a clock then leads to overvoltage.
2018-08-03 10:03:52 +08:00
446f791180
firmware: simplify SYSREF DRTIO alignment
2018-07-26 19:37:59 +08:00
dbcf2fe9b4
firmware: remove 'chip found' messages on Sayma
2018-07-26 16:07:37 +08:00
d523d03f71
sayma: automated FPGA SYSREF phase offset calibration
2018-07-26 14:53:28 +08:00
29c35ee553
hmc7043: fix dumb mistake in previous commit
2018-07-12 13:01:41 +08:00
8802b930de
hmc7043: add delay after init
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Delay required at step 9 of the "Typical Programming Sequence" (page 24 of the datasheet)
2018-07-12 12:37:12 +08:00
c66f9483f8
hmc7043: wait after changing delays
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Allows for the SPI transaction to finish, and for the delay to stabilize.
2018-07-12 12:33:53 +08:00
773240bef4
hmc7043: test GPO before using
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Based on code by David.
2018-07-12 11:30:24 +08:00
4843832329
hmc7043: check phase status on init. Closes #1055
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Troubleshooting by David.
2018-07-11 19:45:24 +08:00
9397fa7f5a
hmc7043: unstick SYSREF FSM ( #1055 )
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Troubleshooting by David.
Additionally, register 7D is broken.
Checking phase init state has to be done through another means.
2018-07-11 19:11:01 +08:00
4eb26c0050
hmc7043: enable group 5
2018-07-03 14:16:31 +02:00
a65721d649
sayma: put RTM clock tree into the siphaser loop
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* Fixes one bug where siphaser was one Si5324 output and the rest of the
system was clocked by the other. With the Si5324 settings we have, skew
between the outputs is not controlled.
* Puts the coaxial cable between AMC and RTM into the siphaser loop.
2018-06-27 21:46:55 +08:00
46c044099c
hmc7043,satman: verify alignment of SYSREF slips
2018-06-27 17:36:13 +08:00
7dfd70c502
hmc7043: make margin_{minus,plus} consistent with ad9154
2018-06-27 17:35:26 +08:00
4bbdd43bdf
hmc7043: do not freeze if SYSREF slip fails
2018-06-27 17:32:56 +08:00
de7d64d482
sayma: clock JESD204 from GTP CLK2
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This frees up GTP CLK1, which is routable to the SFP quads, for DRTIO.
2018-06-21 22:33:53 +08:00
07bcdfd91e
hmc7043: stricter check of FPGA SYSREF margin
2018-06-21 22:26:49 +08:00
5a2a857a2f
firmware: clean up SYSREF phase management
2018-06-21 16:23:41 +08:00
05e908a0fd
hmc7043: align SYSREF with RTIO
2018-06-21 15:54:42 +08:00
9741654cad
hmc7043: style
2018-06-21 15:54:42 +08:00
45e8263208
hmc7043: do not configure phases during initial init
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They are determined later on.
2018-06-21 15:54:42 +08:00
814d0583db
hmc7043: improve smoothness of sysref phase control
2018-06-20 17:40:48 +08:00
5272c11704
typo
2018-06-20 17:05:20 +08:00
3d0e92aefd
hmc7043: check that chip is disabled at startup
2018-06-19 23:49:17 +08:00
740e6863c3
hmc7043: add delay after releasing hardware reset
2018-06-19 23:48:48 +08:00
