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Merge pull request #1628 from pathfinder49/fastino_mu_fix 

fastino: ensure `xxx_to_mu()` methods return int32 on the host
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Robert Jördens 2021-04-15 15:02:12 +02:00 committed by GitHub
parent 78490bef5d bda5aa7c7e
commit ffe1c9f9b1
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1 changed files with 3 additions and 2 deletions
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5
artiq/coredevice/fastino.py
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@ -1,6 +1,7 @@
"""RTIO driver for the Fastino 32channel, 16 bit, 2.5 MS/s per channel, """RTIO driver for the Fastino 32channel, 16 bit, 2.5 MS/s per channel,
streaming DAC. streaming DAC.
""" """
from numpy import int32
from artiq.language.core import kernel, portable, delay from artiq.language.core import kernel, portable, delay
from artiq.coredevice.rtio import (rtio_output, rtio_output_wide, from artiq.coredevice.rtio import (rtio_output, rtio_output_wide,
@ -112,7 +113,7 @@ class Fastino:
:param voltage: Voltage in SI Volts. :param voltage: Voltage in SI Volts.
:return: DAC data word in machine units, 16 bit integer. :return: DAC data word in machine units, 16 bit integer.
""" """
data = int(round((0x8000/10.)*voltage)) + 0x8000 data = int32(round((0x8000/10.)*voltage)) + int32(0x8000)
if data < 0 or data > 0xffff: if data < 0 or data > 0xffff:
raise ValueError("DAC voltage out of bounds") raise ValueError("DAC voltage out of bounds")
return data return data
@ -129,7 +130,7 @@ class Fastino:
v = self.voltage_to_mu(voltage[i]) v = self.voltage_to_mu(voltage[i])
if i & 1: if i & 1:
v = data[i // 2] | (v << 16) v = data[i // 2] | (v << 16)
data[i // 2] = v data[i // 2] = int32(v)
@kernel @kernel
def set_dac(self, dac, voltage): def set_dac(self, dac, voltage):