forked from M-Labs/artiq
rtio: use input collector module
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4dc80e3d05
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@ -2,8 +2,6 @@ from functools import reduce
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from operator import and_
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from migen import *
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from migen.genlib.record import Record
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import PulseSynchronizer
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from misoc.interconnect.csr import *
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@ -13,141 +11,7 @@ from artiq.gateware.rtio import rtlink
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from artiq.gateware.rtio.channel import *
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from artiq.gateware.rtio.cdc import *
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from artiq.gateware.rtio.sed.core import *
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class _InputManager(Module):
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def __init__(self, interface, coarse_ts, fifo_depth):
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data_width = rtlink.get_data_width(interface)
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fine_ts_width = rtlink.get_fine_ts_width(interface)
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ev_layout = []
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if data_width:
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ev_layout.append(("data", data_width))
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if interface.timestamped:
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ev_layout.append(("timestamp", len(coarse_ts) + fine_ts_width))
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self.ev = Record(ev_layout)
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self.readable = Signal()
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self.re = Signal()
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self.overflow = Signal() # pulsed
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# # #
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fifo = ClockDomainsRenamer({"read": "rsys", "write": "rio"})(
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AsyncFIFO(layout_len(ev_layout), fifo_depth))
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self.submodules += fifo
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fifo_in = Record(ev_layout)
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fifo_out = Record(ev_layout)
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self.comb += [
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fifo.din.eq(fifo_in.raw_bits()),
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fifo_out.raw_bits().eq(fifo.dout)
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]
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# latency compensation
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if interface.delay:
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counter_rtio = Signal.like(coarse_ts, reset_less=True)
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self.sync.rtio += counter_rtio.eq(coarse_ts -
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(interface.delay + 1))
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else:
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counter_rtio = coarse_ts
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# FIFO write
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if data_width:
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self.comb += fifo_in.data.eq(interface.data)
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if interface.timestamped:
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if fine_ts_width:
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full_ts = Cat(interface.fine_ts, counter_rtio)
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else:
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full_ts = counter_rtio
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self.comb += fifo_in.timestamp.eq(full_ts)
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self.comb += fifo.we.eq(interface.stb)
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# FIFO read
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self.comb += [
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self.ev.eq(fifo_out),
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self.readable.eq(fifo.readable),
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fifo.re.eq(self.re)
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]
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overflow_transfer = BlindTransfer()
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self.submodules += overflow_transfer
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self.comb += [
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overflow_transfer.i.eq(fifo.we & ~fifo.writable),
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self.overflow.eq(overflow_transfer.o),
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]
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class _Inputs(Module):
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def __init__(self, interface, coarse_ts, channels):
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self.cri = interface
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# Inputs
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i_statuses = []
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i_datas, i_timestamps = [], []
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i_ack = Signal()
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sel = self.cri.chan_sel[:16]
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for n, channel in enumerate(channels):
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if isinstance(channel, LogChannel):
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i_datas.append(0)
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i_timestamps.append(0)
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i_statuses.append(0)
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continue
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if channel.interface.i is not None:
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selected = Signal()
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self.comb += selected.eq(sel == n)
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i_manager = _InputManager(channel.interface.i, coarse_ts,
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channel.ififo_depth)
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self.submodules += i_manager
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if hasattr(i_manager.ev, "data"):
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i_datas.append(i_manager.ev.data)
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else:
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i_datas.append(0)
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if channel.interface.i.timestamped:
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ts_shift = (len(self.cri.i_timestamp) - len(i_manager.ev.timestamp))
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i_timestamps.append(i_manager.ev.timestamp << ts_shift)
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else:
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i_timestamps.append(0)
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overflow = Signal()
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self.sync.rsys += [
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If(selected & i_ack,
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overflow.eq(0)),
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If(i_manager.overflow,
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overflow.eq(1))
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]
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self.comb += i_manager.re.eq(selected & i_ack & ~overflow)
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i_statuses.append(Cat(i_manager.readable & ~overflow, overflow))
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else:
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i_datas.append(0)
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i_timestamps.append(0)
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i_statuses.append(0)
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i_status_raw = Signal(2)
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self.comb += i_status_raw.eq(Array(i_statuses)[sel])
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input_timeout = Signal.like(self.cri.timestamp)
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input_pending = Signal()
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self.sync.rsys += [
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i_ack.eq(0),
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If(i_ack,
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self.cri.i_status.eq(Cat(~i_status_raw[0], i_status_raw[1], 0)),
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self.cri.i_data.eq(Array(i_datas)[sel]),
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self.cri.i_timestamp.eq(Array(i_timestamps)[sel]),
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),
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If((self.cri.counter >= input_timeout) | (i_status_raw != 0),
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If(input_pending, i_ack.eq(1)),
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input_pending.eq(0)
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),
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If(self.cri.cmd == cri.commands["read"],
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input_timeout.eq(self.cri.timestamp),
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input_pending.eq(1),
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self.cri.i_status.eq(0b100)
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)
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]
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from artiq.gateware.rtio.input_collector import *
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class Core(Module, AutoCSR):
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@ -190,17 +54,17 @@ class Core(Module, AutoCSR):
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self.specials += AsyncResetSynchronizer(self.cd_rio_phy, cmd_reset_phy)
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# TSC
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fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
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for channel in channels),
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max(rtlink.get_fine_ts_width(channel.interface.i)
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for channel in channels))
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coarse_ts = Signal(64-fine_ts_width)
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glbl_fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
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for channel in channels),
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max(rtlink.get_fine_ts_width(channel.interface.i)
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for channel in channels))
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coarse_ts = Signal(64-glbl_fine_ts_width)
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self.sync.rtio += coarse_ts.eq(coarse_ts + 1)
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coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts))
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self.submodules += coarse_ts_cdc
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self.comb += [
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coarse_ts_cdc.i.eq(coarse_ts),
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self.cri.counter.eq(coarse_ts_cdc.o << fine_ts_width)
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self.cri.counter.eq(coarse_ts_cdc.o << glbl_fine_ts_width)
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]
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# Asychronous output errors
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@ -219,13 +83,12 @@ class Core(Module, AutoCSR):
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]
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self.comb += self.async_error.w.eq(Cat(o_collision, o_busy))
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# Inputs
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inputs = _Inputs(self.cri, coarse_ts, channels)
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self.submodules += inputs
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# Outputs
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outputs = SED(channels, "async",
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quash_channels=[n for n, c in enumerate(channels) if isinstance(c, LogChannel)],
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# Outputs/Inputs
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quash_channels = [n for n, c in enumerate(channels) if isinstance(c, LogChannel)]
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outputs = SED(channels, glbl_fine_ts_width, "async",
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quash_channels=quash_channels,
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interface=self.cri)
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self.submodules += outputs
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self.comb += outputs.coarse_timestamp.eq(coarse_ts)
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@ -234,3 +97,8 @@ class Core(Module, AutoCSR):
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o_collision_sync.i.eq(outputs.collision),
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o_busy_sync.i.eq(outputs.busy)
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]
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inputs = InputCollector(channels, glbl_fine_ts_width, "async",
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quash_channels=quash_channels,
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interface=self.cri)
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self.submodules += inputs
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