From ff0da2c9fc66afecae1ad141fe2c4d089c5d7fcc Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 21 Jun 2017 13:10:09 +0200 Subject: [PATCH] sawg: stage code for y-data exchange on channels --- artiq/gateware/targets/phaser.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py index cdd16e1c8..fe141837f 100755 --- a/artiq/gateware/targets/phaser.py +++ b/artiq/gateware/targets/phaser.py @@ -142,6 +142,11 @@ class AD9154(Module, AutoCSR): self.sawgs = [sawg.Channel(width=16, parallelism=2) for i in range(4)] self.submodules += self.sawgs + # self.sawgs[0].connect_y(self.sawgs[1]) + # self.sawgs[1].connect_y(self.sawgs[0]) + # self.sawgs[2].connect_y(self.sawgs[3]) + # self.sawgs[3].connect_y(self.sawgs[2]) + for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs): self.sync.jesd += conv.eq(Cat(ch.o))