forked from M-Labs/artiq
rtio/sed: add lane distributor simulation unittest
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import unittest
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from migen import *
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from artiq.gateware.rtio import cri
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from artiq.gateware.rtio.sed import lane_distributor
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LANE_COUNT = 8
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def simulate(input_events):
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dut = lane_distributor.LaneDistributor(LANE_COUNT, 16, [("channel", 8), ("timestamp", 32)], 3)
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output = []
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access_results = []
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def gen():
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for channel, timestamp in input_events:
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yield dut.cri.chan_sel.eq(channel)
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yield dut.cri.timestamp.eq(timestamp)
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yield
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yield dut.cri.cmd.eq(cri.commands["write"])
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yield
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yield dut.cri.cmd.eq(cri.commands["nop"])
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access_time = 0
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yield
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while (yield dut.cri.o_status) & 0x01:
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yield
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access_time += 1
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status = (yield dut.cri.o_status)
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access_status = "ok"
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if status & 0x02:
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access_status = "underflow"
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if status & 0x04:
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access_status = "sequence_error"
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access_results.append((access_status, access_time))
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@passive
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def monitor_lane(n, lio, wait_time):
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yield lio.writable.eq(1)
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while True:
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while not (yield lio.we):
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yield
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seqn = (yield lio.seqn)
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channel = (yield lio.payload.channel)
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timestamp = (yield lio.payload.timestamp)
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output.append((n, seqn, channel, timestamp))
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yield lio.writable.eq(0)
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for i in range(wait_time):
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yield
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yield lio.writable.eq(1)
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yield
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generators = [gen()]
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for n, lio in enumerate(dut.lane_io):
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if n == 6:
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wait_time = 1
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elif n == 7:
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wait_time = 4
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else:
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wait_time = 0
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generators.append(monitor_lane(n, lio, wait_time))
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run_simulation(dut, generators)
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return output, access_results
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class TestLaneDistributor(unittest.TestCase):
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def test_regular(self):
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# Assumes lane 0 does not have wait time.
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N = 16
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output, access_results = simulate([(42+n, (n+1)*8) for n in range(N)])
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self.assertEqual(output, [(0, n, 42+n, (n+1)*8) for n in range(N)])
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self.assertEqual(access_results, [("ok", 0)]*N)
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def test_wait_time(self):
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output, access_results = simulate([(42+n, 8) for n in range(LANE_COUNT)])
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self.assertEqual(output, [(n, n, 42+n, 8) for n in range(LANE_COUNT)])
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expected_access_results = [("ok", 0)]*LANE_COUNT
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expected_access_results[6] = ("ok", 1)
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expected_access_results[7] = ("ok", 4)
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self.assertEqual(access_results, expected_access_results)
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def test_lane_switch(self):
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N = 32
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output, access_results = simulate([(42+n, n+8) for n in range(N)])
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self.assertEqual(output, [((n-n//8) % LANE_COUNT, n, 42+n, n+8) for n in range(N)])
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self.assertEqual([ar[0] for ar in access_results], ["ok"]*N)
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def test_sequence_error(self):
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input_events = [(42+n, 8) for n in range(LANE_COUNT+1)]
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input_events.append((42+LANE_COUNT+1, 16))
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output, access_results = simulate(input_events)
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self.assertEqual(len(output), len(input_events)-1) # event with sequence error must get discarded
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self.assertEqual([ar[0] for ar in access_results[:LANE_COUNT]], ["ok"]*LANE_COUNT)
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self.assertEqual(access_results[LANE_COUNT][0], "sequence_error")
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def test_underflow(self):
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N = 16
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input_events = [(42+n, (n+1)*8) for n in range(N-2)]
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input_events.append((0, 0)) # timestamp < 8 underflows
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input_events.append((42+N-2, N*8))
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output, access_results = simulate(input_events)
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self.assertEqual(len(output), len(input_events)-1) # event with underflow must get discarded
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self.assertEqual([ar[0] for ar in access_results[:N-2]], ["ok"]*(N-2))
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self.assertEqual(access_results[N-2][0], "underflow")
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self.assertEqual(output[N-2], (0, N-2, 42+N-2, N*8))
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self.assertEqual(access_results[N-1][0], "ok")
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