forked from M-Labs/artiq
pdq: documentation
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@ -11,6 +11,16 @@ _PDQ_SPI_CONFIG = (
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@portable
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def _PDQ_CMD(board, is_mem, adr, we):
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"""Pack PDQ command fields into command byte.
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:param board: Board address, 0 to 15, with ``15 = 0xf`` denoting broadcast
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to all boards connected.
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:param is_mem: If ``1``, ``adr`` denote the address of the memory to access
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(0 to 2). Otherwise ``adr`` denotes the register to access.
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:param adr: Address of the register or memory to access.
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(``_PDQ_ADR_CONFIG``, ``_PDQ_ADR_FRAME``, ``_PDQ_ADR_CRC``).
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:param we: If ``1`` then write, otherwise read.
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"""
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return (adr << 0) | (is_mem << 2) | (board << 3) | (we << 7)
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@ -20,11 +30,22 @@ _PDQ_ADR_FRAME = 2
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class PDQ:
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"""
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"""PDQ smart arbitrary waveform generator stack.
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Provides access to a stack of PDQ boards connected via SPI using PDQ
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gateware version 3 or later.
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The SPI bus is wired with ``CS_N`` from the core device connected to
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``F2 IN`` on the master PDQ, ``CLK`` connected to ``F3 IN``, ``MOSI``
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connected to ``F4 IN`` and ``MISO`` (optionally) connected to ``F5 OUT``.
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``F1 TTL Input Trigger`` remains as waveform trigger input.
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Due to hardware constraints, there can only be one board connected to the
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core device's MISO line and therefore there can only be SPI readback
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from one board at any time.
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:param spi_device: Name of the SPI bus this device is on.
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:param chip_select: Value to drive on the chip select lines
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during transactions.
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:param chip_select: Value to drive on the chip select lines of the SPI bus
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during transactions.
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"""
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kernel_invariants = {"core", "chip_select", "bus"}
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@ -54,11 +75,26 @@ class PDQ:
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@kernel
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def write_reg(self, adr, data, board):
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"""Set a PDQ register.
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:param adr: Address of the register (``_PDQ_ADR_CONFIG``,
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``_PDQ_ADR_FRAME``, ``_PDQ_ADR_CRC``).
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:param data: Register data (8 bit).
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:param board: Board to access, ``0xf`` to write to all boards.
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"""
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self.bus.write((_PDQ_CMD(board, 0, adr, 1) << 24) | (data << 16))
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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@kernel
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def read_reg(self, adr, board):
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"""Get a PDQ register.
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:param adr: Address of the register (``_PDQ_ADR_CONFIG``,
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``_PDQ_ADR_FRAME``, ``_PDQ_ADR_CRC``).
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:param board: Board to access, ``0xf`` to write to all boards.
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:return: Register data (8 bit).
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"""
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self.bus.set_xfer(self.chip_select, 16, 8)
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self.bus.write(_PDQ_CMD(board, 0, adr, 0) << 24)
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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@ -69,32 +105,58 @@ class PDQ:
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@kernel
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def write_config(self, reset=0, clk2x=0, enable=1,
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trigger=0, aux_miso=0, aux_dac=0b111, board=0xf):
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"""Set configuration register.
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:param reset: Reset board (auto-clear).
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:param clk2x: Enable clock double (100 MHz).
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:param enable: Enable the reading and execution of waveform data from
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memory.
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:param trigger: Software trigger, logical OR with ``F1 TTL Input
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Trigger``.
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:param aux_miso: Use ``F5 OUT`` for ``MISO``. If ``0``, use the
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masked logical OR of the DAC channels.
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:param aux_dac: DAC channel mask to for AUX (``F5 OUT``) output.
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:param board: Boards to address, ``0xf`` to write to all boards.
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"""
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config = ((reset << 0) | (clk2x << 1) | (enable << 2) |
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(trigger << 3) | (aux_miso << 4) | (aux_dac << 5))
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self.write_reg(_PDQ_ADR_CONFIG, config, board)
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@kernel
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def read_config(self, board=0xf):
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"""Read configuration register."""
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return self.read_reg(_PDQ_ADR_CONFIG, board)
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@kernel
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def write_crc(self, crc, board=0xf):
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"""Write checksum register."""
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self.write_reg(_PDQ_ADR_CRC, crc, board)
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@kernel
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def read_crc(self, board=0xf):
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"""Read checksum register."""
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return self.read_reg(_PDQ_ADR_CRC, board)
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@kernel
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def write_frame(self, frame, board=0xf):
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"""Write frame selection register."""
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self.write_reg(_PDQ_ADR_FRAME, frame, board)
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@kernel
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def read_frame(self, board=0xf):
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"""Read frame selection register."""
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return self.read_reg(_PDQ_ADR_FRAME, board)
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@kernel
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def write_mem(self, mem, adr, data, board=0xf): # FIXME: m-labs/artiq#714
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"""Write to DAC channel waveform data memory.
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:param mem: DAC channel memory to access (0 to 2).
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:param adr: Start address.
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:param data: Memory data. List of 16 bit integers.
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:param board: Board to access (0-15) with ``0xf = 15`` being broadcast
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to all boards.
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"""
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self.bus.set_xfer(self.chip_select, 24, 0)
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self.bus.write((_PDQ_CMD(board, 1, mem, 1) << 24) |
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((adr & 0x00ff) << 16) | (adr & 0xff00))
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@ -108,6 +170,14 @@ class PDQ:
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@kernel
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def read_mem(self, mem, adr, data, board=0xf, buffer=8):
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"""Read from DAC channel waveform data memory.
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:param mem: DAC channel memory to access (0 to 2).
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:param adr: Start address.
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:param data: Memory data. List of 16 bit integers.
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:param board: Board to access (0-15) with ``0xf = 15`` being broadcast
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to all boards.
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"""
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n = len(data)
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if not n:
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return
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