From fe93a454d68b6e6db697c0c0c6f550ec95bbb691 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 19 Jul 2018 14:10:36 +0800 Subject: [PATCH] fmcdio_vhdci_eem: fix direction shift register permutation and polarity --- artiq/coredevice/fmcdio_vhdci_eem.py | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/artiq/coredevice/fmcdio_vhdci_eem.py b/artiq/coredevice/fmcdio_vhdci_eem.py index 13d6224b0..d10378feb 100644 --- a/artiq/coredevice/fmcdio_vhdci_eem.py +++ b/artiq/coredevice/fmcdio_vhdci_eem.py @@ -6,11 +6,20 @@ eem_fmc_connections = { } +fmcdio_shiftreg_permutation = [ + 1, 0, 3, 2, 5, 4, 7, 6, + 9, 8, 11, 10, 13, 12, 15, 14, + 17, 16, 19, 18, 21, 20, 23, 22, + 25, 24, 27, 26, 29, 28, 31, 30 +] + + def shiftreg_bits(eem, out_pins): r = 0 for i in range(8): - if i in out_pins: - shift = eem_fmc_connections[eem][i] + if i not in out_pins: + lvds_line = eem_fmc_connections[eem][i] + shift = fmcdio_shiftreg_permutation.index(lvds_line) r |= 1 << shift return r