forked from M-Labs/artiq
fmcdio_vhdci_eem: fix direction shift register permutation and polarity
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@ -6,11 +6,20 @@ eem_fmc_connections = {
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}
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fmcdio_shiftreg_permutation = [
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1, 0, 3, 2, 5, 4, 7, 6,
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9, 8, 11, 10, 13, 12, 15, 14,
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17, 16, 19, 18, 21, 20, 23, 22,
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25, 24, 27, 26, 29, 28, 31, 30
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]
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def shiftreg_bits(eem, out_pins):
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r = 0
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for i in range(8):
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if i in out_pins:
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shift = eem_fmc_connections[eem][i]
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if i not in out_pins:
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lvds_line = eem_fmc_connections[eem][i]
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shift = fmcdio_shiftreg_permutation.index(lvds_line)
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r |= 1 << shift
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return r
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