forked from M-Labs/artiq
targets: kc705 -> kc705_dds
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8be9a827ba
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@ -84,7 +84,7 @@ def main():
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if action == "build":
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logger.info("Building runtime")
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try:
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subprocess.check_call(["python3", "-m", "artiq.gateware.targets.kc705",
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subprocess.check_call(["python3", "-m", "artiq.gateware.targets.kc705_dds",
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"-H", "nist_clock",
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"--no-compile-gateware",
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"--output-dir", "/tmp/kc705"])
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@ -314,8 +314,8 @@ class NIST_QC2(_NIST_Ions):
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ core device builder / KC705 "
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"+ NIST Ions CLOCK/QC2 hardware adapters")
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description="ARTIQ device binary builder / single-FPGA KC705-based "
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"systems with AD9 DDS (NIST Ions hardware)")
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builder_args(parser)
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soc_kc705_args(parser)
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parser.add_argument("-H", "--hw-adapter", default="nist_clock",
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@ -105,7 +105,7 @@ class Master(MiniSoC, AMPSoC):
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ with DRTIO on KC705 - Master")
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description="ARTIQ device binary builder / KC705 DRTIO master")
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builder_args(parser)
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soc_kc705_args(parser)
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parser.add_argument("-c", "--config", default="simple_gbe",
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@ -202,7 +202,7 @@ class Satellite(BaseSoC):
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ with DRTIO on KC705 - Satellite")
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description="ARTIQ device binary builder / KC705 DRTIO satellite")
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builder_args(parser)
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soc_kc705_args(parser)
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parser.add_argument("-c", "--config", default="simple_gbe",
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@ -257,8 +257,7 @@ class Phaser(MiniSoC, AMPSoC):
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ core device builder for "
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"KC705+AD9154 hardware")
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description="ARTIQ device binary builder / KC705 phaser demo")
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builder_args(parser)
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soc_kc705_args(parser)
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args = parser.parse_args()
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@ -229,7 +229,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ core device builder / Pipistrello demo")
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description="ARTIQ device binary builder / Pipistrello demo")
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builder_args(parser)
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soc_pipistrello_args(parser)
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args = parser.parse_args()
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@ -6,7 +6,7 @@ BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
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SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-nist_clock
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mkdir -p $SOC_PREFIX
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$PYTHON -m artiq.gateware.targets.kc705 -H nist_clock --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
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$PYTHON -m artiq.gateware.targets.kc705_dds -H nist_clock --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
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cp misoc_nist_clock_kc705/gateware/top.bit $SOC_PREFIX
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cp misoc_nist_clock_kc705/software/bios/bios.bin $SOC_PREFIX
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cp misoc_nist_clock_kc705/software/runtime/runtime.fbi $SOC_PREFIX
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@ -6,7 +6,7 @@ BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
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SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-nist_qc2
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mkdir -p $SOC_PREFIX
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$PYTHON -m artiq.gateware.targets.kc705 -H nist_qc2 --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
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$PYTHON -m artiq.gateware.targets.kc705_dds -H nist_qc2 --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
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cp misoc_nist_qc2_kc705/gateware/top.bit $SOC_PREFIX
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cp misoc_nist_qc2_kc705/software/bios/bios.bin $SOC_PREFIX
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cp misoc_nist_qc2_kc705/software/runtime/runtime.fbi $SOC_PREFIX
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@ -170,7 +170,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
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* For KC705::
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$ python3.5 -m artiq.gateware.targets.kc705 -H nist_clock # or nist_qc2
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$ python3.5 -m artiq.gateware.targets.kc705_dds -H nist_clock # or nist_qc2
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.. note:: Add ``--toolchain ise`` if you wish to use ISE instead of Vivado.
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