From fcb611d1d2ccb7b69feb1a4eb9d1e46dc564601a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Wed, 7 Nov 2018 18:18:35 +0100 Subject: [PATCH] test_ad9910: don't expect large SYNC_IN delay margins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit sinara-hw/Urukul#16 Signed-off-by: Robert Jördens --- artiq/test/coredevice/test_ad9910.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/artiq/test/coredevice/test_ad9910.py b/artiq/test/coredevice/test_ad9910.py index 1243760cc..4ce47fdee 100644 --- a/artiq/test/coredevice/test_ad9910.py +++ b/artiq/test/coredevice/test_ad9910.py @@ -82,7 +82,9 @@ class AD9910Exp(EnvExperiment): print(err) self.core.break_realtime() dly, win = self.dev.tune_sync_delay() - self.sync_scan(err, win=win + 1) # tighten window by 2*75ps + self.sync_scan(err, win=win) + # FIXME: win + 1 # tighten window by 2*75ps + # after https://github.com/sinara-hw/Urukul/issues/16 self.set_dataset("dly", dly) self.set_dataset("win", win) self.set_dataset("err", err)