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drtio: remove spurious multichannel transceiver clock constraints 

They used to cause (otherwise harmless) Vivado critical warnings.
This commit is contained in:
Sebastien Bourdeauducq 2018-03-09 22:46:20 +08:00
parent caf7b14b55
commit fc3d97f1f7
2 changed files with 16 additions and 8 deletions
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6
artiq/gateware/targets/kasli.py
View File

@ -472,12 +472,16 @@ class _MasterBase(MiniSoC, AMPSoC):
self.add_memory_group("drtio_aux", drtio_memory_group) self.add_memory_group("drtio_aux", drtio_memory_group)
rtio_clk_period = 1e9/rtio_clk_freq rtio_clk_period = 1e9/rtio_clk_freq
for gtp in self.drtio_transceiver.gtps: gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk) gtp.txoutclk, gtp.rxoutclk)
for gtp in self.drtio_transceiver.gtps[1:]:
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.rxoutclk)
self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq) self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)

6
artiq/gateware/targets/sayma_amc.py
View File

@ -330,12 +330,16 @@ class Master(MiniSoC, AMPSoC):
self.add_memory_group("drtio_aux", drtio_memory_group) self.add_memory_group("drtio_aux", drtio_memory_group)
rtio_clk_period = 1e9/rtio_clk_freq rtio_clk_period = 1e9/rtio_clk_freq
for gth in self.drtio_transceiver.gths: gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period) platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.crg.cd_sys.clk,
gth.txoutclk, gth.rxoutclk) gth.txoutclk, gth.rxoutclk)
for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gth.rxoutclk)
rtio_channels = [] rtio_channels = []
for i in range(4): for i in range(4):