From fc3d97f1f76121e4cbc5b734a7c0129c353547b1 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 9 Mar 2018 22:46:20 +0800 Subject: [PATCH] drtio: remove spurious multichannel transceiver clock constraints They used to cause (otherwise harmless) Vivado critical warnings. --- artiq/gateware/targets/kasli.py | 12 ++++++++---- artiq/gateware/targets/sayma_amc.py | 12 ++++++++---- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 2d6a1b5cb..824699780 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -472,12 +472,16 @@ class _MasterBase(MiniSoC, AMPSoC): self.add_memory_group("drtio_aux", drtio_memory_group) rtio_clk_period = 1e9/rtio_clk_freq - for gtp in self.drtio_transceiver.gtps: + gtp = self.drtio_transceiver.gtps[0] + platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) + platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) + platform.add_false_path_constraints( + self.crg.cd_sys.clk, + gtp.txoutclk, gtp.rxoutclk) + for gtp in self.drtio_transceiver.gtps[1:]: platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) - platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.crg.cd_sys.clk, - gtp.txoutclk, gtp.rxoutclk) + self.crg.cd_sys.clk, gtp.rxoutclk) self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 6e909f2db..0b25886ba 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -330,12 +330,16 @@ class Master(MiniSoC, AMPSoC): self.add_memory_group("drtio_aux", drtio_memory_group) rtio_clk_period = 1e9/rtio_clk_freq - for gth in self.drtio_transceiver.gths: - platform.add_period_constraint(gth.txoutclk, rtio_clk_period) + gth = self.drtio_transceiver.gths[0] + platform.add_period_constraint(gth.txoutclk, rtio_clk_period) + platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) + platform.add_false_path_constraints( + self.crg.cd_sys.clk, + gth.txoutclk, gth.rxoutclk) + for gth in self.drtio_transceiver.gths[1:]: platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.crg.cd_sys.clk, - gth.txoutclk, gth.rxoutclk) + self.crg.cd_sys.clk, gth.rxoutclk) rtio_channels = [] for i in range(4):