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serdes_s6: no need to reset

This commit is contained in:
Robert Jördens 2015-07-28 01:21:11 -06:00
parent 9dfbf07743
commit fb339d294e
1 changed files with 1 additions and 2 deletions
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artiq/gateware/rtio/phy/ttl_serdes_spartan6.py
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@ -103,8 +103,7 @@ class _OSERDES2_4X(Module):
p_DATA_WIDTH=4, p_OUTPUT_MODE="SINGLE_ENDED", p_DATA_WIDTH=4, p_OUTPUT_MODE="SINGLE_ENDED",
i_TRAIN=0, i_CLK0=ClockSignal("rtiox4"), i_TRAIN=0, i_CLK0=ClockSignal("rtiox4"),
i_CLK1=0, i_CLKDIV=ClockSignal("rio_phy"), i_CLK1=0, i_CLKDIV=ClockSignal("rio_phy"),
i_IOCE=stb, i_OCE=1, i_TCE=1, i_IOCE=stb, i_OCE=1, i_TCE=1, i_RST=0,
i_RST=ResetSignal(),
i_T4=self.t_in, i_T3=self.t_in, i_T4=self.t_in, i_T3=self.t_in,
i_T2=self.t_in, i_T1=self.t_in, i_T2=self.t_in, i_T1=self.t_in,
i_D4=o[3], i_D3=o[2], i_D2=o[1], i_D1=o[0], i_D4=o[3], i_D3=o[2], i_D2=o[1], i_D1=o[0],