forked from M-Labs/artiq
firmware: fix non-DRTIO build
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ec7b2bea12
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fb0ade77a9
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@ -158,12 +158,14 @@ pub fn init() {
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}
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#[cfg(has_drtio)]
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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clock::spin_us(1500); // wait for CPLL/QPLL lock
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unsafe {
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csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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{
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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clock::spin_us(1500); // wait for CPLL/QPLL lock
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unsafe {
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csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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}
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}
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#[cfg(has_rtio_crg)]
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