From fa41c946ea7cce06167bde3bc5f9d88678d6eb09 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 20 Nov 2019 17:04:24 +0800 Subject: [PATCH] wrpll: si549 fixes --- artiq/gateware/drtio/wrpll/si549.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/drtio/wrpll/si549.py b/artiq/gateware/drtio/wrpll/si549.py index 652e3f0b5..a0f2c985a 100644 --- a/artiq/gateware/drtio/wrpll/si549.py +++ b/artiq/gateware/drtio/wrpll/si549.py @@ -170,7 +170,7 @@ class ADPLLProgrammer(Module): self.submodules += master self.comb += [ - master.cg.load.eq(self.i2c_divider.storage), + master.cg.load.eq(self.i2c_divider), self.scl.eq(master.scl), master.sda_i.eq(self.sda_i), self.sda_o.eq(master.sda_o) @@ -184,7 +184,7 @@ class Si549(Module, AutoCSR): self.gpio_out = CSRStorage(2) self.gpio_oe = CSRStorage(2) - self.i2c_divider = CSRStorage(16) + self.i2c_divider = CSRStorage(16, reset=2500) self.i2c_address = CSRStorage(7) self.errors = CSR(2) @@ -205,7 +205,7 @@ class Si549(Module, AutoCSR): ] self.comb += [ programmer.adpll.eq(self.adpll), - programmer.adpll_stb.eq(self.adpll_stb) + programmer.stb.eq(self.adpll_stb) ] self.gpio_enable.storage.attr.add("no_retiming")