forked from M-Labs/artiq
firmware: Sayma RTM FPGA bitstream loading prototype (#813).
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@ -1,4 +1,3 @@
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#![feature(asm, lang_items)]
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#![no_std]
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#[macro_use]
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@ -25,3 +24,5 @@ mod ad9154_reg;
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pub mod ad9154;
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#[cfg(has_allaki_atts)]
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pub mod hmc542;
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#[cfg(has_rtm_fpga_cfg)]
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pub mod rtm_fpga;
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@ -0,0 +1,46 @@
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use core::slice;
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use board::csr::rtm_fpga_cfg;
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use board::clock;
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const ADDR: *const u8 = 0x150000 as *const u8;
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pub fn program_bitstream() -> Result<(), ()> {
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unsafe {
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let length = *(ADDR as *const usize);
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let bitstream = slice::from_raw_parts(ADDR.offset(4) as *const u32, length / 4);
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debug!("resetting");
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rtm_fpga_cfg::divisor_write(15);
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rtm_fpga_cfg::program_write(1);
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clock::spin_us(1000);
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rtm_fpga_cfg::program_write(0);
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clock::spin_us(1000);
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while rtm_fpga_cfg::error_read() != 0 {}
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debug!("programming");
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for word in bitstream {
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rtm_fpga_cfg::data_write(*word);
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rtm_fpga_cfg::start_write(1);
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while rtm_fpga_cfg::busy_read() == 1 {}
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}
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debug!("finishing");
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loop {
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if rtm_fpga_cfg::error_read() != 0 {
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error!("programming error");
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return Err(())
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}
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if rtm_fpga_cfg::done_read() != 0 {
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debug!("done");
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return Ok(())
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}
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}
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}
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}
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@ -49,11 +49,20 @@ mod moninj;
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mod analyzer;
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fn startup() {
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log::set_max_level(log::LevelFilter::TRACE);
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logger_artiq::BufferLogger::with(|logger|
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logger.set_uart_log_level(log::LevelFilter::TRACE));
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board::clock::init();
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info!("ARTIQ runtime starting...");
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info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
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info!("gateware version {}", board::ident::read(&mut [0; 64]));
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#[cfg(has_rtm_fpga_cfg)]
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board_artiq::rtm_fpga::program_bitstream().expect("cannot program RTM FPGA");
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#[cfg(has_serwb_phy_amc)]
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board_artiq::serwb::wait_init();
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match config::read_str("log_level", |r| r.map(|s| s.parse())) {
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Ok(Ok(log_level_filter)) => {
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info!("log level set to {} by `log_level` config key",
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@ -72,9 +81,6 @@ fn startup() {
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_ => info!("UART log level set to INFO by default")
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}
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#[cfg(has_serwb_phy_amc)]
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board_artiq::serwb::wait_init();
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let t = board::clock::get_ms();
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info!("press 'e' to erase startup and idle kernels...");
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while board::clock::get_ms() < t + 1000 {
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@ -6,6 +6,7 @@ import subprocess
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import tempfile
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import shutil
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import re
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import io
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import atexit
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from functools import partial
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from collections import defaultdict
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@ -278,6 +279,7 @@ def main():
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"bootloader": ("spi1", 0x000000),
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"storage": ("spi1", 0x040000),
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"firmware": ("spi1", 0x050000),
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"rtm_gateware": ("spi1", 0x150000),
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},
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}[args.target]
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@ -309,18 +311,30 @@ def main():
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else:
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return os.path.join(args.srcbuild, *path_filename)
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def convert_gateware(bit_filename, prefix_size=False):
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bin_io = io.BytesIO()
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with open(bit_filename, "rb") as bit_file:
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bit2bin(bit_file, bin_io)
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bin_data = bin_io.getvalue()
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bin_handle, bin_filename = tempfile.mkstemp(
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prefix="artiq_", suffix="_" + os.path.basename(bit_filename))
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with open(bin_handle, "wb") as bin_file:
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if prefix_size:
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bin_file.write(len(bin_data).to_bytes(4, byteorder="big"))
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bin_file.write(bin_data)
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atexit.register(lambda: os.unlink(bin_filename))
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return bin_filename
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try:
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for action in args.action:
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if action == "gateware":
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gateware_bin = artifact_path(variant, "gateware", "top.bin")
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if not os.access(gateware_bin, os.R_OK):
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bin_handle, gateware_bin = tempfile.mkstemp()
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gateware_bit = artifact_path(variant, "gateware", "top.bit")
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with open(gateware_bit, "rb") as bit_file, open(bin_handle, "wb") as bin_file:
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bit2bin(bit_file, bin_file)
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atexit.register(lambda: os.unlink(gateware_bin))
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gateware_bin = convert_gateware(artifact_path(variant, "gateware", "top.bit"))
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programmer.write_binary(*config["gateware"], gateware_bin)
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if args.target == "sayma":
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rtm_gateware_bin = convert_gateware(artifact_path("rtm_gateware", "top.bit"))
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programmer.write_binary(*config["rtm_gateware"], rtm_gateware_bin)
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elif action == "bootloader":
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bootloader_bin = artifact_path(variant, "software", "bootloader", "bootloader.bin")
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programmer.write_binary(*config["bootloader"], bootloader_bin)
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