forked from M-Labs/artiq
dma test: no more rsys or rtio domains
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458bd8a927
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@ -203,11 +203,11 @@ class TestDMA(unittest.TestCase):
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run_simulation(tb[32], {"sys": [
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run_simulation(tb[32], {"sys": [
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do_dma(tb[32].dut, 0), monitor(32),
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do_dma(tb[32].dut, 0), monitor(32),
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(None for _ in range(70)),
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(None for _ in range(70)),
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]}, {"sys": 8, "rsys": 8, "rtio": 8, "rio": 8, "rio_phy": 8})
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]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8})
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run_simulation(tb[64], {"sys": [
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run_simulation(tb[64], {"sys": [
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do_dma(tb[64].dut, 0), monitor(64),
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do_dma(tb[64].dut, 0), monitor(64),
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(None for _ in range(70)),
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(None for _ in range(70)),
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]}, {"sys": 8, "rsys": 8, "rtio": 8, "rio": 8, "rio_phy": 8})
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]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8})
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correct_changes = [(timestamp + 11, channel)
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correct_changes = [(timestamp + 11, channel)
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for channel, timestamp, _, _ in test_writes_full_stack]
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for channel, timestamp, _, _ in test_writes_full_stack]
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