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fastino: monitor probe dacs

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Simon Renblad 2024-07-16 13:12:29 +08:00
parent 81106f3567
commit f8d7f57b14
1 changed files with 1 additions and 0 deletions
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artiq/gateware/rtio/phy/fastino.py
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@ -27,6 +27,7 @@ class Fastino(Module):
# dac data words # dac data words
dacs = [Signal(16) for i in range(32)] dacs = [Signal(16) for i in range(32)]
self.probes = dacs
header = Record([ header = Record([
("cfg", 4), ("cfg", 4),