forked from M-Labs/artiq
drtio: fix GTH clock domains
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1af21c0b29
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f8c8f3fe26
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@ -1,3 +1,6 @@
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from functools import reduce
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from operator import or_
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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@ -237,16 +240,10 @@ class GTH(Module, TransceiverInterface):
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TransceiverInterface.__init__(self, channel_interfaces)
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# rtio clock domain (clock from gth tx0, ored reset from all gth txs)
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self.comb += self.cd_rtio.clk.eq(ClockSignal("gth0_rtio_tx"))
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rtio_rst = Signal()
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for i in range(nchannels):
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rtio_rst.eq(rtio_rst | ResetSignal("gth" + str(i) + "rtio_tx"))
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new_rtio_rst = Signal()
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rtio_rst = new_rtio_rst
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self.comb += self.cd_rtio.rst.eq(rtio_rst)
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# rtio_rx clock domains
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self.comb += [
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self.cd_rtio.clk.eq(self.gths[master].cd_rtio_tx.clk),
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self.cd_rtio.rst.eq(reduce(or_, [gth.cd_rtio_tx.rst for gth in self.gths]))
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]
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for i in range(nchannels):
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self.comb += [
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getattr(self, "cd_rtio_rx" + str(i)).clk.eq(self.gths[i].cd_rtio_rx.clk),
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