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LLVMIRGenerator: fixup phis on expansion of ARTIQ instructions.

This commit is contained in:
whitequark 2015-08-09 20:24:16 +03:00
parent d4270cf66e
commit f7b64db8f4
1 changed files with 9 additions and 1 deletions
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10
artiq/compiler/transforms/llvm_ir_generator.py
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@ -17,6 +17,7 @@ class LLVMIRGenerator:
self.llmodule.data_layout = target.data_layout self.llmodule.data_layout = target.data_layout
self.llfunction = None self.llfunction = None
self.llmap = {} self.llmap = {}
self.llblock_map = {}
self.fixups = [] self.fixups = []
def llty_of_type(self, typ, bare=False, for_return=False): def llty_of_type(self, typ, bare=False, for_return=False):
@ -229,6 +230,13 @@ class LLVMIRGenerator:
assert llinsn is not None assert llinsn is not None
self.llmap[insn] = llinsn self.llmap[insn] = llinsn
# There is no 1:1 correspondence between ARTIQ and LLVM
# basic blocks, because sometimes we expand a single ARTIQ
# instruction so that the result spans several LLVM basic
# blocks. This only really matters for phis, which will
# use a different map.
self.llblock_map[block] = self.llbuilder.basic_block
# Fourth, fixup phis. # Fourth, fixup phis.
for fixup in self.fixups: for fixup in self.fixups:
fixup() fixup()
@ -241,7 +249,7 @@ class LLVMIRGenerator:
llinsn = self.llbuilder.phi(self.llty_of_type(insn.type), name=insn.name) llinsn = self.llbuilder.phi(self.llty_of_type(insn.type), name=insn.name)
def fixup(): def fixup():
for value, block in insn.incoming(): for value, block in insn.incoming():
llinsn.add_incoming(self.map(value), self.map(block)) llinsn.add_incoming(self.map(value), self.llblock_map[block])
self.fixups.append(fixup) self.fixups.append(fixup)
return llinsn return llinsn