forked from M-Labs/artiq
LLVMIRGenerator: fixup phis on expansion of ARTIQ instructions.
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@ -17,6 +17,7 @@ class LLVMIRGenerator:
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self.llmodule.data_layout = target.data_layout
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self.llfunction = None
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self.llmap = {}
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self.llblock_map = {}
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self.fixups = []
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def llty_of_type(self, typ, bare=False, for_return=False):
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@ -229,6 +230,13 @@ class LLVMIRGenerator:
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assert llinsn is not None
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self.llmap[insn] = llinsn
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# There is no 1:1 correspondence between ARTIQ and LLVM
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# basic blocks, because sometimes we expand a single ARTIQ
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# instruction so that the result spans several LLVM basic
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# blocks. This only really matters for phis, which will
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# use a different map.
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self.llblock_map[block] = self.llbuilder.basic_block
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# Fourth, fixup phis.
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for fixup in self.fixups:
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fixup()
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@ -241,7 +249,7 @@ class LLVMIRGenerator:
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llinsn = self.llbuilder.phi(self.llty_of_type(insn.type), name=insn.name)
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def fixup():
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for value, block in insn.incoming():
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llinsn.add_incoming(self.map(value), self.map(block))
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llinsn.add_incoming(self.map(value), self.llblock_map[block])
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self.fixups.append(fixup)
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return llinsn
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