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test_ad9910: robustify w.r.t. profile synchronization

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Signed-off-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
Robert Jördens 2018-11-14 07:41:24 +00:00
parent c3178c2cab
commit f77a75ab17
1 changed files with 4 additions and 0 deletions
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4
artiq/test/coredevice/test_ad9910.py
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@ -144,6 +144,10 @@ class AD9910Exp(EnvExperiment):
ftw = [0] * 8
for i in range(8):
self.dev.cpld.set_profile(i)
# If PROFILE is not alligned to SYNC_CLK a multi-bit change
# doesn't transfer cleanly. Use IO_UPDATE to load the profile
# again.
self.dev.cpld.io_update.pulse_mu(8)
ftw[i] = self.dev.read32(_AD9910_REG_FTW)
delay(100*us)
self.set_dataset("ftw", ftw)