forked from M-Labs/artiq
test_ad9910: robustify w.r.t. profile synchronization
Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -144,6 +144,10 @@ class AD9910Exp(EnvExperiment):
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ftw = [0] * 8
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for i in range(8):
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self.dev.cpld.set_profile(i)
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# If PROFILE is not alligned to SYNC_CLK a multi-bit change
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# doesn't transfer cleanly. Use IO_UPDATE to load the profile
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# again.
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self.dev.cpld.io_update.pulse_mu(8)
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ftw[i] = self.dev.read32(_AD9910_REG_FTW)
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delay(100*us)
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self.set_dataset("ftw", ftw)
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