forked from M-Labs/artiq
drtio: fix channel selection
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ad042de954
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@ -46,9 +46,10 @@ class IOT(Module):
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rt_packets.fifo_space.eq(channel.ofifo_depth - fifo.level))
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# FIFO write
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self.comb += fifo.we.eq(rt_packets.write_stb)
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self.comb += fifo.we.eq(rt_packets.write_stb
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& (rt_packets.write_channel == n))
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self.sync += \
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If(rt_packets.write_stb,
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If(fifo.we,
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If(rt_packets.write_overflow_ack,
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rt_packets.write_overflow.eq(0)),
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If(~fifo.writable, rt_packets.write_overflow.eq(1)),
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