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drtio: fix channel selection

This commit is contained in:
Sebastien Bourdeauducq 2016-10-26 00:33:21 +08:00
parent ad042de954
commit f763b519f4
1 changed files with 3 additions and 2 deletions
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5
artiq/gateware/drtio/iot.py
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@ -46,9 +46,10 @@ class IOT(Module):
rt_packets.fifo_space.eq(channel.ofifo_depth - fifo.level)) rt_packets.fifo_space.eq(channel.ofifo_depth - fifo.level))
# FIFO write # FIFO write
self.comb += fifo.we.eq(rt_packets.write_stb) self.comb += fifo.we.eq(rt_packets.write_stb
& (rt_packets.write_channel == n))
self.sync += \ self.sync += \
If(rt_packets.write_stb, If(fifo.we,
If(rt_packets.write_overflow_ack, If(rt_packets.write_overflow_ack,
rt_packets.write_overflow.eq(0)), rt_packets.write_overflow.eq(0)),
If(~fifo.writable, rt_packets.write_overflow.eq(1)), If(~fifo.writable, rt_packets.write_overflow.eq(1)),