From f62dc7e1d4aad251a2b5a17f878d9462273f1ae2 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sun, 6 Oct 2019 20:15:09 +0800
Subject: [PATCH] sayma: refactor JESD DAC channel groups

---
 artiq/firmware/libboard_artiq/jdcg.rs | 37 +++++++++++++++++++++++++++
 artiq/firmware/libboard_artiq/lib.rs  |  6 +++--
 artiq/gateware/targets/sayma_amc.py   | 33 ++++++++++++------------
 3 files changed, 58 insertions(+), 18 deletions(-)
 create mode 100644 artiq/firmware/libboard_artiq/jdcg.rs

diff --git a/artiq/firmware/libboard_artiq/jdcg.rs b/artiq/firmware/libboard_artiq/jdcg.rs
new file mode 100644
index 000000000..b93d28336
--- /dev/null
+++ b/artiq/firmware/libboard_artiq/jdcg.rs
@@ -0,0 +1,37 @@
+use board_misoc::csr;
+
+pub fn jesd_reset(reset: bool) {
+    unsafe {
+        csr::jesd_crg::jreset_write(if reset {1}  else {0});
+    }
+}
+
+fn jesd_enable(dacno: u8, en: bool) {
+    unsafe {
+        (csr::JDCG[dacno as usize].jesd_control_enable_write)(if en {1} else {0})
+    }
+}
+
+fn jesd_ready(dacno: u8) -> bool {
+    unsafe {
+        (csr::JDCG[dacno as usize].jesd_control_ready_read)() != 0
+    }
+}
+
+fn jesd_prbs(dacno: u8, en: bool) {
+    unsafe {
+        (csr::JDCG[dacno as usize].jesd_control_prbs_config_write)(if en {0b01} else {0b00})
+    }
+}
+
+fn jesd_stpl(dacno: u8, en: bool) {
+    unsafe {
+        (csr::JDCG[dacno as usize].jesd_control_stpl_enable_write)(if en {1} else {0})
+    }
+}
+
+fn jesd_jsync(dacno: u8) -> bool {
+    unsafe {
+        (csr::JDCG[dacno as usize].jesd_control_jsync_read)() != 0
+    }
+}
diff --git a/artiq/firmware/libboard_artiq/lib.rs b/artiq/firmware/libboard_artiq/lib.rs
index 241002879..24594414f 100644
--- a/artiq/firmware/libboard_artiq/lib.rs
+++ b/artiq/firmware/libboard_artiq/lib.rs
@@ -40,8 +40,10 @@ pub mod hmc830_7043;
 mod ad9154_reg;
 #[cfg(has_ad9154)]
 pub mod ad9154;
-#[cfg(has_ad9154)]
-pub mod jesd204sync;
+/* TODO: #[cfg(has_jdcg)]
+pub mod jesd204sync; */
+#[cfg(has_jdcg)]
+pub mod jdcg;
 #[cfg(has_allaki_atts)]
 pub mod hmc542;
 
diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index 5d70ce2d2..be74a43f6 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -162,7 +162,8 @@ class SatelliteBase(BaseSoC):
         self.csr_devices.append("routing_table")
 
 
-class AD9154(Module, AutoCSR):
+# JESD204 DAC Channel Group
+class JDCG(Module, AutoCSR):
     def __init__(self, platform, sys_crg, jesd_crg, dac):
         self.submodules.jesd = jesd204_tools.UltrascaleTX(
             platform, sys_crg, jesd_crg, dac)
@@ -175,7 +176,7 @@ class AD9154(Module, AutoCSR):
             self.sync.jesd += conv.eq(Cat(ch.o))
 
 
-class AD9154NoSAWG(Module, AutoCSR):
+class JDCGNoSAWG(Module, AutoCSR):
     def __init__(self, platform, sys_crg, jesd_crg, dac):
         self.submodules.jesd = jesd204_tools.UltrascaleTX(
             platform, sys_crg, jesd_crg, dac)
@@ -256,23 +257,23 @@ class Satellite(SatelliteBase):
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
 
-        self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(
+        self.submodules.jesd_crg = jesd204_tools.UltrascaleCRG(
             platform, use_rtio_clock=True)
         if with_sawg:
-            cls = AD9154
+            cls = JDCG
         else:
-            cls = AD9154NoSAWG
-        self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
-        self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
-        self.csr_devices.append("ad9154_crg")
-        self.csr_devices.append("ad9154_0")
-        self.csr_devices.append("ad9154_1")
-        self.config["HAS_AD9154"] = None
-        self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
+            cls = JDCGNoSAWG
+        self.submodules.jdcg_0 = cls(platform, self.crg, self.jesd_crg, 0)
+        self.submodules.jdcg_1 = cls(platform, self.crg, self.jesd_crg, 1)
+        self.csr_devices.append("jesd_crg")
+        self.csr_devices.append("jdcg_0")
+        self.csr_devices.append("jdcg_1")
+        self.config["HAS_JDCG"] = None
+        self.add_csr_group("jdcg", ["jdcg_0", "jdcg_1"])
         self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
         rtio_channels.extend(rtio.Channel.from_phy(phy)
-                                for sawg in self.ad9154_0.sawgs +
-                                            self.ad9154_1.sawgs
+                                for sawg in self.jdcg_0.sawgs +
+                                            self.jdcg_1.sawgs
                                 for phy in sawg.phys)
 
         self.add_rtio(rtio_channels)
@@ -280,8 +281,8 @@ class Satellite(SatelliteBase):
         self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
             platform.request("dac_sysref"), self.rtio_tsc.coarse_ts)
         self.csr_devices.append("sysref_sampler")
-        self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref)
-        self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref)
+        self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref)
+        self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref)
 
 
 class SimpleSatellite(SatelliteBase):