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drtio: fix ad9154 extension registration

This commit is contained in:
Sebastien Bourdeauducq 2017-01-30 10:59:22 +08:00
parent 3aced46b19
commit f6024b6c9a
2 changed files with 2 additions and 2 deletions
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2
artiq/gateware/targets/kc705_drtio_master.py
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@ -53,7 +53,7 @@ class Master(MiniSoC, AMPSoC):
elif cfg == "sawg_3g": elif cfg == "sawg_3g":
# 3Gb link, 150MHz RTIO clock # 3Gb link, 150MHz RTIO clock
# with SAWG on local RTIO and AD9154-FMC-EBZ # with SAWG on local RTIO and AD9154-FMC-EBZ
platform.register_extension(ad9154_fmc_ebz) platform.add_extension(ad9154_fmc_ebz)
self.submodules.transceiver = gtx_7series.GTX_3G( self.submodules.transceiver = gtx_7series.GTX_3G(
clock_pads=platform.request("ad9154_refclk"), clock_pads=platform.request("ad9154_refclk"),
tx_pads=tx_pads, tx_pads=tx_pads,

2
artiq/gateware/targets/kc705_drtio_satellite.py
View File

@ -169,7 +169,7 @@ class Satellite(BaseSoC):
elif cfg == "sawg_3g": elif cfg == "sawg_3g":
# 3Gb link, 150MHz RTIO clock # 3Gb link, 150MHz RTIO clock
# with SAWG on local RTIO and AD9154-FMC-EBZ # with SAWG on local RTIO and AD9154-FMC-EBZ
platform.register_extension(ad9154_fmc_ebz) platform.add_extension(ad9154_fmc_ebz)
self.submodules.transceiver = gtx_7series.GTX_3G( self.submodules.transceiver = gtx_7series.GTX_3G(
clock_pads=platform.request("ad9154_refclk"), clock_pads=platform.request("ad9154_refclk"),
tx_pads=tx_pads, tx_pads=tx_pads,