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sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant

This commit is contained in:
Sebastien Bourdeauducq 2019-01-02 16:41:11 +08:00
parent e85df13127
commit f5cda3689e
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/targets/sayma_amc.py
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@ -279,7 +279,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
] ]
self.submodules.drtio_transceiver = gth_ultrascale.GTH( self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=self.ad9154_crg.refclk, clock_pads=self.ad9154_crg.refclk,
data_pads=[platform.request("sfp", i) for i in range(2)], data_pads=[platform.request("sata")] + [platform.request("sfp", i) for i in range(2)],
sys_clk_freq=self.clk_freq, sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq) rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")
@ -290,7 +290,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
drtioaux_csr_group = [] drtioaux_csr_group = []
drtioaux_memory_group = [] drtioaux_memory_group = []
drtio_cri = [] drtio_cri = []
for i in range(2): for i in range(3):
core_name = "drtio" + str(i) core_name = "drtio" + str(i)
coreaux_name = "drtioaux" + str(i) coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem" memory_name = "drtioaux" + str(i) + "_mem"