forked from M-Labs/artiq
test/full_stack: add exception test
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parent
d10112688f
commit
f510d3aa49
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@ -52,7 +52,7 @@ class _PulseLogger(AutoContext):
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self.print_off(int(now()))
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class _PulseTest(AutoContext):
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class _Pulses(AutoContext):
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def build(self):
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for name in "a", "b", "c", "d":
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pl = _PulseLogger(self, name=name)
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@ -70,6 +70,52 @@ class _PulseTest(AutoContext):
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self.d.pulse(400+i, 20*us)
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class _MyException(Exception):
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pass
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class _Exceptions(AutoContext):
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parameters = "trace"
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@kernel
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def run(self):
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for i in range(10):
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self.trace.append(i)
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if i == 4:
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try:
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self.trace.append(10)
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try:
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self.trace.append(11)
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break
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except:
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pass
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else:
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self.trace.append(12)
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try:
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self.trace.append(13)
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except:
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pass
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except _MyException:
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self.trace.append(14)
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for i in range(4):
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try:
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self.trace.append(100)
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if i == 1:
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raise _MyException
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elif i == 2:
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raise IndexError
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except (TypeError, IndexError):
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self.trace.append(101)
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raise
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except:
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self.trace.append(102)
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else:
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self.trace.append(103)
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finally:
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self.trace.append(104)
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class SimCompareCase(unittest.TestCase):
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def test_primes(self):
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l_device, l_host = [], []
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@ -80,7 +126,15 @@ class SimCompareCase(unittest.TestCase):
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def test_pulses(self):
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# TODO: compare results on host and device
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# (this requires better unit management in the compiler)
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_run_on_device(_PulseTest)
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_run_on_device(_Pulses)
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def test_exceptions(self):
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t_device, t_host = [], []
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with self.assertRaises(IndexError):
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_run_on_device(_Exceptions, trace=t_device)
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with self.assertRaises(IndexError):
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_run_on_host(_Exceptions, trace=t_host)
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self.assertEqual(t_device, t_host)
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class _RTIOLoopback(AutoContext):
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