forked from M-Labs/artiq
rtio: always read full DMA sequence
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c413d95b49
commit
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@ -350,12 +350,12 @@ class DMA(Module):
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.enable.re & self.enable.r, NextState("FLOWING"))
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If(self.enable.re, NextState("FLOWING"))
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)
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fsm.act("FLOWING",
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self.enable.w.eq(1),
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flow_enable.eq(1),
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If(self.slicer.end_marker_found | (self.enable.re & ~self.enable.r),
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If(self.slicer.end_marker_found,
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NextState("FLUSH")
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)
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)
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