forked from M-Labs/artiq
rtio/sed: fix seqn_width
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@ -21,10 +21,10 @@ def fifo_payload(channels):
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return layout
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def seqn_width(lane_count, fifo_width):
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def seqn_width(lane_count, fifo_depth):
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# There must be a unique sequence number for every possible event in every FIFO.
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# Plus 2 bits to detect and handle wraparounds.
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return bits_for(lane_count*fifo_size-1) + 2
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return bits_for(lane_count*fifo_depth-1) + 2
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def fifo_ingress(seqn_width, layout_payload):
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