forked from M-Labs/artiq
pipistrello: drop ttls on pmod, add leds back in
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@ -196,19 +196,13 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
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for led_number in range(2):
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for led_number in range(4):
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phy = ttl_simple.Output(platform.request("user_led", led_number))
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phy = ttl_simple.Output(platform.request("user_led", led_number))
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
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spi_pins = self.platform.request("pmod_extended_spi", 0)
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spi_pins = self.platform.request("pmod_extended_spi", 0)
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for i, p in enumerate((spi_pins.int, spi_pins.rst)):
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phy = ttl_simple.Inout(p)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4,
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ofifo_depth=4))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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phy = ttl_simple.ClockGen(platform.request("ttl", 15))
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phy = ttl_simple.ClockGen(platform.request("ttl", 15))
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@ -128,9 +128,9 @@ When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are
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+--------------+------------+--------------+
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+--------------+------------+--------------+
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| 19 | USER_LED_2 | Output |
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| 19 | USER_LED_2 | Output |
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+--------------+------------+--------------+
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+--------------+------------+--------------+
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| 20 | PMOD_4 | Input+Output |
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| 20 | USER_LED_3 | Output |
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+--------------+------------+--------------+
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+--------------+------------+--------------+
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| 21 | PMOD_5 | Input+Output |
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| 21 | USER_LED_4 | Output |
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+--------------+------------+--------------+
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+--------------+------------+--------------+
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| 22 | TTL15 | Clock |
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| 22 | TTL15 | Clock |
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+--------------+------------+--------------+
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+--------------+------------+--------------+
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