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runtime: rt2wb_input -> rtio_input_data

This commit is contained in:
Robert Jördens 2016-03-01 19:21:50 +01:00
parent baf7b0dcf2
commit f30dc4b39e
9 changed files with 54 additions and 62 deletions

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@ -1,7 +0,0 @@
from artiq.language.core import *
from artiq.language.types import *
@syscall
def rt2wb_input(channel: TInt32) -> TInt32:
raise NotImplementedError("syscall not simulated")

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@ -11,3 +11,8 @@ def rtio_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
@syscall
def rtio_input_timestamp(timeout_mu: TInt64, channel: TInt32) -> TInt64:
raise NotImplementedError("syscall not simulated")
@syscall
def rtio_input_data(channel: TInt32) -> TInt32:
raise NotImplementedError("syscall not simulated")

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@ -1,8 +1,7 @@
from artiq.language.core import (kernel, seconds_to_mu, now_mu,
delay_mu, int)
from artiq.language.units import MHz
from artiq.coredevice.rtio import rtio_output as rt2wb_output
from artiq.coredevice.rt2wb import rt2wb_input
from artiq.coredevice.rtio import rtio_output, rtio_input_data
SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
@ -50,48 +49,48 @@ class SPIMaster:
@kernel
def set_config_mu(self, flags=0, write_div=6, read_div=6):
rt2wb_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
((write_div - 2) << 16) | ((read_div - 2) << 24))
rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
((write_div - 2) << 16) | ((read_div - 2) << 24))
self.write_period_mu = int(write_div*self.ref_period_mu)
self.read_period_mu = int(read_div*self.ref_period_mu)
delay_mu(3*self.ref_period_mu)
@kernel
def set_xfer(self, chip_select=0, write_length=0, read_length=0):
rt2wb_output(now_mu(), self.channel, SPI_XFER_ADDR,
chip_select | (write_length << 16) | (read_length << 24))
rtio_output(now_mu(), self.channel, SPI_XFER_ADDR,
chip_select | (write_length << 16) | (read_length << 24))
self.xfer_period_mu = int(write_length*self.write_period_mu +
read_length*self.read_period_mu)
delay_mu(3*self.ref_period_mu)
@kernel
def write(self, data):
rt2wb_output(now_mu(), self.channel, SPI_DATA_ADDR, data)
rtio_output(now_mu(), self.channel, SPI_DATA_ADDR, data)
delay_mu(3*self.ref_period_mu)
@kernel
def read_async(self):
# every read_async() must be matched by an input_async()
rt2wb_output(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
rtio_output(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
delay_mu(3*self.ref_period_mu)
@kernel
def input_async(self):
# matches the preeeding read_async()
return rt2wb_input(self.channel)
return rtio_input_data(self.channel)
@kernel
def read_sync(self):
rt2wb_output(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
return rt2wb_input(self.channel)
rtio_output(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
return rtio_input_data(self.channel)
@kernel
def _get_xfer_sync(self):
rt2wb_output(now_mu(), self.channel, SPI_XFER_ADDR | SPI_RT2WB_READ, 0)
return rt2wb_input(self.channel)
rtio_output(now_mu(), self.channel, SPI_XFER_ADDR | SPI_RT2WB_READ, 0)
return rtio_input_data(self.channel)
@kernel
def _get_config_sync(self):
rt2wb_output(now_mu(), self.channel, SPI_CONFIG_ADDR | SPI_RT2WB_READ,
0)
return rt2wb_input(self.channel)
rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR | SPI_RT2WB_READ,
0)
return rtio_input_data(self.channel)

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@ -7,7 +7,7 @@ OBJECTS := isr.o clock.o rtiocrg.o flash_storage.o mailbox.o \
session.o log.o analyzer.o moninj.o net_server.o bridge_ctl.o \
ksupport_data.o kloader.o test_mode.o main.o
OBJECTS_KSUPPORT := ksupport.o artiq_personality.o mailbox.o \
bridge.o rtio.o rt2wb.o dds.o
bridge.o rtio.o dds.o
CFLAGS += -I$(LIBALLOC_DIRECTORY) \
-I$(MISOC_DIRECTORY)/software/include/dyld \

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@ -15,7 +15,6 @@
#include "artiq_personality.h"
#include "dds.h"
#include "rtio.h"
#include "rt2wb.h"
double round(double x);
@ -111,14 +110,13 @@ static const struct symbol runtime_exports[] = {
{"rtio_log", &rtio_log},
{"rtio_output", &rtio_output},
{"rtio_input_timestamp", &rtio_input_timestamp},
{"rtio_input_data", &rtio_input_data},
{"dds_init", &dds_init},
{"dds_batch_enter", &dds_batch_enter},
{"dds_batch_exit", &dds_batch_exit},
{"dds_set", &dds_set},
{"rt2wb_input", &rt2wb_input},
{"cache_get", &cache_get},
{"cache_put", &cache_put},

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@ -1,26 +0,0 @@
#include <generated/csr.h>
#include "artiq_personality.h"
#include "rtio.h"
#include "rt2wb.h"
unsigned int rt2wb_input(int channel)
{
unsigned int data;
int status;
rtio_chan_sel_write(channel);
while((status = rtio_i_status_read())) {
if(status & RTIO_I_STATUS_OVERFLOW) {
rtio_i_overflow_reset_write(1);
artiq_raise_from_c("RTIOOverflow",
"RT2WB input overflow on channel {0}",
channel, 0, 0);
}
}
data = rtio_i_data_read();
rtio_i_re_write(1);
return data;
}

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@ -1,9 +0,0 @@
#ifndef __RT2WB_H
#define __RT2WB_H
#include "rtio.h"
unsigned int rt2wb_input(int channel);
#endif /* __RT2WB_H */

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@ -91,6 +91,27 @@ long long int rtio_input_timestamp(long long int timeout, int channel)
}
unsigned int rtio_input_data(int channel)
{
unsigned int data;
int status;
rtio_chan_sel_write(channel);
while((status = rtio_i_status_read())) {
if(status & RTIO_I_STATUS_OVERFLOW) {
rtio_i_overflow_reset_write(1);
artiq_raise_from_c("RTIOOverflow",
"RTIO input overflow on channel {0}",
channel, 0, 0);
}
}
data = rtio_i_data_read();
rtio_i_re_write(1);
return data;
}
void rtio_log_va(long long int timestamp, const char *fmt, va_list args)
{
// This executes on the kernel CPU's stack, which is specifically designed

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@ -19,6 +19,17 @@ void rtio_log(long long int timestamp, const char *format, ...);
void rtio_log_va(long long int timestamp, const char *format, va_list args);
void rtio_output(long long int timestamp, int channel, unsigned int address,
unsigned int data);
/*
* Waits at least until timeout and returns the timestamp of the first
* input event on the chanel, -1 if there was no event.
*/
long long int rtio_input_timestamp(long long int timeout, int channel);
/*
* Assumes that there is or will be an event in the channel and returns only
* its data.
*/
unsigned int rtio_input_data(int channel);
#endif /* __RTIO_H */