forked from M-Labs/artiq
wrpll.ddmtd: remove CSRs from DDMTD
We will gather then from the collector output so we can get all tags on the same cycle
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@ -88,10 +88,8 @@ class DDMTDDeglitcherFirstEdge(Module):
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]
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class DDMTD(Module, AutoCSR):
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class DDMTD(Module):
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def __init__(self, counter, input_signal):
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self.arm = CSR()
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self.tag = CSRStatus(len(counter))
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# in helper clock domain
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self.h_tag = Signal(len(counter))
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@ -110,24 +108,6 @@ class DDMTD(Module, AutoCSR):
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)
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]
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tag_update_ps = PulseSynchronizer("helper", "sys")
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self.submodules += tag_update_ps
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self.comb += tag_update_ps.i.eq(self.h_tag_update)
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tag_update = Signal()
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self.sync += tag_update.eq(tag_update_ps.o)
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tag = Signal(len(counter))
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self.h_tag.attr.add("no_retiming")
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self.specials += MultiReg(self.h_tag, tag)
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self.sync += [
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If(self.arm.re & self.arm.r, self.arm.w.eq(1)),
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If(tag_update,
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If(self.arm.w, self.tag.status.eq(tag)),
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self.arm.w.eq(0),
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)
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]
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class Collector(Module):
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"""Generates loop filter inputs from DDMTD outputs.
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