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wrpll.ddmtd: remove CSRs from DDMTD 

We will gather then from the collector output so we can get all tags on the same cycle
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hartytp 2020-10-06 15:59:05 +01:00 committed by Sebastien Bourdeauducq
parent 85bb641917
commit f2f942a8b4
1 changed files with 1 additions and 21 deletions
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22
artiq/gateware/drtio/wrpll/ddmtd.py
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@ -88,10 +88,8 @@ class DDMTDDeglitcherFirstEdge(Module):
] ]
class DDMTD(Module, AutoCSR): class DDMTD(Module):
def __init__(self, counter, input_signal): def __init__(self, counter, input_signal):
self.arm = CSR()
self.tag = CSRStatus(len(counter))
# in helper clock domain # in helper clock domain
self.h_tag = Signal(len(counter)) self.h_tag = Signal(len(counter))
@ -110,24 +108,6 @@ class DDMTD(Module, AutoCSR):
) )
] ]
tag_update_ps = PulseSynchronizer("helper", "sys")
self.submodules += tag_update_ps
self.comb += tag_update_ps.i.eq(self.h_tag_update)
tag_update = Signal()
self.sync += tag_update.eq(tag_update_ps.o)
tag = Signal(len(counter))
self.h_tag.attr.add("no_retiming")
self.specials += MultiReg(self.h_tag, tag)
self.sync += [
If(self.arm.re & self.arm.r, self.arm.w.eq(1)),
If(tag_update,
If(self.arm.w, self.tag.status.eq(tag)),
self.arm.w.eq(0),
)
]
class Collector(Module): class Collector(Module):
"""Generates loop filter inputs from DDMTD outputs. """Generates loop filter inputs from DDMTD outputs.