forked from M-Labs/artiq
drtio: add aux receiver (untested)
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8a48d6d66e
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117
artiq/gateware/drtio/aux_controller.py
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117
artiq/gateware/drtio/aux_controller.py
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from migen import *
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from migen.fhdl.simplify import FullMemoryWE
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.interconnect import wishbone
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max_packet = 1024
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class Transmitter(Module, AutoCSR):
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def __init__(self, link_layer, min_mem_dw):
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# TODO
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class Receiver(Module, AutoCSR):
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def __init__(self, link_layer, min_mem_dw):
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self.aux_rx_length = CSRStatus(bits_for(max_packet))
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self.aux_rx_present = CSR()
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self.aux_rx_error = CSR()
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ll_dw = len(link_layer.rx_aux_data)
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mem_dw = max(min_mem_dw, ll_dw)
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self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8))
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converter = stream.Converter(ll_dw, mem_dw)
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self.submodules += converter
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self.sync.rtio_rx += [
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converter.sink.stb.eq(link_layer.rx_aux_frame),
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converter.sink.data.eq(link_layer.rx_aux_data)
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]
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self.comb += converter.sink.eop.eq(~link_layer.rx_aux_frame)
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mem_port = self.mem.get_port(write_capable=True, clock_domain="rtio_rx")
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self.specials += mem_port
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frame_counter_nbits = bits_for(max_packet) - log2_int(mem_dw//8)
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frame_counter = Signal(frame_counter_nbits)
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self.comb += [
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mem_port.adr.eq(frame_counter),
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mem_port.dat_w.eq(link_layer.rx_aux_data)
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]
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frame_counter.attr.add("no_retiming")
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frame_counter_sys = Signal(frame_counter_nbits)
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self.specials += MultiReg(frame_counter, frame_counter_sys)
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self.comb += aux_rx_length.status.eq(frame_counter_sys << log2_int(mem_dw//8))
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signal_frame = PulseSynchronizer("rtio_rx", "sys")
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frame_ack = PulseSynchronizer("sys", "rtio_rx")
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signal_error = PulseSynchronizer("rtio_rx", "sys")
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self.submodules += signal_frame, signal_error
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self.sync += [
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If(self.aux_rx_present.re, self.aux_rx_present.w.eq(0)),
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If(signal_frame.o, self.aux_rx_present.w.eq(1)),
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If(self.aux_rx_error.re, self.aux_rx_error.w.eq(0)),
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If(signal_error.o, self.aux_rx_error.eq(1))
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]
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self.comb += frame_ack.i.eq(self.aux_rx_present.re)
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fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="IDLE"))
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self.submodules += fsm
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rx_aux_frame_r = Signal()
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self.sync.rtio_rx += rx_aux_frame_r.eq(link_layer.rx_aux_frame)
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fsm.act("IDLE",
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If(link_layer.rx_aux_frame & ~rx_aux_frame_r,
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NextValue(frame_counter, frame_counter + 1),
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mem_port.we.eq(1),
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NextState("FRAME")
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).Else(
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NextValue(frame_counter, 0)
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)
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)
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fsm.act("FRAME",
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If(link_layer.rx_aux_frame,
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NextValue(frame_counter, frame_counter + 1),
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mem_port.we.eq(1),
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If(frame_counter == max_packet,
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mem_port.we.eq(0),
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signal_error.i.eq(1),
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NextState("IDLE") # remainder of the frame discarded
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)
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).Else(
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signal_frame.i.eq(1),
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NextState("WAIT_ACK")
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)
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)
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fsm.act("WAIT_ACK",
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If(frame_ack.o,
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NextValue(frame_counter, 0),
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NextState("IDLE")
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),
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If(link_layer.rx_aux_frame, signal_error.i.eq(1))
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)
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class AuxController(Module):
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def __init__(self, link_layer):
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self.bus = wishbone.Interface()
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self.submodules.transmitter = Transmitter(link_layer, len(self.bus.dat_w))
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self.submodules.receiver = Receiver(link_layer, len(self.bus.dat_w))
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# TODO: FullMemoryWE should be applied by migen.build
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tx_sdram_if = FullMemoryWE()(self.transmitter.mem, read_only=False)
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rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True)
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wsb = log2_int(len(self.bus.dat_w)//8)
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decoder = wishbone.Decoder(self.bus,
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[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if)
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(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if)],
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register=True)
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self.submodules += tx_sdram_if, rx_sdram_if, decoder
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def get_csrs(self):
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return self.transmitter.get_csrs() + self.receiver.get_csrs()
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