diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py
index 03f479e03..dd1e23f55 100644
--- a/artiq/gateware/rtio/dma.py
+++ b/artiq/gateware/rtio/dma.py
@@ -12,9 +12,7 @@ def _reverse_bytes(s, g):
 
 
 class WishboneReader(Module):
-    def __init__(self, bus=None):
-        if bus is None:
-            bus = wishbone.Interface
+    def __init__(self):
         self.bus = bus
 
         aw = len(bus.adr)