forked from M-Labs/artiq
re-impl ADC using general access methods
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9e1447d104
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f2694f25eb
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@ -183,6 +183,20 @@ class ADC:
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@kernel
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def read_id(self) -> TInt32:
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return self.read16(_AD4115_REG_ID)
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@kernel
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def reset(self):
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# Hold DIN high for 64 cycles
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# However, asserting CS right after the 64 cycles seems to interrupt
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# the start-up sequence.
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self.bus.set_config_mu(ADC_SPI_CONFIG, 32, SPIT_ADC_WR, CS_ADC)
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self.bus.write(0xffffffff)
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self.bus.write(0xffffffff)
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 32, SPIT_ADC_WR, CS_ADC)
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self.bus.write(0xffffffff)
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@kernel
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def read8(self, addr: TInt32) -> TInt32:
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self.bus.set_config_mu(
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@ -225,6 +239,13 @@ class ADC:
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ADC_SPI_CONFIG | spi.SPI_END, 32, SPIT_ADC_WR, CS_ADC)
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self.bus.write(addr << 24 | (data & 0xffffff))
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@kernel
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def read_ch(self, channel: TInt32) -> TFloat:
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# Always configure Profile 0 for single conversion
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self.write16(_AD4115_REG_CH0, 0x8000 | ((channel * 2 + 1) << 4))
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self.write16(_AD4115_REG_SETUPCON0, 0x1300)
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self.write16(_AD4115_REG_ADCMODE, 0x8010)
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delay(100*us)
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adc_code = self.read24(_AD4115_REG_DATA)
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return ((adc_code / (1 << 23)) - 1) * 2.5 / 0.1
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