forked from M-Labs/artiq
drtio: increase A7 clock aligner check period
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@ -689,7 +689,7 @@ class GTPSingle(Module):
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self.comb += decoders[i].input.eq(rxdata[10*i:10*(i+1)])
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# clock alignment
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clock_aligner = BruteforceClockAligner(0b0101111100, rtio_clk_freq, check_period=10e-3)
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clock_aligner = BruteforceClockAligner(0b0101111100, rtio_clk_freq, check_period=12e-3)
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self.submodules += clock_aligner
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self.comb += [
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clock_aligner.rxdata.eq(rxdata),
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