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drtio: increase A7 clock aligner check period

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This commit is contained in:
Sebastien Bourdeauducq 2018-02-20 18:50:35 +08:00
parent 738654c783
commit f060d6e1b3
1 changed files with 1 additions and 1 deletions
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artiq/gateware/drtio/transceiver/gtp_7series.py
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@ -689,7 +689,7 @@ class GTPSingle(Module):
self.comb += decoders[i].input.eq(rxdata[10*i:10*(i+1)])
# clock alignment
clock_aligner = BruteforceClockAligner(0b0101111100, rtio_clk_freq, check_period=10e-3)
clock_aligner = BruteforceClockAligner(0b0101111100, rtio_clk_freq, check_period=12e-3)
self.submodules += clock_aligner
self.comb += [
clock_aligner.rxdata.eq(rxdata),